{"id":809655,"url":"http://patchwork.ozlabs.org/api/patches/809655/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-33-git-send-email-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1504527967-29248-33-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-04T12:26:03","name":"[PULL,32/36] target/arm: Implement new do_transaction_failed hook","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"3623aaca5b060a4051ec7061b95410aa8acaa5b6","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-33-git-send-email-peter.maydell@linaro.org/mbox/","series":[{"id":1366,"url":"http://patchwork.ozlabs.org/api/series/1366/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1366","date":"2017-09-04T12:25:36","name":"[PULL,01/36] target/arm: Use MMUAccessType enum rather than int","version":1,"mbox":"http://patchwork.ozlabs.org/series/1366/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/809655/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/809655/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xm8m83D4xz9sNr\n\tfor ;\n\tMon, 4 Sep 2017 22:48:40 +1000 (AEST)","from localhost ([::1]:59649 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1doqnu-0004nQ-FV\n\tfor incoming@patchwork.ozlabs.org; Mon, 04 Sep 2017 08:48:38 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:52911)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1doqSi-0005Dg-Jr\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:53 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1doqSV-0004yz-5K\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:44 -0400","from orth.archaic.org.uk ([2001:8b0:1d0::2]:37136)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1doqSU-0004xA-Th\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:31 -0400","from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from ) id 1doqST-0005cx-KQ\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 13:26:29 +0100"],"From":"Peter Maydell ","To":"qemu-devel@nongnu.org","Date":"Mon, 4 Sep 2017 13:26:03 +0100","Message-Id":"<1504527967-29248-33-git-send-email-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>","References":"<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2001:8b0:1d0::2","Subject":"[Qemu-devel] [PULL 32/36] target/arm: Implement new\n\tdo_transaction_failed hook","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"Implement the new do_transaction_failed hook for ARM, which should\ncause the CPU to take a prefetch abort or data abort.\n\nSigned-off-by: Peter Maydell \nReviewed-by: Richard Henderson \nReviewed-by: Edgar E. Iglesias \n---\n target/arm/internals.h | 10 ++++++++++\n target/arm/cpu.c | 1 +\n target/arm/op_helper.c | 43 +++++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 54 insertions(+)","diff":"diff --git a/target/arm/internals.h b/target/arm/internals.h\nindex 461f558..b100da9 100644\n--- a/target/arm/internals.h\n+++ b/target/arm/internals.h\n@@ -472,6 +472,16 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,\n MMUAccessType access_type,\n int mmu_idx, uintptr_t retaddr);\n \n+/* arm_cpu_do_transaction_failed: handle a memory system error response\n+ * (eg \"no device/memory present at address\") by raising an external abort\n+ * exception\n+ */\n+void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,\n+ vaddr addr, unsigned size,\n+ MMUAccessType access_type,\n+ int mmu_idx, MemTxAttrs attrs,\n+ MemTxResult response, uintptr_t retaddr);\n+\n /* Call the EL change hook if one has been registered */\n static inline void arm_call_el_change_hook(ARMCPU *cpu)\n {\ndiff --git a/target/arm/cpu.c b/target/arm/cpu.c\nindex 41ae6ba..a323e6b 100644\n--- a/target/arm/cpu.c\n+++ b/target/arm/cpu.c\n@@ -1667,6 +1667,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)\n #else\n cc->do_interrupt = arm_cpu_do_interrupt;\n cc->do_unaligned_access = arm_cpu_do_unaligned_access;\n+ cc->do_transaction_failed = arm_cpu_do_transaction_failed;\n cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;\n cc->asidx_from_attrs = arm_asidx_from_attrs;\n cc->vmsd = &vmstate_arm_cpu;\ndiff --git a/target/arm/op_helper.c b/target/arm/op_helper.c\nindex 8f6db80..d1bca46 100644\n--- a/target/arm/op_helper.c\n+++ b/target/arm/op_helper.c\n@@ -229,6 +229,49 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,\n deliver_fault(cpu, vaddr, access_type, fsr, fsc, &fi);\n }\n \n+/* arm_cpu_do_transaction_failed: handle a memory system error response\n+ * (eg \"no device/memory present at address\") by raising an external abort\n+ * exception\n+ */\n+void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,\n+ vaddr addr, unsigned size,\n+ MMUAccessType access_type,\n+ int mmu_idx, MemTxAttrs attrs,\n+ MemTxResult response, uintptr_t retaddr)\n+{\n+ ARMCPU *cpu = ARM_CPU(cs);\n+ CPUARMState *env = &cpu->env;\n+ uint32_t fsr, fsc;\n+ ARMMMUFaultInfo fi = {};\n+ ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx);\n+\n+ if (retaddr) {\n+ /* now we have a real cpu fault */\n+ cpu_restore_state(cs, retaddr);\n+ }\n+\n+ /* The EA bit in syndromes and fault status registers is an\n+ * IMPDEF classification of external aborts. ARM implementations\n+ * usually use this to indicate AXI bus Decode error (0) or\n+ * Slave error (1); in QEMU we follow that.\n+ */\n+ fi.ea = (response != MEMTX_DECODE_ERROR);\n+\n+ /* The fault status register format depends on whether we're using\n+ * the LPAE long descriptor format, or the short descriptor format.\n+ */\n+ if (arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) {\n+ /* long descriptor form, STATUS 0b010000: synchronous ext abort */\n+ fsr = (fi.ea << 12) | (1 << 9) | 0x10;\n+ } else {\n+ /* short descriptor form, FSR 0b01000 : synchronous ext abort */\n+ fsr = (fi.ea << 12) | 0x8;\n+ }\n+ fsc = 0x10;\n+\n+ deliver_fault(cpu, addr, access_type, fsr, fsc, &fi);\n+}\n+\n #endif /* !defined(CONFIG_USER_ONLY) */\n \n uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b)\n","prefixes":["PULL","32/36"]}