{"id":809650,"url":"http://patchwork.ozlabs.org/api/patches/809650/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-28-git-send-email-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1504527967-29248-28-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-04T12:25:58","name":"[PULL,27/36] cputlb: Support generating CPU exceptions on memory transaction failures","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"6b0f1e36b48dae9b2ecec424edab05128a9129db","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-28-git-send-email-peter.maydell@linaro.org/mbox/","series":[{"id":1366,"url":"http://patchwork.ozlabs.org/api/series/1366/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1366","date":"2017-09-04T12:25:36","name":"[PULL,01/36] target/arm: Use MMUAccessType enum rather than int","version":1,"mbox":"http://patchwork.ozlabs.org/series/1366/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/809650/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/809650/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xm8hX41Sxz9t2Z\n\tfor ;\n\tMon, 4 Sep 2017 22:45:32 +1000 (AEST)","from localhost ([::1]:59635 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1doqks-0002OX-D7\n\tfor incoming@patchwork.ozlabs.org; Mon, 04 Sep 2017 08:45:30 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:52863)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1doqSg-0005DX-3f\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:52 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1doqSQ-0004vs-UD\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:42 -0400","from orth.archaic.org.uk ([2001:8b0:1d0::2]:37132)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1doqSQ-0004v8-N6\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:26 -0400","from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from ) id 1doqSP-0005aw-Mz\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 13:26:25 +0100"],"From":"Peter Maydell ","To":"qemu-devel@nongnu.org","Date":"Mon, 4 Sep 2017 13:25:58 +0100","Message-Id":"<1504527967-29248-28-git-send-email-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>","References":"<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2001:8b0:1d0::2","Subject":"[Qemu-devel] [PULL 27/36] cputlb: Support generating CPU exceptions\n\ton memory transaction failures","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"Call the new cpu_transaction_failed() hook at the places where\nCPU generated code interacts with the memory system:\n io_readx()\n io_writex()\n get_page_addr_code()\n\nAny access from C code (eg via cpu_physical_memory_rw(),\naddress_space_rw(), ld/st_*_phys()) will *not* trigger CPU exceptions\nvia cpu_transaction_failed(). Handling for transactions failures for\nthis kind of call should be done by using a function which returns a\nMemTxResult and treating the failure case appropriately in the\ncalling code.\n\nIn an ideal world we would not generate CPU exceptions for\ninstruction fetch failures in get_page_addr_code() but instead wait\nuntil the code translation process tried a load and it failed;\nhowever that change would require too great a restructuring and\nredesign to attempt at this point.\n\nSigned-off-by: Peter Maydell \nReviewed-by: Edgar E. Iglesias \n---\n softmmu_template.h | 4 ++--\n accel/tcg/cputlb.c | 32 ++++++++++++++++++++++++++++++--\n 2 files changed, 32 insertions(+), 4 deletions(-)","diff":"diff --git a/softmmu_template.h b/softmmu_template.h\nindex 4a2b665..d756329 100644\n--- a/softmmu_template.h\n+++ b/softmmu_template.h\n@@ -101,7 +101,7 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,\n uintptr_t retaddr)\n {\n CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index];\n- return io_readx(env, iotlbentry, addr, retaddr, DATA_SIZE);\n+ return io_readx(env, iotlbentry, mmu_idx, addr, retaddr, DATA_SIZE);\n }\n #endif\n \n@@ -262,7 +262,7 @@ static inline void glue(io_write, SUFFIX)(CPUArchState *env,\n uintptr_t retaddr)\n {\n CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index];\n- return io_writex(env, iotlbentry, val, addr, retaddr, DATA_SIZE);\n+ return io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, DATA_SIZE);\n }\n \n void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,\ndiff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c\nindex 85635ae..e72415a 100644\n--- a/accel/tcg/cputlb.c\n+++ b/accel/tcg/cputlb.c\n@@ -747,6 +747,7 @@ static inline ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr)\n }\n \n static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,\n+ int mmu_idx,\n target_ulong addr, uintptr_t retaddr, int size)\n {\n CPUState *cpu = ENV_GET_CPU(env);\n@@ -754,6 +755,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,\n MemoryRegion *mr = iotlb_to_region(cpu, physaddr, iotlbentry->attrs);\n uint64_t val;\n bool locked = false;\n+ MemTxResult r;\n \n physaddr = (physaddr & TARGET_PAGE_MASK) + addr;\n cpu->mem_io_pc = retaddr;\n@@ -767,7 +769,12 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,\n qemu_mutex_lock_iothread();\n locked = true;\n }\n- memory_region_dispatch_read(mr, physaddr, &val, size, iotlbentry->attrs);\n+ r = memory_region_dispatch_read(mr, physaddr,\n+ &val, size, iotlbentry->attrs);\n+ if (r != MEMTX_OK) {\n+ cpu_transaction_failed(cpu, physaddr, addr, size, MMU_DATA_LOAD,\n+ mmu_idx, iotlbentry->attrs, r, retaddr);\n+ }\n if (locked) {\n qemu_mutex_unlock_iothread();\n }\n@@ -776,6 +783,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,\n }\n \n static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,\n+ int mmu_idx,\n uint64_t val, target_ulong addr,\n uintptr_t retaddr, int size)\n {\n@@ -783,6 +791,7 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,\n hwaddr physaddr = iotlbentry->addr;\n MemoryRegion *mr = iotlb_to_region(cpu, physaddr, iotlbentry->attrs);\n bool locked = false;\n+ MemTxResult r;\n \n physaddr = (physaddr & TARGET_PAGE_MASK) + addr;\n if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu->can_do_io) {\n@@ -795,7 +804,12 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,\n qemu_mutex_lock_iothread();\n locked = true;\n }\n- memory_region_dispatch_write(mr, physaddr, val, size, iotlbentry->attrs);\n+ r = memory_region_dispatch_write(mr, physaddr,\n+ val, size, iotlbentry->attrs);\n+ if (r != MEMTX_OK) {\n+ cpu_transaction_failed(cpu, physaddr, addr, size, MMU_DATA_STORE,\n+ mmu_idx, iotlbentry->attrs, r, retaddr);\n+ }\n if (locked) {\n qemu_mutex_unlock_iothread();\n }\n@@ -845,6 +859,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr)\n MemoryRegion *mr;\n CPUState *cpu = ENV_GET_CPU(env);\n CPUIOTLBEntry *iotlbentry;\n+ hwaddr physaddr;\n \n index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);\n mmu_idx = cpu_mmu_index(env, true);\n@@ -868,6 +883,19 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr)\n }\n qemu_mutex_unlock_iothread();\n \n+ /* Give the new-style cpu_transaction_failed() hook first chance\n+ * to handle this.\n+ * This is not the ideal place to detect and generate CPU\n+ * exceptions for instruction fetch failure (for instance\n+ * we don't know the length of the access that the CPU would\n+ * use, and it would be better to go ahead and try the access\n+ * and use the MemTXResult it produced). However it is the\n+ * simplest place we have currently available for the check.\n+ */\n+ physaddr = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;\n+ cpu_transaction_failed(cpu, physaddr, addr, 0, MMU_INST_FETCH, mmu_idx,\n+ iotlbentry->attrs, MEMTX_DECODE_ERROR, 0);\n+\n cpu_unassigned_access(cpu, addr, false, true, 0, 4);\n /* The CPU's unassigned access hook might have longjumped out\n * with an exception. If it didn't (or there was no hook) then\n","prefixes":["PULL","27/36"]}