{"id":809644,"url":"http://patchwork.ozlabs.org/api/patches/809644/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-19-git-send-email-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1504527967-29248-19-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-04T12:25:49","name":"[PULL,18/36] hw/arm: use defined type name instead of hard-coded string","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"5ffd7ade3d3ad7191910fd2dbaa273b98ad9422c","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-19-git-send-email-peter.maydell@linaro.org/mbox/","series":[{"id":1366,"url":"http://patchwork.ozlabs.org/api/series/1366/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1366","date":"2017-09-04T12:25:36","name":"[PULL,01/36] target/arm: Use MMUAccessType enum rather than int","version":1,"mbox":"http://patchwork.ozlabs.org/series/1366/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/809644/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/809644/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xm8b50nXcz9t2R\n\tfor ;\n\tMon, 4 Sep 2017 22:40:49 +1000 (AEST)","from localhost ([::1]:59610 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1doqgJ-0006zg-6c\n\tfor incoming@patchwork.ozlabs.org; Mon, 04 Sep 2017 08:40:47 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:52620)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1doqSU-00052j-9s\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:44 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1doqSG-0004ox-N7\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:30 -0400","from orth.archaic.org.uk ([2001:8b0:1d0::2]:37122)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1doqSG-0004oE-Ai\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:16 -0400","from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from ) id 1doqSF-0005Wx-Bk\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 13:26:15 +0100"],"From":"Peter Maydell ","To":"qemu-devel@nongnu.org","Date":"Mon, 4 Sep 2017 13:25:49 +0100","Message-Id":"<1504527967-29248-19-git-send-email-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>","References":"<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2001:8b0:1d0::2","Subject":"[Qemu-devel] [PULL 18/36] hw/arm: use defined type name instead of\n\thard-coded string","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"From: Philippe Mathieu-Daudé \n\nSigned-off-by: Philippe Mathieu-Daudé \nReviewed-by: Peter Maydell \nSigned-off-by: Peter Maydell \n---\n hw/arm/armv7m.c | 4 ++--\n hw/arm/exynos4210.c | 4 ++--\n hw/arm/highbank.c | 11 +++++++----\n hw/arm/realview.c | 6 ++++--\n hw/arm/vexpress.c | 6 ++++--\n hw/arm/xilinx_zynq.c | 14 ++++++++------\n 6 files changed, 27 insertions(+), 18 deletions(-)","diff":"diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c\nindex c8a11f2..d2477e8 100644\n--- a/hw/arm/armv7m.c\n+++ b/hw/arm/armv7m.c\n@@ -146,7 +146,7 @@ static void armv7m_instance_init(Object *obj)\n &error_abort);\n memory_region_init(&s->container, obj, \"armv7m-container\", UINT64_MAX);\n \n- object_initialize(&s->nvic, sizeof(s->nvic), \"armv7m_nvic\");\n+ object_initialize(&s->nvic, sizeof(s->nvic), TYPE_NVIC);\n qdev_set_parent_bus(DEVICE(&s->nvic), sysbus_get_default());\n object_property_add_alias(obj, \"num-irq\",\n OBJECT(&s->nvic), \"num-irq\", &error_abort);\n@@ -293,7 +293,7 @@ DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,\n cpu_model = \"cortex-m3\";\n }\n \n- armv7m = qdev_create(NULL, \"armv7m\");\n+ armv7m = qdev_create(NULL, TYPE_ARMV7M);\n qdev_prop_set_uint32(armv7m, \"num-irq\", num_irq);\n qdev_prop_set_string(armv7m, \"cpu-model\", cpu_model);\n object_property_set_link(OBJECT(armv7m), OBJECT(get_system_memory()),\ndiff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c\nindex f9e79f3..ee1438a 100644\n--- a/hw/arm/exynos4210.c\n+++ b/hw/arm/exynos4210.c\n@@ -33,7 +33,7 @@\n #include \"hw/arm/arm.h\"\n #include \"hw/loader.h\"\n #include \"hw/arm/exynos4210.h\"\n-#include \"hw/sd/sd.h\"\n+#include \"hw/sd/sdhci.h\"\n #include \"hw/usb/hcd-ehci.h\"\n \n #define EXYNOS4210_CHIPID_ADDR 0x10000000\n@@ -381,7 +381,7 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)\n BlockBackend *blk;\n DriveInfo *di;\n \n- dev = qdev_create(NULL, \"generic-sdhci\");\n+ dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);\n qdev_prop_set_uint32(dev, \"capareg\", EXYNOS4210_SDHCI_CAPABILITIES);\n qdev_init_nofail(dev);\n \ndiff --git a/hw/arm/highbank.c b/hw/arm/highbank.c\nindex 20e60f1..942d5a8 100644\n--- a/hw/arm/highbank.c\n+++ b/hw/arm/highbank.c\n@@ -31,6 +31,9 @@\n #include \"exec/address-spaces.h\"\n #include \"qemu/error-report.h\"\n #include \"hw/char/pl011.h\"\n+#include \"hw/ide/ahci.h\"\n+#include \"hw/cpu/a9mpcore.h\"\n+#include \"hw/cpu/a15mpcore.h\"\n \n #define SMP_BOOT_ADDR 0x100\n #define SMP_BOOT_REG 0x40\n@@ -300,10 +303,10 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)\n busdev = SYS_BUS_DEVICE(dev);\n sysbus_mmio_map(busdev, 0, 0xfff12000);\n \n- dev = qdev_create(NULL, \"a9mpcore_priv\");\n+ dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);\n break;\n case CALXEDA_MIDWAY:\n- dev = qdev_create(NULL, \"a15mpcore_priv\");\n+ dev = qdev_create(NULL, TYPE_A15MPCORE_PRIV);\n break;\n }\n qdev_prop_set_uint32(dev, \"num-cpu\", smp_cpus);\n@@ -329,7 +332,7 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)\n sysbus_connect_irq(busdev, 0, pic[18]);\n pl011_create(0xfff36000, pic[20], serial_hds[0]);\n \n- dev = qdev_create(NULL, \"highbank-regs\");\n+ dev = qdev_create(NULL, TYPE_HIGHBANK_REGISTERS);\n qdev_init_nofail(dev);\n busdev = SYS_BUS_DEVICE(dev);\n sysbus_mmio_map(busdev, 0, 0xfff3c000);\n@@ -341,7 +344,7 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)\n sysbus_create_simple(\"pl031\", 0xfff35000, pic[19]);\n sysbus_create_simple(\"pl022\", 0xfff39000, pic[23]);\n \n- sysbus_create_simple(\"sysbus-ahci\", 0xffe08000, pic[83]);\n+ sysbus_create_simple(TYPE_SYSBUS_AHCI, 0xffe08000, pic[83]);\n \n if (nd_table[0].used) {\n qemu_check_nic_model(&nd_table[0], \"xgmac\");\ndiff --git a/hw/arm/realview.c b/hw/arm/realview.c\nindex 76ff557..2736156 100644\n--- a/hw/arm/realview.c\n+++ b/hw/arm/realview.c\n@@ -24,6 +24,8 @@\n #include \"exec/address-spaces.h\"\n #include \"qemu/error-report.h\"\n #include \"hw/char/pl011.h\"\n+#include \"hw/cpu/a9mpcore.h\"\n+#include \"hw/intc/realview_gic.h\"\n \n #define SMP_BOOT_ADDR 0xe0000000\n #define SMP_BOOTREG_ADDR 0x10000030\n@@ -172,7 +174,7 @@ static void realview_init(MachineState *machine,\n sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000);\n \n if (is_mpcore) {\n- dev = qdev_create(NULL, is_pb ? \"a9mpcore_priv\": \"realview_mpcore\");\n+ dev = qdev_create(NULL, is_pb ? TYPE_A9MPCORE_PRIV : \"realview_mpcore\");\n qdev_prop_set_uint32(dev, \"num-cpu\", smp_cpus);\n qdev_init_nofail(dev);\n busdev = SYS_BUS_DEVICE(dev);\n@@ -186,7 +188,7 @@ static void realview_init(MachineState *machine,\n } else {\n uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000;\n /* For now just create the nIRQ GIC, and ignore the others. */\n- dev = sysbus_create_simple(\"realview_gic\", gic_addr, cpu_irq[0]);\n+ dev = sysbus_create_simple(TYPE_REALVIEW_GIC, gic_addr, cpu_irq[0]);\n }\n for (n = 0; n < 64; n++) {\n pic[n] = qdev_get_gpio_in(dev, n);\ndiff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c\nindex 528c65d..571dd36 100644\n--- a/hw/arm/vexpress.c\n+++ b/hw/arm/vexpress.c\n@@ -40,6 +40,8 @@\n #include \"qemu/error-report.h\"\n #include \n #include \"hw/char/pl011.h\"\n+#include \"hw/cpu/a9mpcore.h\"\n+#include \"hw/cpu/a15mpcore.h\"\n \n #define VEXPRESS_BOARD_ID 0x8e0\n #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)\n@@ -293,7 +295,7 @@ static void a9_daughterboard_init(const VexpressMachineState *vms,\n memory_region_add_subregion(sysmem, 0x60000000, ram);\n \n /* 0x1e000000 A9MPCore (SCU) private memory region */\n- init_cpus(cpu_model, \"a9mpcore_priv\", 0x1e000000, pic, vms->secure);\n+ init_cpus(cpu_model, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, vms->secure);\n \n /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */\n \n@@ -378,7 +380,7 @@ static void a15_daughterboard_init(const VexpressMachineState *vms,\n memory_region_add_subregion(sysmem, 0x80000000, ram);\n \n /* 0x2c000000 A15MPCore private memory region (GIC) */\n- init_cpus(cpu_model, \"a15mpcore_priv\", 0x2c000000, pic, vms->secure);\n+ init_cpus(cpu_model, TYPE_A15MPCORE_PRIV, 0x2c000000, pic, vms->secure);\n \n /* A15 daughterboard peripherals: */\n \ndiff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c\nindex 6b11a75..a750959 100644\n--- a/hw/arm/xilinx_zynq.c\n+++ b/hw/arm/xilinx_zynq.c\n@@ -31,8 +31,10 @@\n #include \"hw/misc/zynq-xadc.h\"\n #include \"hw/ssi/ssi.h\"\n #include \"qemu/error-report.h\"\n-#include \"hw/sd/sd.h\"\n+#include \"hw/sd/sdhci.h\"\n #include \"hw/char/cadence_uart.h\"\n+#include \"hw/net/cadence_gem.h\"\n+#include \"hw/cpu/a9mpcore.h\"\n \n #define NUM_SPI_FLASHES 4\n #define NUM_QSPI_FLASHES 2\n@@ -96,9 +98,9 @@ static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)\n DeviceState *dev;\n SysBusDevice *s;\n \n- dev = qdev_create(NULL, \"cadence_gem\");\n+ dev = qdev_create(NULL, TYPE_CADENCE_GEM);\n if (nd->used) {\n- qemu_check_nic_model(nd, \"cadence_gem\");\n+ qemu_check_nic_model(nd, TYPE_CADENCE_GEM);\n qdev_set_nic_properties(dev, nd);\n }\n qdev_init_nofail(dev);\n@@ -222,7 +224,7 @@ static void zynq_init(MachineState *machine)\n qdev_init_nofail(dev);\n sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000);\n \n- dev = qdev_create(NULL, \"a9mpcore_priv\");\n+ dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);\n qdev_prop_set_uint32(dev, \"num-cpu\", 1);\n qdev_init_nofail(dev);\n busdev = SYS_BUS_DEVICE(dev);\n@@ -252,7 +254,7 @@ static void zynq_init(MachineState *machine)\n gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]);\n gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]);\n \n- dev = qdev_create(NULL, \"generic-sdhci\");\n+ dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);\n qdev_init_nofail(dev);\n sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0100000);\n sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[56-IRQ_OFFSET]);\n@@ -263,7 +265,7 @@ static void zynq_init(MachineState *machine)\n qdev_prop_set_drive(carddev, \"drive\", blk, &error_fatal);\n object_property_set_bool(OBJECT(carddev), true, \"realized\", &error_fatal);\n \n- dev = qdev_create(NULL, \"generic-sdhci\");\n+ dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);\n qdev_init_nofail(dev);\n sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0101000);\n sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[79-IRQ_OFFSET]);\n","prefixes":["PULL","18/36"]}