{"id":809641,"url":"http://patchwork.ozlabs.org/api/patches/809641/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-16-git-send-email-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1504527967-29248-16-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-04T12:25:46","name":"[PULL,15/36] nvic: Implement \"user accesses BusFault\" SCS region behaviour","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"e31a6533b616833358e9a2320d3a6f614dd409f7","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-16-git-send-email-peter.maydell@linaro.org/mbox/","series":[{"id":1366,"url":"http://patchwork.ozlabs.org/api/series/1366/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1366","date":"2017-09-04T12:25:36","name":"[PULL,01/36] target/arm: Use MMUAccessType enum rather than int","version":1,"mbox":"http://patchwork.ozlabs.org/series/1366/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/809641/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/809641/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xm8YL0sW0z9t2R\n\tfor ;\n\tMon, 4 Sep 2017 22:39:18 +1000 (AEST)","from localhost ([::1]:59604 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1doqeq-0005uT-33\n\tfor incoming@patchwork.ozlabs.org; Mon, 04 Sep 2017 08:39:16 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:52588)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1doqSS-00051a-GD\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:44 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1doqSC-0004mW-UZ\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:28 -0400","from orth.archaic.org.uk ([2001:8b0:1d0::2]:37116)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1doqSC-0004l7-MS\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:12 -0400","from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from ) id 1doqSB-0005Ve-Hx\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 13:26:11 +0100"],"From":"Peter Maydell ","To":"qemu-devel@nongnu.org","Date":"Mon, 4 Sep 2017 13:25:46 +0100","Message-Id":"<1504527967-29248-16-git-send-email-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>","References":"<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2001:8b0:1d0::2","Subject":"[Qemu-devel] [PULL 15/36] nvic: Implement \"user accesses BusFault\"\n\tSCS region behaviour","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"The ARMv7M architecture specifies that most of the addresses in the\nPPB region (which includes the NVIC, systick and system registers)\nare not accessible to unprivileged accesses, which should\nBusFault with a few exceptions:\n * the STIR is configurably user-accessible\n * the ITM (which we don't implement at all) is always\n user-accessible\n\nImplement this by switching the register access functions\nto the _with_attrs scheme that lets us distinguish user\nmode accesses.\n\nThis allows us to pull the handling of the CCR.USERSETMPEND\nflag up to the level where we can make it generate a BusFault\nas it should for non-permitted accesses.\n\nNote that until the core ARM CPU code implements turning\nMEMTX_ERROR into a BusFault the registers will continue to\nact as RAZ/WI to user accesses.\n\nSigned-off-by: Peter Maydell \nReviewed-by: Edgar E. Iglesias \nReviewed-by: Richard Henderson \nMessage-id: 1501692241-23310-16-git-send-email-peter.maydell@linaro.org\n---\n hw/intc/armv7m_nvic.c | 58 ++++++++++++++++++++++++++++++++++++---------------\n 1 file changed, 41 insertions(+), 17 deletions(-)","diff":"diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c\nindex 5a18025..bbfe2d5 100644\n--- a/hw/intc/armv7m_nvic.c\n+++ b/hw/intc/armv7m_nvic.c\n@@ -733,11 +733,8 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)\n }\n case 0xf00: /* Software Triggered Interrupt Register */\n {\n- /* user mode can only write to STIR if CCR.USERSETMPEND permits it */\n int excnum = (value & 0x1ff) + NVIC_FIRST_IRQ;\n- if (excnum < s->num_irq &&\n- (arm_current_el(&cpu->env) ||\n- (cpu->env.v7m.ccr & R_V7M_CCR_USERSETMPEND_MASK))) {\n+ if (excnum < s->num_irq) {\n armv7m_nvic_set_pending(s, excnum);\n }\n break;\n@@ -748,14 +745,32 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value)\n }\n }\n \n-static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr,\n- unsigned size)\n+static bool nvic_user_access_ok(NVICState *s, hwaddr offset)\n+{\n+ /* Return true if unprivileged access to this register is permitted. */\n+ switch (offset) {\n+ case 0xf00: /* STIR: accessible only if CCR.USERSETMPEND permits */\n+ return s->cpu->env.v7m.ccr & R_V7M_CCR_USERSETMPEND_MASK;\n+ default:\n+ /* All other user accesses cause a BusFault unconditionally */\n+ return false;\n+ }\n+}\n+\n+static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,\n+ uint64_t *data, unsigned size,\n+ MemTxAttrs attrs)\n {\n NVICState *s = (NVICState *)opaque;\n uint32_t offset = addr;\n unsigned i, startvec, end;\n uint32_t val;\n \n+ if (attrs.user && !nvic_user_access_ok(s, addr)) {\n+ /* Generate BusFault for unprivileged accesses */\n+ return MEMTX_ERROR;\n+ }\n+\n switch (offset) {\n /* reads of set and clear both return the status */\n case 0x100 ... 0x13f: /* NVIC Set enable */\n@@ -826,11 +841,13 @@ static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr,\n }\n \n trace_nvic_sysreg_read(addr, val, size);\n- return val;\n+ *data = val;\n+ return MEMTX_OK;\n }\n \n-static void nvic_sysreg_write(void *opaque, hwaddr addr,\n- uint64_t value, unsigned size)\n+static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,\n+ uint64_t value, unsigned size,\n+ MemTxAttrs attrs)\n {\n NVICState *s = (NVICState *)opaque;\n uint32_t offset = addr;\n@@ -839,6 +856,11 @@ static void nvic_sysreg_write(void *opaque, hwaddr addr,\n \n trace_nvic_sysreg_write(addr, value, size);\n \n+ if (attrs.user && !nvic_user_access_ok(s, addr)) {\n+ /* Generate BusFault for unprivileged accesses */\n+ return MEMTX_ERROR;\n+ }\n+\n switch (offset) {\n case 0x100 ... 0x13f: /* NVIC Set enable */\n offset += 0x80;\n@@ -853,7 +875,7 @@ static void nvic_sysreg_write(void *opaque, hwaddr addr,\n }\n }\n nvic_irq_update(s);\n- return;\n+ return MEMTX_OK;\n case 0x200 ... 0x23f: /* NVIC Set pend */\n /* the special logic in armv7m_nvic_set_pending()\n * is not needed since IRQs are never escalated\n@@ -870,9 +892,9 @@ static void nvic_sysreg_write(void *opaque, hwaddr addr,\n }\n }\n nvic_irq_update(s);\n- return;\n+ return MEMTX_OK;\n case 0x300 ... 0x33f: /* NVIC Active */\n- return; /* R/O */\n+ return MEMTX_OK; /* R/O */\n case 0x400 ... 0x5ef: /* NVIC Priority */\n startvec = 8 * (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */\n \n@@ -880,26 +902,28 @@ static void nvic_sysreg_write(void *opaque, hwaddr addr,\n set_prio(s, startvec + i, (value >> (i * 8)) & 0xff);\n }\n nvic_irq_update(s);\n- return;\n+ return MEMTX_OK;\n case 0xd18 ... 0xd23: /* System Handler Priority. */\n for (i = 0; i < size; i++) {\n unsigned hdlidx = (offset - 0xd14) + i;\n set_prio(s, hdlidx, (value >> (i * 8)) & 0xff);\n }\n nvic_irq_update(s);\n- return;\n+ return MEMTX_OK;\n }\n if (size == 4) {\n nvic_writel(s, offset, value);\n- return;\n+ return MEMTX_OK;\n }\n qemu_log_mask(LOG_GUEST_ERROR,\n \"NVIC: Bad write of size %d at offset 0x%x\\n\", size, offset);\n+ /* This is UNPREDICTABLE; treat as RAZ/WI */\n+ return MEMTX_OK;\n }\n \n static const MemoryRegionOps nvic_sysreg_ops = {\n- .read = nvic_sysreg_read,\n- .write = nvic_sysreg_write,\n+ .read_with_attrs = nvic_sysreg_read,\n+ .write_with_attrs = nvic_sysreg_write,\n .endianness = DEVICE_NATIVE_ENDIAN,\n };\n \n","prefixes":["PULL","15/36"]}