{"id":809640,"url":"http://patchwork.ozlabs.org/api/patches/809640/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-14-git-send-email-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1504527967-29248-14-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-04T12:25:44","name":"[PULL,13/36] target/arm: Create and use new function arm_v7m_is_handler_mode()","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"1a0d85ac64ac6a39363c14699403436ba7881288","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-14-git-send-email-peter.maydell@linaro.org/mbox/","series":[{"id":1366,"url":"http://patchwork.ozlabs.org/api/series/1366/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1366","date":"2017-09-04T12:25:36","name":"[PULL,01/36] target/arm: Use MMUAccessType enum rather than int","version":1,"mbox":"http://patchwork.ozlabs.org/series/1366/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/809640/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/809640/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xm8Vf2tgDz9t2R\n\tfor ;\n\tMon, 4 Sep 2017 22:36:58 +1000 (AEST)","from localhost ([::1]:59595 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1doqca-0004CD-De\n\tfor incoming@patchwork.ozlabs.org; Mon, 04 Sep 2017 08:36:56 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:52487)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1doqSN-0004xq-GD\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:38 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1doqSA-0004kU-Li\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:23 -0400","from orth.archaic.org.uk ([2001:8b0:1d0::2]:37114)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1doqSA-0004k3-Ex\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:10 -0400","from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from ) id 1doqS9-0005V0-GH\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 13:26:09 +0100"],"From":"Peter Maydell ","To":"qemu-devel@nongnu.org","Date":"Mon, 4 Sep 2017 13:25:44 +0100","Message-Id":"<1504527967-29248-14-git-send-email-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>","References":"<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2001:8b0:1d0::2","Subject":"[Qemu-devel] [PULL 13/36] target/arm: Create and use new function\n\tarm_v7m_is_handler_mode()","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"Add a utility function for testing whether the CPU is in Handler\nmode; this is just a check whether v7m.exception is non-zero, but\nwe do it in several places and it makes the code a bit easier\nto read to not have to mentally figure out what the test is testing.\n\nSigned-off-by: Peter Maydell \nReviewed-by: Philippe Mathieu-Daudé \nReviewed-by: Edgar E. Iglesias \nReviewed-by: Richard Henderson \nMessage-id: 1501692241-23310-14-git-send-email-peter.maydell@linaro.org\n---\n target/arm/cpu.h | 10 ++++++++--\n target/arm/helper.c | 8 ++++----\n 2 files changed, 12 insertions(+), 6 deletions(-)","diff":"diff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex 8ef552a..eabef00 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -1629,13 +1629,19 @@ static inline int arm_highest_el(CPUARMState *env)\n return 1;\n }\n \n+/* Return true if a v7M CPU is in Handler mode */\n+static inline bool arm_v7m_is_handler_mode(CPUARMState *env)\n+{\n+ return env->v7m.exception != 0;\n+}\n+\n /* Return the current Exception Level (as per ARMv8; note that this differs\n * from the ARMv7 Privilege Level).\n */\n static inline int arm_current_el(CPUARMState *env)\n {\n if (arm_feature(env, ARM_FEATURE_M)) {\n- return !((env->v7m.exception == 0) && (env->v7m.control & 1));\n+ return arm_v7m_is_handler_mode(env) || !(env->v7m.control & 1);\n }\n \n if (is_a64(env)) {\n@@ -2635,7 +2641,7 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,\n }\n *flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT;\n \n- if (env->v7m.exception != 0) {\n+ if (arm_v7m_is_handler_mode(env)) {\n *flags |= ARM_TBFLAG_HANDLER_MASK;\n }\n \ndiff --git a/target/arm/helper.c b/target/arm/helper.c\nindex 267a170..37e7fd9 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -6142,7 +6142,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu)\n * that jumps to magic addresses don't have magic behaviour unless\n * we're in Handler mode (compare pseudocode BXWritePC()).\n */\n- assert(env->v7m.exception != 0);\n+ assert(arm_v7m_is_handler_mode(env));\n \n /* In the spec pseudocode ExceptionReturn() is called directly\n * from BXWritePC() and gets the full target PC value including\n@@ -6249,7 +6249,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu)\n * resuming in Thread mode. If that doesn't match what the\n * exception return type specified then this is a UsageFault.\n */\n- if (return_to_handler == (env->v7m.exception == 0)) {\n+ if (return_to_handler != arm_v7m_is_handler_mode(env)) {\n /* Take an INVPC UsageFault by pushing the stack again. */\n armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);\n env->v7m.cfsr |= R_V7M_CFSR_INVPC_MASK;\n@@ -6400,7 +6400,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)\n if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) {\n lr |= 4;\n }\n- if (env->v7m.exception == 0) {\n+ if (!arm_v7m_is_handler_mode(env)) {\n lr |= 8;\n }\n \n@@ -8793,7 +8793,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)\n * switch_v7m_sp() deals with updating the SPSEL bit in\n * env->v7m.control, so we only need update the others.\n */\n- if (env->v7m.exception == 0) {\n+ if (!arm_v7m_is_handler_mode(env)) {\n switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0);\n }\n env->v7m.control &= ~R_V7M_CONTROL_NPRIV_MASK;\n","prefixes":["PULL","13/36"]}