{"id":809638,"url":"http://patchwork.ozlabs.org/api/patches/809638/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-2-git-send-email-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1504527967-29248-2-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-04T12:25:32","name":"[PULL,01/36] target/arm: Use MMUAccessType enum rather than int","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"aa21c5f62fb6b7de2b063469be99f0a68df38f5f","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-2-git-send-email-peter.maydell@linaro.org/mbox/","series":[{"id":1366,"url":"http://patchwork.ozlabs.org/api/series/1366/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1366","date":"2017-09-04T12:25:36","name":"[PULL,01/36] target/arm: Use MMUAccessType enum rather than int","version":1,"mbox":"http://patchwork.ozlabs.org/series/1366/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/809638/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/809638/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xm8Tl74gQz9t2R\n\tfor ;\n\tMon, 4 Sep 2017 22:36:10 +1000 (AEST)","from localhost ([::1]:59580 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1doqbm-0003e3-EL\n\tfor incoming@patchwork.ozlabs.org; Mon, 04 Sep 2017 08:36:06 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:52323)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1doqSE-0004r9-Hi\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:29 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1doqS4-0004dD-0R\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:14 -0400","from orth.archaic.org.uk ([2001:8b0:1d0::2]:37104)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1doqS3-0004RY-NO\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:03 -0400","from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from ) id 1doqRs-0005PK-7l\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 13:25:52 +0100"],"From":"Peter Maydell ","To":"qemu-devel@nongnu.org","Date":"Mon, 4 Sep 2017 13:25:32 +0100","Message-Id":"<1504527967-29248-2-git-send-email-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>","References":"<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2001:8b0:1d0::2","Subject":"[Qemu-devel] [PULL 01/36] target/arm: Use MMUAccessType enum rather\n\tthan int","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"In the ARM get_phys_addr() code, switch to using the MMUAccessType\nenum and its MMU_* values rather than int and literal 0/1/2.\n\nSigned-off-by: Peter Maydell \nReviewed-by: Edgar E. Iglesias \nReviewed-by: Philippe Mathieu-Daudé \nReviewed-by: Richard Henderson \nMessage-id: 1501692241-23310-2-git-send-email-peter.maydell@linaro.org\n---\n target/arm/internals.h | 3 ++-\n target/arm/helper.c | 30 +++++++++++++++---------------\n 2 files changed, 17 insertions(+), 16 deletions(-)","diff":"diff --git a/target/arm/internals.h b/target/arm/internals.h\nindex 1f6efef..bb06946 100644\n--- a/target/arm/internals.h\n+++ b/target/arm/internals.h\n@@ -457,7 +457,8 @@ struct ARMMMUFaultInfo {\n };\n \n /* Do a page table walk and add page to TLB if possible */\n-bool arm_tlb_fill(CPUState *cpu, vaddr address, int rw, int mmu_idx,\n+bool arm_tlb_fill(CPUState *cpu, vaddr address,\n+ MMUAccessType access_type, int mmu_idx,\n uint32_t *fsr, ARMMMUFaultInfo *fi);\n \n /* Return true if the stage 1 translation regime is using LPAE format page\ndiff --git a/target/arm/helper.c b/target/arm/helper.c\nindex 0ec92d3..8e148be 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -20,13 +20,13 @@\n \n #ifndef CONFIG_USER_ONLY\n static bool get_phys_addr(CPUARMState *env, target_ulong address,\n- int access_type, ARMMMUIdx mmu_idx,\n+ MMUAccessType access_type, ARMMMUIdx mmu_idx,\n hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,\n target_ulong *page_size, uint32_t *fsr,\n ARMMMUFaultInfo *fi);\n \n static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,\n- int access_type, ARMMMUIdx mmu_idx,\n+ MMUAccessType access_type, ARMMMUIdx mmu_idx,\n hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,\n target_ulong *page_size_ptr, uint32_t *fsr,\n ARMMMUFaultInfo *fi);\n@@ -2135,7 +2135,7 @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,\n }\n \n static uint64_t do_ats_write(CPUARMState *env, uint64_t value,\n- int access_type, ARMMMUIdx mmu_idx)\n+ MMUAccessType access_type, ARMMMUIdx mmu_idx)\n {\n hwaddr phys_addr;\n target_ulong page_size;\n@@ -2194,7 +2194,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,\n \n static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)\n {\n- int access_type = ri->opc2 & 1;\n+ MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;\n uint64_t par64;\n ARMMMUIdx mmu_idx;\n int el = arm_current_el(env);\n@@ -2253,7 +2253,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)\n static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,\n uint64_t value)\n {\n- int access_type = ri->opc2 & 1;\n+ MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;\n uint64_t par64;\n \n par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS);\n@@ -2273,7 +2273,7 @@ static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri,\n static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,\n uint64_t value)\n {\n- int access_type = ri->opc2 & 1;\n+ MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;\n ARMMMUIdx mmu_idx;\n int secure = arm_is_secure_below_el3(env);\n \n@@ -7505,7 +7505,7 @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,\n }\n \n static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,\n- int access_type, ARMMMUIdx mmu_idx,\n+ MMUAccessType access_type, ARMMMUIdx mmu_idx,\n hwaddr *phys_ptr, int *prot,\n target_ulong *page_size, uint32_t *fsr,\n ARMMMUFaultInfo *fi)\n@@ -7621,7 +7621,7 @@ do_fault:\n }\n \n static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,\n- int access_type, ARMMMUIdx mmu_idx,\n+ MMUAccessType access_type, ARMMMUIdx mmu_idx,\n hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,\n target_ulong *page_size, uint32_t *fsr,\n ARMMMUFaultInfo *fi)\n@@ -7728,7 +7728,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,\n if (pxn && !regime_is_user(env, mmu_idx)) {\n xn = 1;\n }\n- if (xn && access_type == 2)\n+ if (xn && access_type == MMU_INST_FETCH)\n goto do_fault;\n \n if (arm_feature(env, ARM_FEATURE_V6K) &&\n@@ -7843,7 +7843,7 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,\n }\n \n static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,\n- int access_type, ARMMMUIdx mmu_idx,\n+ MMUAccessType access_type, ARMMMUIdx mmu_idx,\n hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,\n target_ulong *page_size_ptr, uint32_t *fsr,\n ARMMMUFaultInfo *fi)\n@@ -8251,7 +8251,7 @@ static inline bool m_is_system_region(CPUARMState *env, uint32_t address)\n }\n \n static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,\n- int access_type, ARMMMUIdx mmu_idx,\n+ MMUAccessType access_type, ARMMMUIdx mmu_idx,\n hwaddr *phys_ptr, int *prot, uint32_t *fsr)\n {\n ARMCPU *cpu = arm_env_get_cpu(env);\n@@ -8410,7 +8410,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,\n }\n \n static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,\n- int access_type, ARMMMUIdx mmu_idx,\n+ MMUAccessType access_type, ARMMMUIdx mmu_idx,\n hwaddr *phys_ptr, int *prot, uint32_t *fsr)\n {\n int n;\n@@ -8437,7 +8437,7 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,\n return true;\n }\n \n- if (access_type == 2) {\n+ if (access_type == MMU_INST_FETCH) {\n mask = env->cp15.pmsav5_insn_ap;\n } else {\n mask = env->cp15.pmsav5_data_ap;\n@@ -8508,7 +8508,7 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,\n * @fsr: set to the DFSR/IFSR value on failure\n */\n static bool get_phys_addr(CPUARMState *env, target_ulong address,\n- int access_type, ARMMMUIdx mmu_idx,\n+ MMUAccessType access_type, ARMMMUIdx mmu_idx,\n hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,\n target_ulong *page_size, uint32_t *fsr,\n ARMMMUFaultInfo *fi)\n@@ -8621,7 +8621,7 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,\n * fsr with ARM DFSR/IFSR fault register format value on failure.\n */\n bool arm_tlb_fill(CPUState *cs, vaddr address,\n- int access_type, int mmu_idx, uint32_t *fsr,\n+ MMUAccessType access_type, int mmu_idx, uint32_t *fsr,\n ARMMMUFaultInfo *fi)\n {\n ARMCPU *cpu = ARM_CPU(cs);\n","prefixes":["PULL","01/36"]}