{"id":809630,"url":"http://patchwork.ozlabs.org/api/patches/809630/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-12-git-send-email-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1504527967-29248-12-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-04T12:25:42","name":"[PULL,11/36] target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"962925251d56b313a52667577e4b542588f8b6af","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-12-git-send-email-peter.maydell@linaro.org/mbox/","series":[{"id":1366,"url":"http://patchwork.ozlabs.org/api/series/1366/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1366","date":"2017-09-04T12:25:36","name":"[PULL,01/36] target/arm: Use MMUAccessType enum rather than int","version":1,"mbox":"http://patchwork.ozlabs.org/series/1366/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/809630/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/809630/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xm8M26lpQz9t2S\n\tfor ;\n\tMon, 4 Sep 2017 22:30:22 +1000 (AEST)","from localhost ([::1]:59549 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1doqWC-0007S4-UI\n\tfor incoming@patchwork.ozlabs.org; Mon, 04 Sep 2017 08:30:21 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:52383)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1doqSI-0004tp-50\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:33 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1doqS7-0004he-4m\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:18 -0400","from orth.archaic.org.uk ([2001:8b0:1d0::2]:37110)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1doqS6-0004ej-Tm\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:07 -0400","from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from ) id 1doqS5-0005Ts-RL\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 13:26:05 +0100"],"From":"Peter Maydell ","To":"qemu-devel@nongnu.org","Date":"Mon, 4 Sep 2017 13:25:42 +0100","Message-Id":"<1504527967-29248-12-git-send-email-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>","References":"<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2001:8b0:1d0::2","Subject":"[Qemu-devel] [PULL 11/36] target/arm: Make arm_cpu_dump_state()\n\thandle the M-profile XPSR","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"Make the arm_cpu_dump_state() debug logging handle the M-profile XPSR\nrather than assuming it's an A-profile CPSR. On M profile the PSR\nline of a register dump will now look like this:\n\nXPSR=41000000 -Z-- T priv-thread\n\nSigned-off-by: Peter Maydell \nReviewed-by: Edgar E. Iglesias \nReviewed-by: Richard Henderson \nMessage-id: 1501692241-23310-12-git-send-email-peter.maydell@linaro.org\n---\n target/arm/translate.c | 58 ++++++++++++++++++++++++++++++++++----------------\n 1 file changed, 40 insertions(+), 18 deletions(-)","diff":"diff --git a/target/arm/translate.c b/target/arm/translate.c\nindex 3c14cb0..e52a6d7 100644\n--- a/target/arm/translate.c\n+++ b/target/arm/translate.c\n@@ -12215,8 +12215,6 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,\n ARMCPU *cpu = ARM_CPU(cs);\n CPUARMState *env = &cpu->env;\n int i;\n- uint32_t psr;\n- const char *ns_status;\n \n if (is_a64(env)) {\n aarch64_cpu_dump_state(cs, f, cpu_fprintf, flags);\n@@ -12230,24 +12228,48 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,\n else\n cpu_fprintf(f, \" \");\n }\n- psr = cpsr_read(env);\n \n- if (arm_feature(env, ARM_FEATURE_EL3) &&\n- (psr & CPSR_M) != ARM_CPU_MODE_MON) {\n- ns_status = env->cp15.scr_el3 & SCR_NS ? \"NS \" : \"S \";\n+ if (arm_feature(env, ARM_FEATURE_M)) {\n+ uint32_t xpsr = xpsr_read(env);\n+ const char *mode;\n+\n+ if (xpsr & XPSR_EXCP) {\n+ mode = \"handler\";\n+ } else {\n+ if (env->v7m.control & R_V7M_CONTROL_NPRIV_MASK) {\n+ mode = \"unpriv-thread\";\n+ } else {\n+ mode = \"priv-thread\";\n+ }\n+ }\n+\n+ cpu_fprintf(f, \"XPSR=%08x %c%c%c%c %c %s\\n\",\n+ xpsr,\n+ xpsr & XPSR_N ? 'N' : '-',\n+ xpsr & XPSR_Z ? 'Z' : '-',\n+ xpsr & XPSR_C ? 'C' : '-',\n+ xpsr & XPSR_V ? 'V' : '-',\n+ xpsr & XPSR_T ? 'T' : 'A',\n+ mode);\n } else {\n- ns_status = \"\";\n- }\n-\n- cpu_fprintf(f, \"PSR=%08x %c%c%c%c %c %s%s%d\\n\",\n- psr,\n- psr & (1 << 31) ? 'N' : '-',\n- psr & (1 << 30) ? 'Z' : '-',\n- psr & (1 << 29) ? 'C' : '-',\n- psr & (1 << 28) ? 'V' : '-',\n- psr & CPSR_T ? 'T' : 'A',\n- ns_status,\n- cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26);\n+ uint32_t psr = cpsr_read(env);\n+ const char *ns_status = \"\";\n+\n+ if (arm_feature(env, ARM_FEATURE_EL3) &&\n+ (psr & CPSR_M) != ARM_CPU_MODE_MON) {\n+ ns_status = env->cp15.scr_el3 & SCR_NS ? \"NS \" : \"S \";\n+ }\n+\n+ cpu_fprintf(f, \"PSR=%08x %c%c%c%c %c %s%s%d\\n\",\n+ psr,\n+ psr & CPSR_N ? 'N' : '-',\n+ psr & CPSR_Z ? 'Z' : '-',\n+ psr & CPSR_C ? 'C' : '-',\n+ psr & CPSR_V ? 'V' : '-',\n+ psr & CPSR_T ? 'T' : 'A',\n+ ns_status,\n+ cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26);\n+ }\n \n if (flags & CPU_DUMP_FPU) {\n int numvfpregs = 0;\n","prefixes":["PULL","11/36"]}