{"id":809629,"url":"http://patchwork.ozlabs.org/api/patches/809629/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-9-git-send-email-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1504527967-29248-9-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-04T12:25:39","name":"[PULL,08/36] target/arm: Define and use XPSR bit masks","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"d2826d84cdf744abfb8a52957e91ef4871a4c24a","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1504527967-29248-9-git-send-email-peter.maydell@linaro.org/mbox/","series":[{"id":1366,"url":"http://patchwork.ozlabs.org/api/series/1366/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1366","date":"2017-09-04T12:25:36","name":"[PULL,01/36] target/arm: Use MMUAccessType enum rather than int","version":1,"mbox":"http://patchwork.ozlabs.org/series/1366/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/809629/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/809629/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xm8Lw6nwwz9t2S\n\tfor ;\n\tMon, 4 Sep 2017 22:30:16 +1000 (AEST)","from localhost ([::1]:59547 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1doqW6-0007Nk-Sh\n\tfor incoming@patchwork.ozlabs.org; Mon, 04 Sep 2017 08:30:14 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:52318)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1doqSE-0004qu-4N\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:29 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1doqS4-0004dQ-4m\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:14 -0400","from orth.archaic.org.uk ([2001:8b0:1d0::2]:37108)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1doqS3-0004cC-Sv\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:04 -0400","from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from ) id 1doqS2-0005SG-S3\n\tfor qemu-devel@nongnu.org; Mon, 04 Sep 2017 13:26:02 +0100"],"From":"Peter Maydell ","To":"qemu-devel@nongnu.org","Date":"Mon, 4 Sep 2017 13:25:39 +0100","Message-Id":"<1504527967-29248-9-git-send-email-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>","References":"<1504527967-29248-1-git-send-email-peter.maydell@linaro.org>","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2001:8b0:1d0::2","Subject":"[Qemu-devel] [PULL 08/36] target/arm: Define and use XPSR bit masks","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"The M profile XPSR is almost the same format as the A profile CPSR,\nbut not quite. Define some XPSR_* macros and use them where we\ndefinitely dealing with an XPSR rather than reusing the CPSR ones.\n\nSigned-off-by: Peter Maydell \nReviewed-by: Edgar E. Iglesias \nReviewed-by: Richard Henderson \nMessage-id: 1501692241-23310-9-git-send-email-peter.maydell@linaro.org\n---\n target/arm/cpu.h | 38 ++++++++++++++++++++++++++++----------\n target/arm/helper.c | 15 ++++++++-------\n 2 files changed, 36 insertions(+), 17 deletions(-)","diff":"diff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex 2f2aa87..0b9f937 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -882,6 +882,22 @@ void pmccntr_sync(CPUARMState *env);\n /* Mask of bits which may be set by exception return copying them from SPSR */\n #define CPSR_ERET_MASK (~CPSR_RESERVED)\n \n+/* Bit definitions for M profile XPSR. Most are the same as CPSR. */\n+#define XPSR_EXCP 0x1ffU\n+#define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */\n+#define XPSR_IT_2_7 CPSR_IT_2_7\n+#define XPSR_GE CPSR_GE\n+#define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */\n+#define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */\n+#define XPSR_IT_0_1 CPSR_IT_0_1\n+#define XPSR_Q CPSR_Q\n+#define XPSR_V CPSR_V\n+#define XPSR_C CPSR_C\n+#define XPSR_Z CPSR_Z\n+#define XPSR_N CPSR_N\n+#define XPSR_NZCV CPSR_NZCV\n+#define XPSR_IT CPSR_IT\n+\n #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */\n #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */\n #define TTBCR_PD0 (1U << 4)\n@@ -986,26 +1002,28 @@ static inline uint32_t xpsr_read(CPUARMState *env)\n /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */\n static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)\n {\n- if (mask & CPSR_NZCV) {\n- env->ZF = (~val) & CPSR_Z;\n+ if (mask & XPSR_NZCV) {\n+ env->ZF = (~val) & XPSR_Z;\n env->NF = val;\n env->CF = (val >> 29) & 1;\n env->VF = (val << 3) & 0x80000000;\n }\n- if (mask & CPSR_Q)\n- env->QF = ((val & CPSR_Q) != 0);\n- if (mask & (1 << 24))\n- env->thumb = ((val & (1 << 24)) != 0);\n- if (mask & CPSR_IT_0_1) {\n+ if (mask & XPSR_Q) {\n+ env->QF = ((val & XPSR_Q) != 0);\n+ }\n+ if (mask & XPSR_T) {\n+ env->thumb = ((val & XPSR_T) != 0);\n+ }\n+ if (mask & XPSR_IT_0_1) {\n env->condexec_bits &= ~3;\n env->condexec_bits |= (val >> 25) & 3;\n }\n- if (mask & CPSR_IT_2_7) {\n+ if (mask & XPSR_IT_2_7) {\n env->condexec_bits &= 3;\n env->condexec_bits |= (val >> 8) & 0xfc;\n }\n- if (mask & 0x1ff) {\n- env->v7m.exception = val & 0x1ff;\n+ if (mask & XPSR_EXCP) {\n+ env->v7m.exception = val & XPSR_EXCP;\n }\n }\n \ndiff --git a/target/arm/helper.c b/target/arm/helper.c\nindex 2fb0202..439ad86 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -6114,7 +6114,7 @@ static void v7m_push_stack(ARMCPU *cpu)\n /* Align stack pointer if the guest wants that */\n if ((env->regs[13] & 4) && (env->v7m.ccr & R_V7M_CCR_STKALIGN_MASK)) {\n env->regs[13] -= 4;\n- xpsr |= 0x200;\n+ xpsr |= XPSR_SPREALIGN;\n }\n /* Switch to the handler mode. */\n v7m_push(env, xpsr);\n@@ -6239,10 +6239,11 @@ static void do_v7m_exception_exit(ARMCPU *cpu)\n env->regs[15] &= ~1U;\n }\n xpsr = v7m_pop(env);\n- xpsr_write(env, xpsr, 0xfffffdff);\n+ xpsr_write(env, xpsr, ~XPSR_SPREALIGN);\n /* Undo stack alignment. */\n- if (xpsr & 0x200)\n+ if (xpsr & XPSR_SPREALIGN) {\n env->regs[13] |= 4;\n+ }\n \n /* The restored xPSR exception field will be zero if we're\n * resuming in Thread mode. If that doesn't match what the\n@@ -8688,10 +8689,10 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)\n case 0 ... 7: /* xPSR sub-fields */\n mask = 0;\n if ((reg & 1) && el) {\n- mask |= 0x000001ff; /* IPSR (unpriv. reads as zero) */\n+ mask |= XPSR_EXCP; /* IPSR (unpriv. reads as zero) */\n }\n if (!(reg & 4)) {\n- mask |= 0xf8000000; /* APSR */\n+ mask |= XPSR_NZCV | XPSR_Q; /* APSR */\n }\n /* EPSR reads as zero */\n return xpsr_read(env) & mask;\n@@ -8749,10 +8750,10 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)\n uint32_t apsrmask = 0;\n \n if (mask & 8) {\n- apsrmask |= 0xf8000000; /* APSR NZCVQ */\n+ apsrmask |= XPSR_NZCV | XPSR_Q;\n }\n if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) {\n- apsrmask |= 0x000f0000; /* APSR GE[3:0] */\n+ apsrmask |= XPSR_GE;\n }\n xpsr_write(env, val, apsrmask);\n }\n","prefixes":["PULL","08/36"]}