{"id":809289,"url":"http://patchwork.ozlabs.org/api/patches/809289/?format=json","web_url":"http://patchwork.ozlabs.org/project/buildroot/patch/3447db07fd4678fa60261dd0e400218072d33482.1504444617.git.yann.morin.1998@free.fr/","project":{"id":27,"url":"http://patchwork.ozlabs.org/api/projects/27/?format=json","name":"Buildroot development","link_name":"buildroot","list_id":"buildroot.buildroot.org","list_email":"buildroot@buildroot.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<3447db07fd4678fa60261dd0e400218072d33482.1504444617.git.yann.morin.1998@free.fr>","list_archive_url":null,"date":"2017-09-03T13:17:47","name":"[7/9] arch/arm: add some non-cortex armv8a cores","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"5d10b32df75c9d02572c624ef019033d8a564e05","submitter":{"id":13903,"url":"http://patchwork.ozlabs.org/api/people/13903/?format=json","name":"Yann E. MORIN","email":"yann.morin.1998@free.fr"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/buildroot/patch/3447db07fd4678fa60261dd0e400218072d33482.1504444617.git.yann.morin.1998@free.fr/mbox/","series":[{"id":1231,"url":"http://patchwork.ozlabs.org/api/series/1231/?format=json","web_url":"http://patchwork.ozlabs.org/project/buildroot/list/?series=1231","date":"2017-09-03T13:17:44","name":"[1/9] arch/arm: re-order cores choice","version":1,"mbox":"http://patchwork.ozlabs.org/series/1231/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/809289/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/809289/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","buildroot@lists.busybox.net"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","buildroot@osuosl.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=busybox.net\n\t(client-ip=140.211.166.138; helo=whitealder.osuosl.org;\n\tenvelope-from=buildroot-bounces@busybox.net;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"JxqRQgjG\"; dkim-atps=neutral"],"Received":["from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xlYSr0WMQz9s8J\n\tfor ;\n\tSun, 3 Sep 2017 23:18:20 +1000 (AEST)","from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 24D228609F;\n\tSun, 3 Sep 2017 13:18:18 +0000 (UTC)","from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id Xmcu97foxDBC; Sun, 3 Sep 2017 13:18:12 +0000 (UTC)","from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 958CA8126A;\n\tSun, 3 Sep 2017 13:18:11 +0000 (UTC)","from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\tby ash.osuosl.org (Postfix) with ESMTP id 84CC11C0DB4\n\tfor ;\n\tSun, 3 Sep 2017 13:18:04 +0000 (UTC)","from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 786B1868BC\n\tfor ;\n\tSun, 3 Sep 2017 13:18:04 +0000 (UTC)","from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id SbzeWmS6dJ7s for ;\n\tSun, 3 Sep 2017 13:18:03 +0000 (UTC)","from mail-wm0-f65.google.com (mail-wm0-f65.google.com\n\t[74.125.82.65])\n\tby fraxinus.osuosl.org (Postfix) with ESMTPS id 45D22868A9\n\tfor ; Sun, 3 Sep 2017 13:18:03 +0000 (UTC)","by mail-wm0-f65.google.com with SMTP id u26so4133520wma.5\n\tfor ; Sun, 03 Sep 2017 06:18:03 -0700 (PDT)","from localhost.localdomain\n\t(2a01cb0886107300d59898fcbeacd7d5.ipv6.abo.wanadoo.fr.\n\t[2a01:cb08:8610:7300:d598:98fc:beac:d7d5])\n\tby smtp.gmail.com with ESMTPSA id\n\tc139sm6351605wmh.32.2017.09.03.06.18.00\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tSun, 03 Sep 2017 06:18:00 -0700 (PDT)"],"X-Virus-Scanned":["amavisd-new at osuosl.org","amavisd-new at osuosl.org"],"X-Greylist":"domain auto-whitelisted by SQLgrey-1.7.6","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=sender:from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=doc4N+57c3NxcvV1XLXNdgAS85xTzMCuCFYxz2CK4do=;\n\tb=JxqRQgjGDVqa0DyieAm/XtpLLU0uUuj8lyxBIodL0Xxn+5j2PK73V1emOxCMgCZkOf\n\touMAB+EBW1rrdbz1IsvRkTaVJPR6sZpCnS8uIPZ6iymhvqaBRlsFSGuOf0TBRW/FRrRd\n\tQYlm5o/pc1i4Fqgh3vtNjFzSE6hMNj2eL53FNpKbKm9Nfb5buvfJX+4dyJMngf+G96+s\n\tX6w/5wP9zyHCn5wttiWeU4r3zJRG0jda4CoU6rdT90cg8QSVCm1m4zPLdK5YJk/aMFl+\n\tgGJgKhIfTywE0ux7vOI42v2y9Lf9q15aPs8Ods3XbdJ+amDWLDiBA0aJLBHzHz+vny26\n\tlLMQ==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:sender:from:to:cc:subject:date:message-id\n\t:in-reply-to:references;\n\tbh=doc4N+57c3NxcvV1XLXNdgAS85xTzMCuCFYxz2CK4do=;\n\tb=Gm2/3nPTdmrVmT/ufA9B7+O76+hsbfUYpwXZQfVi3qfIS+uDTtx/BWqQYNq02Bu/Vz\n\tbbIgraradGD14NGq1QtdXJk789hiaEKdbt4wrNeX7KH4pv4bHhsHT/qAqkWJRhoIgxJI\n\tBUpshZffqfatiLnCZC3uRBEcbQ0r8CdVTLN84bGAJRkTN36AQSFbBJaMHDtAqfwcow5D\n\tx3BHht5gBtZ/5M9g5KDvb5Kz0nXSWMzLyIedZt0STkj14aBxLigrl3LgYRbr2gJpB/F6\n\tBN9BaugHh32AQxpwvDtcnE+6iEeaGN05xRDFkTKloxc83pKYsa8CGraNByc/J+dm0C+7\n\tDruw==","X-Gm-Message-State":"AHPjjUiEkP3UAnNMoK12LEoPTzfK1mp7pGQBMo56XENCADW9x1Ljak57\n\tjDd7m8OpvuNDP81w","X-Google-Smtp-Source":"ADKCNb6CjtQmfWjuFj3lZywu+ynjXxkAYWhBf8HroDnuXTleOru8C5rAbefE76wbNG0+ep9GyT8dYg==","X-Received":"by 10.28.236.134 with SMTP id h6mr769118wmi.64.1504444681599;\n\tSun, 03 Sep 2017 06:18:01 -0700 (PDT)","From":"\"Yann E. MORIN\" ","To":"buildroot@buildroot.org","Date":"Sun, 3 Sep 2017 15:17:47 +0200","Message-Id":"<3447db07fd4678fa60261dd0e400218072d33482.1504444617.git.yann.morin.1998@free.fr>","X-Mailer":"git-send-email 2.11.0","In-Reply-To":"","References":"","Cc":"Thomas Petazzoni ,\n\t\"Yann E. MORIN\" ","Subject":"[Buildroot] [PATCH 7/9] arch/arm: add some non-cortex armv8a cores","X-BeenThere":"buildroot@busybox.net","X-Mailman-Version":"2.1.18-1","Precedence":"list","List-Id":"Discussion and development of buildroot ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Errors-To":"buildroot-bounces@busybox.net","Sender":"\"buildroot\" "},"content":"Some need gcc-5, some gcc-6 and some gcc-7.\n\nThe thunderx familly does not build in 32-bit mode (gcc complains\nthat the CPU is unknown, and even gcc master only knows them as\naarch64-only).\n\nSigned-off-by: \"Yann E. MORIN\" \nCc: Thomas Petazzoni \n---\n arch/Config.in.arm | 77 ++++++++++++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 77 insertions(+)","diff":"diff --git a/arch/Config.in.arm b/arch/Config.in.arm\nindex 65caf7aa80..40d6ae18b8 100644\n--- a/arch/Config.in.arm\n+++ b/arch/Config.in.arm\n@@ -332,6 +332,74 @@ config BR2_cortex_a73_a53\n \tselect BR2_ARM_CPU_ARMV8A\n \tselect BR2_ARCH_HAS_MMU_OPTIONAL\n \tselect BR2_ARCH_NEEDS_GCC_AT_LEAST_7\n+config BR2_exynos_m1\n+\tbool \"exynos-m1\"\n+\tselect BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64\n+\tselect BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64\n+\tselect BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64\n+\tselect BR2_ARM_CPU_HAS_FP_ARMV8\n+\tselect BR2_ARM_CPU_ARMV8A\n+\tselect BR2_ARCH_HAS_MMU_OPTIONAL\n+\tselect BR2_ARCH_NEEDS_GCC_AT_LEAST_5\n+config BR2_falkor\n+\tbool \"falkor\"\n+\tselect BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64\n+\tselect BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64\n+\tselect BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64\n+\tselect BR2_ARM_CPU_HAS_FP_ARMV8\n+\tselect BR2_ARM_CPU_ARMV8A\n+\tselect BR2_ARCH_HAS_MMU_OPTIONAL\n+\tselect BR2_ARCH_NEEDS_GCC_AT_LEAST_7\n+config BR2_qdf24xx\n+\tbool \"qdf24xx\"\n+\tselect BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64\n+\tselect BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64\n+\tselect BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64\n+\tselect BR2_ARM_CPU_HAS_FP_ARMV8\n+\tselect BR2_ARM_CPU_ARMV8A\n+\tselect BR2_ARCH_HAS_MMU_OPTIONAL\n+\tselect BR2_ARCH_NEEDS_GCC_AT_LEAST_6\n+if BR2_ARCH_IS_64\n+config BR2_thunderx\n+\tbool \"thunderx\"\n+\tselect BR2_ARM_CPU_HAS_FP_ARMV8\n+\tselect BR2_ARM_CPU_ARMV8A\n+\tselect BR2_ARCH_HAS_MMU_OPTIONAL\n+\tselect BR2_ARCH_NEEDS_GCC_AT_LEAST_5\n+config BR2_thunderxt81\n+\tbool \"thunderxt81\"\n+\tselect BR2_ARM_CPU_HAS_FP_ARMV8\n+\tselect BR2_ARM_CPU_ARMV8A\n+\tselect BR2_ARCH_HAS_MMU_OPTIONAL\n+\tselect BR2_ARCH_NEEDS_GCC_AT_LEAST_7\n+config BR2_thunderxt83\n+\tbool \"thunderxt83\"\n+\tselect BR2_ARM_CPU_HAS_FP_ARMV8\n+\tselect BR2_ARM_CPU_ARMV8A\n+\tselect BR2_ARCH_HAS_MMU_OPTIONAL\n+\tselect BR2_ARCH_NEEDS_GCC_AT_LEAST_7\n+config BR2_thunderxt88\n+\tbool \"thunderxt88\"\n+\tselect BR2_ARM_CPU_HAS_FP_ARMV8\n+\tselect BR2_ARM_CPU_ARMV8A\n+\tselect BR2_ARCH_HAS_MMU_OPTIONAL\n+\tselect BR2_ARCH_NEEDS_GCC_AT_LEAST_7\n+config BR2_thunderxt88p1\n+\tbool \"thunderxt88p1\"\n+\tselect BR2_ARM_CPU_HAS_FP_ARMV8\n+\tselect BR2_ARM_CPU_ARMV8A\n+\tselect BR2_ARCH_HAS_MMU_OPTIONAL\n+\tselect BR2_ARCH_NEEDS_GCC_AT_LEAST_7\n+endif # BR2_ARCH_IS_64\n+config BR2_xgene1\n+\tbool \"xgene1\"\n+\tselect BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64\n+\tselect BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64\n+\tselect BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64\n+\tselect BR2_ARM_CPU_HAS_FP_ARMV8\n+\tselect BR2_ARM_CPU_ARMV8A\n+\tselect BR2_ARCH_HAS_MMU_OPTIONAL\n+\tselect BR2_ARCH_NEEDS_GCC_AT_LEAST_5\n endchoice\n \n config BR2_ARM_ENABLE_NEON\n@@ -628,6 +696,15 @@ config BR2_GCC_TARGET_CPU\n \tdefault \"cortex-a73\"\tif BR2_cortex_a73\n \tdefault \"cortex-a73.cortex-a35\"\tif BR2_cortex_a73_a35\n \tdefault \"cortex-a73.cortex-a53\"\tif BR2_cortex_a73_a53\n+\tdefault \"exynos-m1\"\tif BR2_exynos_m1\n+\tdefault \"falkor\"\tif BR2_falkor\n+\tdefault \"qdf24xx\"\tif BR2_qdf24xx\n+\tdefault \"thunderx\"\tif BR2_thunderx\n+\tdefault \"thunderxt81\"\tif BR2_thunderxt81\n+\tdefault \"thunderxt83\"\tif BR2_thunderxt83\n+\tdefault \"thunderxt88\"\tif BR2_thunderxt88\n+\tdefault \"thunderxt88p1\"\tif BR2_thunderxt88p1\n+\tdefault \"xgene1\"\tif BR2_xgene1\n \n config BR2_GCC_TARGET_ABI\n \tdefault \"aapcs-linux\"\tif BR2_arm || BR2_armeb\n","prefixes":["7/9"]}