{"id":808845,"url":"http://patchwork.ozlabs.org/api/patches/808845/?format=json","web_url":"http://patchwork.ozlabs.org/project/glibc/patch/20170901174034.GA17543@gmail.com/","project":{"id":41,"url":"http://patchwork.ozlabs.org/api/projects/41/?format=json","name":"GNU C Library","link_name":"glibc","list_id":"libc-alpha.sourceware.org","list_email":"libc-alpha@sourceware.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170901174034.GA17543@gmail.com>","list_archive_url":null,"date":"2017-09-01T17:40:34","name":"x86: Add MathVec_Prefer_No_AVX512 to cpu-features [BZ #21967]","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"c3370261aadc2e9f701d16c24a71797b577052b4","submitter":{"id":4412,"url":"http://patchwork.ozlabs.org/api/people/4412/?format=json","name":"H.J. Lu","email":"hongjiu.lu@intel.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/glibc/patch/20170901174034.GA17543@gmail.com/mbox/","series":[{"id":1085,"url":"http://patchwork.ozlabs.org/api/series/1085/?format=json","web_url":"http://patchwork.ozlabs.org/project/glibc/list/?series=1085","date":"2017-09-01T17:40:34","name":"x86: Add MathVec_Prefer_No_AVX512 to cpu-features [BZ #21967]","version":1,"mbox":"http://patchwork.ozlabs.org/series/1085/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/808845/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/808845/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list libc-alpha@sourceware.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=libc-alpha-return-84041-incoming=patchwork.ozlabs.org@sourceware.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tsecure) header.d=sourceware.org header.i=@sourceware.org\n\theader.b=\"YYnfniaM\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xkRNp04r8z9t2x\n\tfor ;\n\tSat, 2 Sep 2017 03:40:57 +1000 (AEST)","(qmail 58415 invoked by alias); 1 Sep 2017 17:40:51 -0000","(qmail 58402 invoked by uid 89); 1 Sep 2017 17:40:51 -0000"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:date:from:to:cc:subject:message-id:reply-to\n\t:mime-version:content-type; q=dns; s=default; b=F3sepW17nqfhU0PZ\n\t+7kOZFMj19PBK2HxcsLr5t3KI/Yor4CFjfMLqZTQTlnaSxGY8+KwICSdPD+TqhGZ\n\tE7mNmySf4LJPfXmenUgl76yBqbw2TajlXZEsxiadb+V6JwVlSnjlLf7tod2Cg99b\n\t71hLNw6q8mgzKP46xPMhLfvPug8=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:date:from:to:cc:subject:message-id:reply-to\n\t:mime-version:content-type; s=default; bh=3x8DlCnzPDTiy9YCnfqBUF\n\ti10N0=; b=YYnfniaMj2A7zONXA2fZuwSL/RqtBh3VgVZpsHSVudg5Gg8EuvO6rn\n\tBiUACtWgiqUKZ97q6NoPh0eVzW06R70gTAdNC32LwuRO7JRAXtTfxDnfQMyYNZym\n\tr4JAEebWwPKqgGMtFAkDM0P/45vWHvp5Yf41tNVzEZQUn4NZkVraw=","Mailing-List":"contact libc-alpha-help@sourceware.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Subscribe":"","List-Archive":"","List-Post":"","List-Help":",\n\t","Sender":"libc-alpha-owner@sourceware.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-25.9 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n\tGIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3,\n\tKAM_LAZY_DOMAIN_SECURITY, NO_DNS_FOR_FROM,\n\tRP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=knl","X-HELO":"mga09.intel.com","X-ExtLoop1":"1","Date":"Fri, 1 Sep 2017 10:40:34 -0700","From":"\"H.J. Lu\" ","To":"GNU C Library ","Cc":"Andrew Senkevich ","Subject":"[PATCH] x86: Add MathVec_Prefer_No_AVX512 to cpu-features [BZ\n\t#21967]","Message-ID":"<20170901174034.GA17543@gmail.com>","Reply-To":"\"H.J. Lu\" ","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","User-Agent":"Mutt/1.8.3 (2017-05-23)"},"content":"AVX512 functions in mathvec are used on machines with AVX512. An AVX2\nwrapper is also provided and it can be used when the AVX512 version\nisn't profitable. MathVec_Prefer_No_AVX512 is addded to cpu-features.\nIf glibc.tune.hwcaps=MathVec_Prefer_No_AVX512 is set in GLIBC_TUNABLES\nenvironment variable, the AVX2 wrapper will be used.\n\nTested on x86-64 machines with and without AVX512. Also verified\nglibc.tune.hwcaps=MathVec_Prefer_No_AVX512 on AVX512 machine.\n\nAny comments?\n\nH.J.\n---\n\t[BZ #21967]\n\t* sysdeps/x86/cpu-features.h (bit_arch_MathVec_Prefer_No_AVX512):\n\tNew.\n\t(index_arch_MathVec_Prefer_No_AVX512): Likewise.\n\t* sysdeps/x86/cpu-tunables.c (TUNABLE_CALLBACK (set_hwcaps)):\n\tHandle MathVec_Prefer_No_AVX512.\n---\n sysdeps/x86/cpu-features.h | 2 ++\n sysdeps/x86/cpu-tunables.c | 7 +++++++\n sysdeps/x86_64/fpu/multiarch/ifunc-mathvec-avx512.h | 13 ++++++++-----\n 3 files changed, 17 insertions(+), 5 deletions(-)","diff":"diff --git a/sysdeps/x86/cpu-features.h b/sysdeps/x86/cpu-features.h\nindex 9e01781424..a032a2e168 100644\n--- a/sysdeps/x86/cpu-features.h\n+++ b/sysdeps/x86/cpu-features.h\n@@ -40,6 +40,7 @@\n #define bit_arch_Use_dl_runtime_resolve_opt\t(1 << 20)\n #define bit_arch_Use_dl_runtime_resolve_slow\t(1 << 21)\n #define bit_arch_Prefer_No_AVX512\t\t(1 << 22)\n+#define bit_arch_MathVec_Prefer_No_AVX512\t(1 << 23)\n \n /* CPUID Feature flags. */\n \n@@ -239,6 +240,7 @@ extern const struct cpu_features *__get_cpu_features (void)\n # define index_arch_Use_dl_runtime_resolve_opt FEATURE_INDEX_1\n # define index_arch_Use_dl_runtime_resolve_slow FEATURE_INDEX_1\n # define index_arch_Prefer_No_AVX512\tFEATURE_INDEX_1\n+# define index_arch_MathVec_Prefer_No_AVX512 FEATURE_INDEX_1\n \n #endif\t/* !__ASSEMBLER__ */\n \ndiff --git a/sysdeps/x86/cpu-tunables.c b/sysdeps/x86/cpu-tunables.c\nindex 0ab708cca8..ec72d86f08 100644\n--- a/sysdeps/x86/cpu-tunables.c\n+++ b/sysdeps/x86/cpu-tunables.c\n@@ -303,6 +303,13 @@ TUNABLE_CALLBACK (set_hwcaps) (tunable_val_t *valp)\n \t\t disable, 23);\n \t }\n \t break;\n+\tcase 24:\n+\t {\n+\t CHECK_GLIBC_IFUNC_ARCH_NEED_ARCH_BOTH\n+\t\t(n, cpu_features, MathVec_Prefer_No_AVX512,\n+\t\t AVX512F_Usable, disable, 24);\n+\t }\n+\t break;\n \tcase 26:\n \t {\n \t CHECK_GLIBC_IFUNC_ARCH_NEED_CPU_BOTH\ndiff --git a/sysdeps/x86_64/fpu/multiarch/ifunc-mathvec-avx512.h b/sysdeps/x86_64/fpu/multiarch/ifunc-mathvec-avx512.h\nindex 1857e1f760..fffc9da114 100644\n--- a/sysdeps/x86_64/fpu/multiarch/ifunc-mathvec-avx512.h\n+++ b/sysdeps/x86_64/fpu/multiarch/ifunc-mathvec-avx512.h\n@@ -32,11 +32,14 @@ IFUNC_SELECTOR (void)\n {\n const struct cpu_features* cpu_features = __get_cpu_features ();\n \n- if (CPU_FEATURES_ARCH_P (cpu_features, AVX512DQ_Usable))\n- return OPTIMIZE (skx);\n-\n- if (CPU_FEATURES_ARCH_P (cpu_features, AVX512F_Usable))\n- return OPTIMIZE (knl);\n+ if (!CPU_FEATURES_ARCH_P (cpu_features, MathVec_Prefer_No_AVX512))\n+ {\n+ if (CPU_FEATURES_ARCH_P (cpu_features, AVX512DQ_Usable))\n+\treturn OPTIMIZE (skx);\n+\n+ if (CPU_FEATURES_ARCH_P (cpu_features, AVX512F_Usable))\n+\treturn OPTIMIZE (knl);\n+ }\n \n return OPTIMIZE (avx2_wrapper);\n }\n","prefixes":[]}