{"id":808257,"url":"http://patchwork.ozlabs.org/api/patches/808257/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20170831135748.32498-1-wens@csie.org/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170831135748.32498-1-wens@csie.org>","list_archive_url":null,"date":"2017-08-31T13:57:48","name":"[U-Boot] mmc: sunxi: Only update timing mode bit when enabling new timing mode","commit_ref":"8a647fc3ca2a93e2b6c965999ac2e0316191a755","pull_url":null,"state":"accepted","archived":false,"hash":"0377c9b1cb95ec04377b1b202e74ebaa553db86e","submitter":{"id":47154,"url":"http://patchwork.ozlabs.org/api/people/47154/?format=json","name":"Chen-Yu Tsai","email":"wens@csie.org"},"delegate":{"id":17739,"url":"http://patchwork.ozlabs.org/api/users/17739/?format=json","username":"jagan","first_name":"Jagannadha Sutradharudu","last_name":"Teki","email":"jagannadh.teki@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20170831135748.32498-1-wens@csie.org/mbox/","series":[{"id":835,"url":"http://patchwork.ozlabs.org/api/series/835/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=835","date":"2017-08-31T13:57:48","name":"[U-Boot] mmc: sunxi: Only update timing mode bit when enabling new timing mode","version":1,"mbox":"http://patchwork.ozlabs.org/series/835/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/808257/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/808257/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xjkV53Hzcz9sPm\n\tfor ;\n\tThu, 31 Aug 2017 23:58:05 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 3183DC21E4A; Thu, 31 Aug 2017 13:57:59 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id C51B8C21DB5;\n\tThu, 31 Aug 2017 13:57:56 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 64A29C21DB5; Thu, 31 Aug 2017 13:57:55 +0000 (UTC)","from wens.csie.org (mirror2.csie.ntu.edu.tw [140.112.30.76])\n\tby lists.denx.de (Postfix) with ESMTPS id 9645AC21D99\n\tfor ; Thu, 31 Aug 2017 13:57:54 +0000 (UTC)","by wens.csie.org (Postfix, from userid 1000)\n\tid 42A255FB68; Thu, 31 Aug 2017 21:57:49 +0800 (CST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.0 required=5.0 tests=none autolearn=unavailable\n\tautolearn_force=no version=3.4.0","From":"Chen-Yu Tsai ","To":"u-boot@lists.denx.de","Date":"Thu, 31 Aug 2017 21:57:48 +0800","Message-Id":"<20170831135748.32498-1-wens@csie.org>","X-Mailer":"git-send-email 2.14.1","Cc":"Jagan Teki ,\n\tMaxime Ripard ","Subject":"[U-Boot] [PATCH] mmc: sunxi: Only update timing mode bit when\n\tenabling new timing mode","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"When enabling the new mmc timing mode, we inadvertently clear all the\nremaining bits in the new timing mode register. The bits cleared\ninclude a default phase delay on the output clock. The BSP kernel\nstates that the default values are supposed to be used. Clearing them\nresults in decreased performance or transfer errors on some boards.\n\nFixes: de9b1771c3b6 (\"mmc: sunxi: Support new mode\")\nSigned-off-by: Chen-Yu Tsai \n---\n drivers/mmc/sunxi_mmc.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)","diff":"diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c\nindex a76e763bfd4f..4edb4be46c81 100644\n--- a/drivers/mmc/sunxi_mmc.c\n+++ b/drivers/mmc/sunxi_mmc.c\n@@ -167,7 +167,7 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)\n \tif (new_mode) {\n #ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE\n \t\tval = CCM_MMC_CTRL_MODE_SEL_NEW;\n-\t\twritel(SUNXI_MMC_NTSR_MODE_SEL_NEW, &priv->reg->ntsr);\n+\t\tsetbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);\n #endif\n \t} else {\n \t\tval = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |\n","prefixes":["U-Boot"]}