{"id":808175,"url":"http://patchwork.ozlabs.org/api/patches/808175/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1504176175-31663-2-git-send-email-Ashish.Kumar@nxp.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1504176175-31663-2-git-send-email-Ashish.Kumar@nxp.com>","list_archive_url":null,"date":"2017-08-31T10:42:54","name":"[U-Boot,v5,2/3] armv8: ls1088ardb: Add support for LS1088ARDB platform","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"536ba3ea55a3799500d1ecf28223bc9d870edc1e","submitter":{"id":68053,"url":"http://patchwork.ozlabs.org/api/people/68053/?format=json","name":"Ashish Kumar","email":"Ashish.kumar@nxp.com"},"delegate":{"id":2666,"url":"http://patchwork.ozlabs.org/api/users/2666/?format=json","username":"yorksun","first_name":"York","last_name":"Sun","email":"yorksun@freescale.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1504176175-31663-2-git-send-email-Ashish.Kumar@nxp.com/mbox/","series":[{"id":792,"url":"http://patchwork.ozlabs.org/api/series/792/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=792","date":"2017-08-31T10:42:53","name":"[U-Boot,v5,1/3] armv8: ls1088a: Add NXP LS1088A SoC support","version":5,"mbox":"http://patchwork.ozlabs.org/series/792/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/808175/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/808175/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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\n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;","From":"Ashish Kumar ","To":"","Date":"Thu, 31 Aug 2017 16:12:54 +0530","Message-ID":"<1504176175-31663-2-git-send-email-Ashish.Kumar@nxp.com>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1504176175-31663-1-git-send-email-Ashish.Kumar@nxp.com>","References":"<1504176175-31663-1-git-send-email-Ashish.Kumar@nxp.com>","X-EOPAttributedMessage":"0","X-Matching-Connectors":"131486497901050140;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); ()","X-Forefront-Antispam-Report":"CIP:192.88.168.50; IPV:NLI; CTRY:US; EFV:NLI;\n\tSFV:NSPM;\n\tSFS:(10009020)(6009001)(336005)(39380400002)(39860400002)(2980300002)(1110001)(1109001)(339900001)(199003)(189002)(97736004)(104016004)(81156014)(8676002)(105606002)(81166006)(36756003)(68736007)(2351001)(2906002)(72206003)(8656003)(86362001)(48376002)(575784001)(626005)(498600001)(4326008)(189998001)(356003)(53946003)(77096006)(5660300001)(54906002)(106466001)(47776003)(6916009)(53936002)(2950100002)(8936002)(5003940100001)(50226002)(85426001)(6666003)(76176999)(50986999)(50466002)(110136004)(305945005)(579004)(357404004);\n\tDIR:OUT; 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BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(400006)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:DM5PR03MB3323; ","X-Forefront-PRVS":"04163EF38A","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"31 Aug 2017 10:43:09.9022\n\t(UTC)","X-MS-Exchange-CrossTenant-Id":"5afe0b00-7697-4969-b663-5eab37d5f47e","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"DM5PR03MB3323","Cc":"Shaohui Xie , Alison Wang ,\n\tRaghav Dogra ","Subject":"[U-Boot] [PATCH v5 2/3] armv8: ls1088ardb: Add support for\n\tLS1088ARDB platform","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"LS1088A is an ARMv8 implementation. The LS1088ARDB is an evaluatoin\nplatform that supports the LS1088A family SoCs. This patch add basic\nsupport of the platform.\n\nSigned-off-by: Alison Wang \nSigned-off-by: Prabhakar Kushwaha \nSigned-off-by: Ashish Kumar \nSigned-off-by: Raghav Dogra \nSigned-off-by: Shaohui Xie \n---\nv5:\n Fix checkpatch's check\n Change getenv() to env_get()\n Rebase to top commit \"8b3cec7 mtdparts: Fix uninitialized scalar usage\"\n\n arch/arm/Kconfig | 14 ++\n arch/arm/cpu/armv8/Kconfig | 1 +\n arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 +\n arch/arm/dts/Makefile | 3 +-\n arch/arm/dts/fsl-ls1088a-rdb.dts | 40 ++++\n board/freescale/ls1088a/Kconfig | 15 ++\n board/freescale/ls1088a/MAINTAINERS | 7 +\n board/freescale/ls1088a/Makefile | 9 +\n board/freescale/ls1088a/README | 66 ++++++\n board/freescale/ls1088a/ddr.c | 102 +++++++++\n board/freescale/ls1088a/ddr.h | 44 ++++\n board/freescale/ls1088a/eth_ls1088ardb.c | 102 +++++++++\n board/freescale/ls1088a/ls1088a.c | 332 ++++++++++++++++++++++++++++++\n board/freescale/ls1088a/ls1088a_qixis.h | 34 +++\n configs/ls1088ardb_qspi_defconfig | 29 +++\n include/configs/ls1088a_common.h | 201 ++++++++++++++++++\n include/configs/ls1088ardb.h | 319 ++++++++++++++++++++++++++++\n 17 files changed, 1318 insertions(+), 1 deletion(-)\n create mode 100644 arch/arm/dts/fsl-ls1088a-rdb.dts\n create mode 100644 board/freescale/ls1088a/Kconfig\n create mode 100644 board/freescale/ls1088a/MAINTAINERS\n create mode 100644 board/freescale/ls1088a/Makefile\n create mode 100644 board/freescale/ls1088a/README\n create mode 100644 board/freescale/ls1088a/ddr.c\n create mode 100644 board/freescale/ls1088a/ddr.h\n create mode 100644 board/freescale/ls1088a/eth_ls1088ardb.c\n create mode 100644 board/freescale/ls1088a/ls1088a.c\n create mode 100644 board/freescale/ls1088a/ls1088a_qixis.h\n create mode 100644 configs/ls1088ardb_qspi_defconfig\n create mode 100644 include/configs/ls1088a_common.h\n create mode 100644 include/configs/ls1088ardb.h","diff":"diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig\nindex 53d0831..acc6990 100644\n--- a/arch/arm/Kconfig\n+++ b/arch/arm/Kconfig\n@@ -906,6 +906,19 @@ config TARGET_LS1012AFRDM\n \t development platform that supports the QorIQ LS1012A\n \t Layerscape Architecture processor.\n \n+config TARGET_LS1088ARDB\n+\tbool \"Support ls1088ardb\"\n+\tselect ARCH_LS1088A\n+\tselect ARM64\n+\tselect ARMV8_MULTIENTRY\n+\tselect ARCH_MISC_INIT\n+\tselect BOARD_LATE_INIT\n+\thelp\n+\t Support for NXP LS1088ARDB platform.\n+\t The LS1088A Reference design board (RDB) is a high-performance\n+\t development platform that supports the QorIQ LS1088A\n+\t Layerscape Architecture processor.\n+\n config TARGET_LS1021AQDS\n \tbool \"Support ls1021aqds\"\n \tselect BOARD_LATE_INIT\n@@ -1185,6 +1198,7 @@ source \"board/creative/xfi3/Kconfig\"\n source \"board/freescale/ls2080a/Kconfig\"\n source \"board/freescale/ls2080aqds/Kconfig\"\n source \"board/freescale/ls2080ardb/Kconfig\"\n+source \"board/freescale/ls1088a/Kconfig\"\n source \"board/freescale/ls1021aqds/Kconfig\"\n source \"board/freescale/ls1043aqds/Kconfig\"\n source \"board/freescale/ls1021atwr/Kconfig\"\ndiff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig\nindex 8e4c3dd..aecdf81 100644\n--- a/arch/arm/cpu/armv8/Kconfig\n+++ b/arch/arm/cpu/armv8/Kconfig\n@@ -88,6 +88,7 @@ config PSCI_RESET\n \tdepends on !ARCH_EXYNOS7 && !ARCH_BCM283X && !TARGET_LS2080A_EMU && \\\n \t\t !TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \\\n \t\t !TARGET_LS2080ARDB && !TARGET_LS1012AQDS && \\\n+\t\t !TARGET_LS1088ARDB && \\\n \t\t !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \\\n \t\t !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \\\n \t\t !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \\\ndiff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\nindex aa2d0d1..9290268 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\n@@ -208,6 +208,7 @@ config SYS_LS_PPA_FW_ADDR\n \tdefault 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A\n \tdefault 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT\n \tdefault 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A\n+\tdefault 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A\n \tdefault 0x60400000 if SYS_LS_PPA_FW_IN_XIP\n \tdefault 0x400000 if SYS_LS_PPA_FW_IN_MMC\n \tdefault 0x400000 if SYS_LS_PPA_FW_IN_NAND\ndiff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\nindex 762429c..9c63fb4 100644\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -187,7 +187,8 @@ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \\\n dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \\\n \tfsl-ls2080a-rdb.dtb \\\n \tfsl-ls2081a-rdb.dtb \\\n-\tfsl-ls2088a-rdb-qspi.dtb\n+\tfsl-ls2088a-rdb-qspi.dtb \\\n+\tfsl-ls1088a-rdb.dtb\n dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \\\n \tfsl-ls1043a-qds-lpuart.dtb \\\n \tfsl-ls1043a-rdb.dtb \\\ndiff --git a/arch/arm/dts/fsl-ls1088a-rdb.dts b/arch/arm/dts/fsl-ls1088a-rdb.dts\nnew file mode 100644\nindex 0000000..30ceed8\n--- /dev/null\n+++ b/arch/arm/dts/fsl-ls1088a-rdb.dts\n@@ -0,0 +1,40 @@\n+/*\n+ * NXP ls1088a RDB board device tree source\n+ *\n+ * Copyright 2017 NXP\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+/dts-v1/;\n+\n+#include \"fsl-ls1088a.dtsi\"\n+\n+/ {\n+\tmodel = \"NXP Layerscape 1088a RDB Board\";\n+\tcompatible = \"fsl,ls1088a-rdb\", \"fsl,ls1088a\";\n+\taliases {\n+\t\tspi0 = &qspi;\n+\t};\n+};\n+\n+&qspi {\n+\tbus-num = <0>;\n+\tstatus = \"okay\";\n+\n+\tqflash0: s25fs512s@0 {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tcompatible = \"spi-flash\";\n+\t\tspi-max-frequency = <50000000>;\n+\t\treg = <0>;\n+\t};\n+\n+\tqflash1: s25fs512s@1 {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tcompatible = \"spi-flash\";\n+\t\tspi-max-frequency = <50000000>;\n+\t\treg = <1>;\n+\t };\n+};\ndiff --git a/board/freescale/ls1088a/Kconfig b/board/freescale/ls1088a/Kconfig\nnew file mode 100644\nindex 0000000..a4d8223\n--- /dev/null\n+++ b/board/freescale/ls1088a/Kconfig\n@@ -0,0 +1,15 @@\n+if TARGET_LS1088ARDB\n+\n+config SYS_BOARD\n+\tdefault \"ls1088a\"\n+\n+config SYS_VENDOR\n+\tdefault \"freescale\"\n+\n+config SYS_SOC\n+\tdefault \"fsl-layerscape\"\n+\n+config SYS_CONFIG_NAME\n+\tdefault \"ls1088ardb\"\n+\n+endif\ndiff --git a/board/freescale/ls1088a/MAINTAINERS b/board/freescale/ls1088a/MAINTAINERS\nnew file mode 100644\nindex 0000000..12834f6\n--- /dev/null\n+++ b/board/freescale/ls1088a/MAINTAINERS\n@@ -0,0 +1,7 @@\n+LS1088ARDB BOARD\n+M:\tPrabhakar Kushwaha \n+M:\tAshish Kumar \n+S:\tMaintained\n+F:\tboard/freescale/ls1088a/\n+F:\tinclude/configs/ls1088ardb.h\n+F:\tconfigs/ls1088ardb_qspi_defconfig\ndiff --git a/board/freescale/ls1088a/Makefile b/board/freescale/ls1088a/Makefile\nnew file mode 100644\nindex 0000000..e997cf1\n--- /dev/null\n+++ b/board/freescale/ls1088a/Makefile\n@@ -0,0 +1,9 @@\n+#\n+# Copyright 2017 NXP\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+obj-y += ls1088a.o\n+obj-$(CONFIG_TARGET_LS1088ARDB) += eth_ls1088ardb.o\n+obj-y += ddr.o\ndiff --git a/board/freescale/ls1088a/README b/board/freescale/ls1088a/README\nnew file mode 100644\nindex 0000000..3f4d987\n--- /dev/null\n+++ b/board/freescale/ls1088a/README\n@@ -0,0 +1,66 @@\n+Overview\n+--------\n+The LS1088A Reference Design (RDB) is a high-performance computing,\n+evaluation, and development platform that supports ARM SoC LS1088A and its\n+derivatives.\n+\n+\n+LS1088A SoC Overview\n+--------------------------------------\n+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc\n+\n+RDB Default Switch Settings (1: ON; 0: OFF)\n+-------------------------------------------\n+\n+For QSPI Boot\n+SW1 0011 0001\n+SW2 x100 0000\n+SW3 1111 0010\n+SW4 1001 0011\n+SW5 1111 0000\n+\n+For SD Boot\n+SW1 0010 0000\n+SW2 0100 0000\n+SW3 1111 0010\n+SW4 1001 0011\n+SW5 1111 0000\n+\n+For eMMC Boot\n+SW1 0010 0000\n+SW2 1100 0000\n+SW3 1111 0010\n+SW4 1001 0011\n+SW5 1111 0000\n+\n+Alternately you can use this command to switch from QSPI to SD\n+\n+=> i2c mw 66 0x60 0x20; i2c mw 66 10 10;i2c mw 66 10 21\n+\n+ LS1088ARDB board Overview\n+ -------------------------\n+ - SERDES Connections, 16 lanes supporting:\n+ - PCI Express - 3.0\n+ - SATA 3.0\n+ - XFI\n+ - QSGMII\n+ - DDR Controller\n+ - One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four\n+ chip-selects on one DIMM connector. Support is up to 2133MT/s, Although MAX default\n+ with FSL refernce software is 2100MT/s\n+ - 2 QSPI-NOR Spansion(S25FS512SDSMFI011) flash of size 64MB\n+ - IFC/Local Bus\n+ - One 2 GB NAND flash with ECC support, not as boot source\n+ - CPLD of size 2K\n+ - USB 3.0\n+ - Two high speed USB 3.0 ports\n+ - First USB 3.0 port configured as Host with Type-A connector\n+ - Second USB 3.0 port configured as OTG with micro-AB connector\n+ - SDHC/eMMC\n+ - SDHC slot and onboard eMMC are muxed together\n+ - 4 I2C controllers\n+ - Two SATA onboard connectors\n+ - 2 UART\n+ - JTAG support\n+ - QSPI emulator support\n+ - TDM riser support\ndiff --git a/board/freescale/ls1088a/ddr.c b/board/freescale/ls1088a/ddr.c\nnew file mode 100644\nindex 0000000..0ecfd65\n--- /dev/null\n+++ b/board/freescale/ls1088a/ddr.c\n@@ -0,0 +1,102 @@\n+/*\n+ * Copyright 2017 NXP\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \"ddr.h\"\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+void fsl_ddr_board_options(memctl_options_t *popts,\n+\t\t\t dimm_params_t *pdimm,\n+\t\t\t unsigned int ctrl_num)\n+{\n+\tconst struct board_specific_parameters *pbsp, *pbsp_highest = NULL;\n+\tulong ddr_freq;\n+\n+\tif (ctrl_num > 1) {\n+\t\tprintf(\"Not supported controller number %d\\n\", ctrl_num);\n+\t\treturn;\n+\t}\n+\tif (!pdimm->n_ranks)\n+\t\treturn;\n+\n+\t/*\n+\t * we use identical timing for all slots. If needed, change the code\n+\t * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];\n+\t */\n+\tpbsp = udimms[0];\n+\n+\t/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr\n+\t * freqency and n_banks specified in board_specific_parameters table.\n+\t */\n+\tddr_freq = get_ddr_freq(0) / 1000000;\n+\twhile (pbsp->datarate_mhz_high) {\n+\t\tif (pbsp->n_ranks == pdimm->n_ranks) {\n+\t\t\tif (ddr_freq <= pbsp->datarate_mhz_high) {\n+\t\t\t\tpopts->clk_adjust = pbsp->clk_adjust;\n+\t\t\t\tpopts->wrlvl_start = pbsp->wrlvl_start;\n+\t\t\t\tpopts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;\n+\t\t\t\tpopts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;\n+\t\t\t\tgoto found;\n+\t\t\t}\n+\t\t\tpbsp_highest = pbsp;\n+\t\t}\n+\t\tpbsp++;\n+\t}\n+\n+\tif (pbsp_highest) {\n+\t\tprintf(\"Error: board specific timing not found for %lu MT/s\\n\",\n+\t\t ddr_freq);\n+\t\tprintf(\"Trying to use the highest speed (%u) parameters\\n\",\n+\t\t pbsp_highest->datarate_mhz_high);\n+\t\tpopts->clk_adjust = pbsp_highest->clk_adjust;\n+\t\tpopts->wrlvl_start = pbsp_highest->wrlvl_start;\n+\t\tpopts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;\n+\t\tpopts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;\n+\t} else {\n+\t\tpanic(\"DIMM is not supported by this board\");\n+\t}\n+found:\n+\tdebug(\"Found timing match: n_ranks %d, data rate %d, rank_gb %d\\n\"\n+\t\t\"\\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\\n\",\n+\t\tpbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,\n+\t\tpbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,\n+\t\tpbsp->wrlvl_ctl_3);\n+\n+\n+\n+\tpopts->half_strength_driver_enable = 0;\n+\t/*\n+\t * Write leveling override\n+\t */\n+\tpopts->wrlvl_override = 1;\n+\tpopts->wrlvl_sample = 0xf;\n+\n+\n+\t/* Enable ZQ calibration */\n+\tpopts->zq_en = 1;\n+\n+\t/* Enable DDR hashing */\n+\tpopts->addr_hash = 1;\n+\n+\tpopts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);\n+\tpopts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |\n+\t\t\t DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;\n+}\n+\n+\n+int fsl_initdram(void)\n+{\n+\tputs(\"Initializing DDR....using SPD\\n\");\n+\n+\tgd->ram_size = fsl_ddr_sdram();\n+\n+\treturn 0;\n+}\ndiff --git a/board/freescale/ls1088a/ddr.h b/board/freescale/ls1088a/ddr.h\nnew file mode 100644\nindex 0000000..dfcfc1f\n--- /dev/null\n+++ b/board/freescale/ls1088a/ddr.h\n@@ -0,0 +1,44 @@\n+/*\n+ * Copyright 2017 NXP\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __LS1088A_DDR_H__\n+#define __LS1088A_DDR_H__\n+struct board_specific_parameters {\n+\tu32 n_ranks;\n+\tu32 datarate_mhz_high;\n+\tu32 rank_gb;\n+\tu32 clk_adjust;\n+\tu32 wrlvl_start;\n+\tu32 wrlvl_ctl_2;\n+\tu32 wrlvl_ctl_3;\n+};\n+\n+/*\n+ * These tables contain all valid speeds we want to override with board\n+ * specific parameters. datarate_mhz_high values need to be in ascending order\n+ * for each n_ranks group.\n+ */\n+\n+static const struct board_specific_parameters udimm0[] = {\n+\t/*\n+\t * memory controller 0\n+\t * num| hi| rank| clk| wrlvl | wrlvl | wrlvl\n+\t * ranks| mhz| GB |adjst| start | ctl2 | ctl3\n+\t */\n+#if defined(CONFIG_TARGET_LS1088ARDB)\n+\n+\t{2, 1666, 0, 8, 8, 0x090A0B0E, 0x0F10110D,},\n+\t{2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},\n+\t{2, 2300, 0, 8, 9, 0x0A0C0E11, 0x1214160F,},\n+\t{}\n+\n+#endif\n+};\n+\n+static const struct board_specific_parameters *udimms[] = {\n+\tudimm0,\n+};\n+#endif\ndiff --git a/board/freescale/ls1088a/eth_ls1088ardb.c b/board/freescale/ls1088a/eth_ls1088ardb.c\nnew file mode 100644\nindex 0000000..853d815\n--- /dev/null\n+++ b/board/freescale/ls1088a/eth_ls1088ardb.c\n@@ -0,0 +1,102 @@\n+/*\n+ * Copyright 2017 NXP\n+ *\n+ * SPDX-License-Identifier: GPL-2.0+\n+ */\n+\n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+#define MC_BOOT_ENV_VAR \"mcinitcmd\"\n+int board_eth_init(bd_t *bis)\n+{\n+#if defined(CONFIG_FSL_MC_ENET)\n+\tchar *mc_boot_env_var;\n+\tint i, interface;\n+\tstruct memac_mdio_info mdio_info;\n+\tstruct mii_dev *dev;\n+\tstruct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);\n+\tstruct memac_mdio_controller *reg;\n+\tu32 srds_s1, cfg;\n+\n+\tcfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &\n+\t\t\t\tFSL_CHASSIS3_SRDS1_PRTCL_MASK;\n+\tcfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;\n+\n+\tsrds_s1 = serdes_get_number(FSL_SRDS_1, cfg);\n+\n+\treg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;\n+\tmdio_info.regs = reg;\n+\tmdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;\n+\n+\t/* Register the EMI 1 */\n+\tfm_memac_mdio_init(bis, &mdio_info);\n+\n+\treg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;\n+\tmdio_info.regs = reg;\n+\tmdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;\n+\n+\t/* Register the EMI 2 */\n+\tfm_memac_mdio_init(bis, &mdio_info);\n+\n+\tswitch (srds_s1) {\n+\tcase 0x1D:\n+\t\t/*\n+\t\t * XFI does not need a PHY to work, but to avoid U-boot use\n+\t\t * default PHY address which is zero to a MAC when it found\n+\t\t * a MAC has no PHY address, we give a PHY address to XFI\n+\t\t * MAC error.\n+\t\t */\n+\t\twriop_set_phy_address(WRIOP1_DPMAC1, 0x0a);\n+\t\twriop_set_phy_address(WRIOP1_DPMAC2, AQ_PHY_ADDR1);\n+\t\twriop_set_phy_address(WRIOP1_DPMAC3, QSGMII1_PORT1_PHY_ADDR);\n+\t\twriop_set_phy_address(WRIOP1_DPMAC4, QSGMII1_PORT2_PHY_ADDR);\n+\t\twriop_set_phy_address(WRIOP1_DPMAC5, QSGMII1_PORT3_PHY_ADDR);\n+\t\twriop_set_phy_address(WRIOP1_DPMAC6, QSGMII1_PORT4_PHY_ADDR);\n+\t\twriop_set_phy_address(WRIOP1_DPMAC7, QSGMII2_PORT1_PHY_ADDR);\n+\t\twriop_set_phy_address(WRIOP1_DPMAC8, QSGMII2_PORT2_PHY_ADDR);\n+\t\twriop_set_phy_address(WRIOP1_DPMAC9, QSGMII2_PORT3_PHY_ADDR);\n+\t\twriop_set_phy_address(WRIOP1_DPMAC10, QSGMII2_PORT4_PHY_ADDR);\n+\n+\t\tbreak;\n+\tdefault:\n+\t\tprintf(\"SerDes1 protocol 0x%x is not supported on LS1088ARDB\\n\",\n+\t\t srds_s1);\n+\t\tbreak;\n+\t}\n+\n+\tfor (i = WRIOP1_DPMAC3; i <= WRIOP1_DPMAC10; i++) {\n+\t\tinterface = wriop_get_enet_if(i);\n+\t\tswitch (interface) {\n+\t\tcase PHY_INTERFACE_MODE_QSGMII:\n+\t\t\tdev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);\n+\t\t\twriop_set_mdio(i, dev);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tdev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);\n+\twriop_set_mdio(WRIOP1_DPMAC2, dev);\n+\n+\tmc_boot_env_var = env_get(MC_BOOT_ENV_VAR);\n+\tif (mc_boot_env_var)\n+\t\trun_command_list(mc_boot_env_var, -1, 0);\n+\tcpu_eth_init(bis);\n+#endif /* CONFIG_FMAN_ENET */\n+\n+\treturn pci_eth_init(bis);\n+}\ndiff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c\nnew file mode 100644\nindex 0000000..a022da9\n--- /dev/null\n+++ b/board/freescale/ls1088a/ls1088a.c\n@@ -0,0 +1,332 @@\n+/*\n+ * Copyright 2017 NXP\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+\n+#include \"../common/qixis.h\"\n+#include \"ls1088a_qixis.h\"\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+unsigned long long get_qixis_addr(void)\n+{\n+\tunsigned long long addr;\n+\n+\tif (gd->flags & GD_FLG_RELOC)\n+\t\taddr = QIXIS_BASE_PHYS;\n+\telse\n+\t\taddr = QIXIS_BASE_PHYS_EARLY;\n+\n+\t/*\n+\t * IFC address under 256MB is mapped to 0x30000000, any address above\n+\t * is mapped to 0x5_10000000 up to 4GB.\n+\t */\n+\taddr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;\n+\n+\treturn addr;\n+}\n+\n+int checkboard(void)\n+{\n+\tchar buf[64];\n+\tu8 sw;\n+\tstatic const char *const freq[] = {\"100\", \"125\", \"156.25\",\n+\t\t\t\t\t \"100 separate SSCG\"};\n+\tint clock;\n+\n+\n+\tprintf(\"Board: LS1088A-RDB, \");\n+\n+\tsw = QIXIS_READ(arch);\n+\tprintf(\"Board Arch: V%d, \", sw >> 4);\n+\n+\tprintf(\"Board version: %c, boot from \", (sw & 0xf) + 'A');\n+\n+\n+\tmemset((u8 *)buf, 0x00, ARRAY_SIZE(buf));\n+\n+\tsw = QIXIS_READ(brdcfg[0]);\n+\tsw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;\n+\n+#ifdef CONFIG_SD_BOOT\n+\tputs(\"SD card\\n\");\n+#endif\n+\tswitch (sw) {\n+\tcase 0:\n+\n+\t\tputs(\"QSPI:\");\n+\t\tsw = QIXIS_READ(brdcfg[0]);\n+\t\tsw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;\n+\t\tif (sw == 0 || sw == 4)\n+\t\t\tputs(\"0\\n\");\n+\t\telse if (sw == 1)\n+\t\t\tputs(\"1\\n\");\n+\t\telse\n+\t\t\tputs(\"EMU\\n\");\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tprintf(\"invalid setting of SW%u\\n\", QIXIS_LBMAP_SWITCH);\n+\t\tbreak;\n+\t}\n+\n+\n+\tprintf(\"CPLD: v%d.%d\\n\", QIXIS_READ(scver), QIXIS_READ(tagdata));\n+\n+\n+\t/*\n+\t * Display the actual SERDES reference clocks as configured by the\n+\t * dip switches on the board. Note that the SWx registers could\n+\t * technically be set to force the reference clocks to match the\n+\t * values that the SERDES expects (or vice versa). For now, however,\n+\t * we just display both values and hope the user notices when they\n+\t * don't match.\n+\t */\n+\tputs(\"SERDES1 Reference : \");\n+\tsw = QIXIS_READ(brdcfg[2]);\n+\tclock = (sw >> 6) & 3;\n+\tprintf(\"Clock1 = %sMHz \", freq[clock]);\n+\tclock = (sw >> 4) & 3;\n+\tprintf(\"Clock2 = %sMHz\", freq[clock]);\n+\n+\tputs(\"\\nSERDES2 Reference : \");\n+\tclock = (sw >> 2) & 3;\n+\tprintf(\"Clock1 = %sMHz \", freq[clock]);\n+\tclock = (sw >> 0) & 3;\n+\tprintf(\"Clock2 = %sMHz\\n\", freq[clock]);\n+\n+\treturn 0;\n+}\n+\n+bool if_board_diff_clk(void)\n+{\n+\tu8 diff_conf = QIXIS_READ(dutcfg[11]);\n+\treturn diff_conf & 0x80;\n+}\n+\n+unsigned long get_board_sys_clk(void)\n+{\n+\tu8 sysclk_conf = QIXIS_READ(brdcfg[1]);\n+\n+\tswitch (sysclk_conf & 0x0f) {\n+\tcase QIXIS_SYSCLK_83:\n+\t\treturn 83333333;\n+\tcase QIXIS_SYSCLK_100:\n+\t\treturn 100000000;\n+\tcase QIXIS_SYSCLK_125:\n+\t\treturn 125000000;\n+\tcase QIXIS_SYSCLK_133:\n+\t\treturn 133333333;\n+\tcase QIXIS_SYSCLK_150:\n+\t\treturn 150000000;\n+\tcase QIXIS_SYSCLK_160:\n+\t\treturn 160000000;\n+\tcase QIXIS_SYSCLK_166:\n+\t\treturn 166666666;\n+\t}\n+\n+\treturn 66666666;\n+}\n+\n+unsigned long get_board_ddr_clk(void)\n+{\n+\tu8 ddrclk_conf = QIXIS_READ(brdcfg[1]);\n+\n+\tif (if_board_diff_clk())\n+\t\treturn get_board_sys_clk();\n+\tswitch ((ddrclk_conf & 0x30) >> 4) {\n+\tcase QIXIS_DDRCLK_100:\n+\t\treturn 100000000;\n+\tcase QIXIS_DDRCLK_125:\n+\t\treturn 125000000;\n+\tcase QIXIS_DDRCLK_133:\n+\t\treturn 133333333;\n+\t}\n+\n+\treturn 66666666;\n+}\n+\n+int select_i2c_ch_pca9547(u8 ch)\n+{\n+\tint ret;\n+\n+\tret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);\n+\tif (ret) {\n+\t\tputs(\"PCA: failed to select proper channel\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+void board_retimer_init(void)\n+{\n+\tu8 reg;\n+\n+\t/* Retimer is connected to I2C1_CH5 */\n+\tselect_i2c_ch_pca9547(I2C_MUX_CH5);\n+\n+\t/* Access to Control/Shared register */\n+\treg = 0x0;\n+\ti2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);\n+\n+\t/* Read device revision and ID */\n+\ti2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);\n+\tdebug(\"Retimer version id = 0x%x\\n\", reg);\n+\n+\t/* Enable Broadcast. All writes target all channel register sets */\n+\treg = 0x0c;\n+\ti2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);\n+\n+\t/* Reset Channel Registers */\n+\ti2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);\n+\treg |= 0x4;\n+\ti2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);\n+\n+\t/* Set data rate as 10.3125 Gbps */\n+\treg = 0x90;\n+\ti2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);\n+\treg = 0xb3;\n+\ti2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);\n+\treg = 0x90;\n+\ti2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);\n+\treg = 0xb3;\n+\ti2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);\n+\treg = 0xcd;\n+\ti2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);\n+\n+\t/* Select VCO Divider to full rate (000) */\n+\ti2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);\n+\treg &= 0x0f;\n+\treg |= 0x70;\n+\ti2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);\n+\n+\n+\t/*return the default channel*/\n+\tselect_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);\n+}\n+\n+int board_init(void)\n+{\n+\tinit_final_memctl_regs();\n+#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)\n+\tu32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;\n+#endif\n+\n+\tselect_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);\n+\tboard_retimer_init();\n+\n+#ifdef CONFIG_ENV_IS_NOWHERE\n+\tgd->env_addr = (ulong)&default_environment[0];\n+#endif\n+\n+#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)\n+\t/* invert AQR105 IRQ pins polarity */\n+\tout_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);\n+#endif\n+\n+#ifdef CONFIG_FSL_LS_PPA\n+\tppa_init();\n+#endif\n+\treturn 0;\n+}\n+\n+int board_early_init_f(void)\n+{\n+\tfsl_lsch3_early_init_f();\n+\treturn 0;\n+}\n+\n+void detail_board_ddr_info(void)\n+{\n+\tputs(\"\\nDDR \");\n+\tprint_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, \"\");\n+\tprint_ddr_info(0);\n+}\n+\n+#if defined(CONFIG_ARCH_MISC_INIT)\n+int arch_misc_init(void)\n+{\n+#ifdef CONFIG_FSL_CAAM\n+\tsec_init();\n+#endif\n+\treturn 0;\n+}\n+#endif\n+\n+#ifdef CONFIG_FSL_MC_ENET\n+void fdt_fixup_board_enet(void *fdt)\n+{\n+\tint offset;\n+\n+\toffset = fdt_path_offset(fdt, \"/fsl-mc\");\n+\n+\tif (offset < 0)\n+\t\toffset = fdt_path_offset(fdt, \"/fsl,dprc@0\");\n+\n+\tif (offset < 0) {\n+\t\tprintf(\"%s: ERROR: fsl-mc node not found in device tree (error %d)\\n\",\n+\t\t __func__, offset);\n+\t\treturn;\n+\t}\n+\n+\tif (get_mc_boot_status() == 0)\n+\t\tfdt_status_okay(fdt, offset);\n+\telse\n+\t\tfdt_status_fail(fdt, offset);\n+}\n+#endif\n+\n+#ifdef CONFIG_OF_BOARD_SETUP\n+int ft_board_setup(void *blob, bd_t *bd)\n+{\n+\tint err, i;\n+\tu64 base[CONFIG_NR_DRAM_BANKS];\n+\tu64 size[CONFIG_NR_DRAM_BANKS];\n+\n+\tft_cpu_setup(blob, bd);\n+\n+\t/* fixup DT for the two GPP DDR banks */\n+\tfor (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {\n+\t\tbase[i] = gd->bd->bi_dram[i].start;\n+\t\tsize[i] = gd->bd->bi_dram[i].size;\n+\t}\n+\n+#ifdef CONFIG_RESV_RAM\n+\t/* reduce size if reserved memory is within this bank */\n+\tif (gd->arch.resv_ram >= base[0] &&\n+\t gd->arch.resv_ram < base[0] + size[0])\n+\t\tsize[0] = gd->arch.resv_ram - base[0];\n+\telse if (gd->arch.resv_ram >= base[1] &&\n+\t\t gd->arch.resv_ram < base[1] + size[1])\n+\t\tsize[1] = gd->arch.resv_ram - base[1];\n+#endif\n+\n+\tfdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);\n+\n+#ifdef CONFIG_FSL_MC_ENET\n+\tfdt_fixup_board_enet(blob);\n+\terr = fsl_mc_ldpaa_exit(bd);\n+\tif (err)\n+\t\treturn err;\n+#endif\n+\n+\treturn 0;\n+}\n+#endif\ndiff --git a/board/freescale/ls1088a/ls1088a_qixis.h b/board/freescale/ls1088a/ls1088a_qixis.h\nnew file mode 100644\nindex 0000000..9757d1b\n--- /dev/null\n+++ b/board/freescale/ls1088a/ls1088a_qixis.h\n@@ -0,0 +1,34 @@\n+/*\n+ * Copyright 2017 NXP\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __LS1088AQDS_QIXIS_H__\n+#define __LS1088AQDS_QIXIS_H__\n+\n+/* Definitions of QIXIS Registers for LS1088AQDS */\n+\n+/* SYSCLK */\n+#define QIXIS_SYSCLK_66\t\t\t0x0\n+#define QIXIS_SYSCLK_83\t\t\t0x1\n+#define QIXIS_SYSCLK_100\t\t0x2\n+#define QIXIS_SYSCLK_125\t\t0x3\n+#define QIXIS_SYSCLK_133\t\t0x4\n+#define QIXIS_SYSCLK_150\t\t0x5\n+#define QIXIS_SYSCLK_160\t\t0x6\n+#define QIXIS_SYSCLK_166\t\t0x7\n+\n+/* DDRCLK */\n+#define QIXIS_DDRCLK_66\t\t\t0x0\n+#define QIXIS_DDRCLK_100\t\t0x1\n+#define QIXIS_DDRCLK_125\t\t0x2\n+#define QIXIS_DDRCLK_133\t\t0x3\n+\n+/* BRDCFG2 - SD clock*/\n+#define QIXIS_SDCLK1_100\t\t0x0\n+#define QIXIS_SDCLK1_125\t\t0x1\n+#define QIXIS_SDCLK1_165\t\t0x2\n+#define QIXIS_SDCLK1_100_SP\t\t0x3\n+\n+#endif\ndiff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig\nnew file mode 100644\nindex 0000000..33e4124\n--- /dev/null\n+++ b/configs/ls1088ardb_qspi_defconfig\n@@ -0,0 +1,29 @@\n+CONFIG_ARM=y\n+CONFIG_TARGET_LS1088ARDB=y\n+# CONFIG_SYS_MALLOC_F is not set\n+CONFIG_DM_SPI=y\n+CONFIG_DM_SPI_FLASH=y\n+CONFIG_DEFAULT_DEVICE_TREE=\"fsl-ls1088a-rdb\"\n+CONFIG_FIT=y\n+CONFIG_FIT_VERBOSE=y\n+CONFIG_OF_BOARD_SETUP=y\n+CONFIG_OF_STDOUT_VIA_ALIAS=y\n+CONFIG_SYS_EXTRA_OPTIONS=\"SYS_FSL_DDR4, QSPI_BOOT\"\n+CONFIG_HUSH_PARSER=y\n+CONFIG_CMD_MMC=y\n+CONFIG_CMD_SF=y\n+CONFIG_CMD_I2C=y\n+# CONFIG_CMD_SETEXPR is not set\n+CONFIG_CMD_DHCP=y\n+CONFIG_CMD_PING=y\n+CONFIG_OF_CONTROL=y\n+CONFIG_NET_RANDOM_ETHADDR=y\n+CONFIG_DM=y\n+CONFIG_SPI_FLASH=y\n+CONFIG_NETDEVICES=y\n+CONFIG_E1000=y\n+CONFIG_SYS_NS16550=y\n+CONFIG_FSL_DSPI=y\n+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y\n+# CONFIG_DISPLAY_BOARDINFO is not set\n+CONFIG_FSL_LS_PPA=y\ndiff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h\nnew file mode 100644\nindex 0000000..c78ba5d\n--- /dev/null\n+++ b/include/configs/ls1088a_common.h\n@@ -0,0 +1,201 @@\n+/*\n+ * Copyright 2017 NXP\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __LS1088_COMMON_H\n+#define __LS1088_COMMON_H\n+\n+\n+#define CONFIG_REMAKE_ELF\n+#define CONFIG_FSL_LAYERSCAPE\n+#define CONFIG_MP\n+\n+#include \n+#include \n+#include \n+\n+/* Link Definitions */\n+#define CONFIG_SYS_INIT_SP_ADDR\t\t(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)\n+\n+/* Link Definitions */\n+#ifdef CONFIG_QSPI_BOOT\n+#define CONFIG_SYS_TEXT_BASE 0x20100000\n+#else\n+#define CONFIG_SYS_TEXT_BASE\t\t0x30100000\n+#endif\n+\n+#define CONFIG_SUPPORT_RAW_INITRD\n+\n+\n+#define CONFIG_SKIP_LOWLEVEL_INIT\n+\n+#define CONFIG_FSL_DDR_INTERACTIVE\t/* Interactive debugging */\n+\n+#define CONFIG_VERY_BIG_RAM\n+#define CONFIG_SYS_DDR_SDRAM_BASE\t0x80000000UL\n+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY\t0\n+#define CONFIG_SYS_SDRAM_BASE\t\tCONFIG_SYS_DDR_SDRAM_BASE\n+#define CONFIG_SYS_DDR_BLOCK2_BASE\t0x8080000000ULL\n+#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS\t1\n+/*\n+ * SMP Definitinos\n+ */\n+#define CPU_RELEASE_ADDR\t\tsecondary_boot_func\n+\n+/* Size of malloc() pool */\n+#define CONFIG_SYS_MALLOC_LEN\t\t(CONFIG_ENV_SIZE + 2048 * 1024)\n+\n+/* I2C */\n+#define CONFIG_SYS_I2C\n+#define CONFIG_SYS_I2C_MXC\n+#define CONFIG_SYS_I2C_MXC_I2C1\t\t/* enable I2C bus 1 */\n+#define CONFIG_SYS_I2C_MXC_I2C2\t\t/* enable I2C bus 2 */\n+#define CONFIG_SYS_I2C_MXC_I2C3\t\t/* enable I2C bus 3 */\n+#define CONFIG_SYS_I2C_MXC_I2C4\t\t/* enable I2C bus 4 */\n+\n+/* Serial Port */\n+#define CONFIG_CONS_INDEX 1\n+#define CONFIG_SYS_NS16550_SERIAL\n+#define CONFIG_SYS_NS16550_REG_SIZE 1\n+#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)\n+\n+#define CONFIG_BAUDRATE\t\t\t115200\n+#define CONFIG_SYS_BAUDRATE_TABLE\t{ 9600, 19200, 38400, 57600, 115200 }\n+\n+/* IFC */\n+#define CONFIG_FSL_IFC\n+\n+/*\n+ * During booting, IFC is mapped at the region of 0x30000000.\n+ * But this region is limited to 256MB. To accommodate NOR, promjet\n+ * and FPGA. This region is divided as below:\n+ * 0x30000000 - 0x37ffffff : 128MB : NOR flash\n+ * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet\n+ * 0x3C000000 - 0x40000000 : 64MB : FPGA etc\n+ *\n+ * To accommodate bigger NOR flash and other devices, we will map IFC\n+ * chip selects to as below:\n+ * 0x5_1000_0000..0x5_1fff_ffff\tMemory Hole\n+ * 0x5_2000_0000..0x5_3fff_ffff\tIFC CSx (FPGA, NAND and others 512MB)\n+ * 0x5_4000_0000..0x5_7fff_ffff\tASIC or others 1GB\n+ * 0x5_8000_0000..0x5_bfff_ffff\tIFC CS0 1GB (NOR/Promjet)\n+ * 0x5_C000_0000..0x5_ffff_ffff\tIFC CS1 1GB (NOR/Promjet)\n+ *\n+ * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.\n+ * CONFIG_SYS_FLASH_BASE has the final address (core view)\n+ * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)\n+ * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address\n+ * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting\n+ */\n+\n+#define CONFIG_SYS_FLASH_BASE\t\t\t0x580000000ULL\n+#define CONFIG_SYS_FLASH_BASE_PHYS\t\t0x80000000\n+#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY\t0x00000000\n+\n+#define CONFIG_SYS_FLASH1_BASE_PHYS\t\t0xC0000000\n+#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY\t0x8000000\n+\n+#ifndef __ASSEMBLY__\n+unsigned long long get_qixis_addr(void);\n+#endif\n+\n+#define QIXIS_BASE\t\t\t\tget_qixis_addr()\n+#define QIXIS_BASE_PHYS\t\t\t\t0x20000000\n+#define QIXIS_BASE_PHYS_EARLY\t\t\t0xC000000\n+\n+\n+#define CONFIG_SYS_NAND_BASE\t\t\t0x530000000ULL\n+#define CONFIG_SYS_NAND_BASE_PHYS\t\t0x30000000\n+\n+\n+/* MC firmware */\n+/* TODO Actual DPL max length needs to be confirmed with the MC FW team */\n+#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH\t 0x20000\n+#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000\n+#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH\t 0x20000\n+#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000\n+#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH\t0x200000\n+#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET\t0x07000000\n+/*\n+ * Carve out a DDR region which will not be used by u-boot/Linux\n+ *\n+ * It will be used by MC and Debug Server. The MC region must be\n+ * 512MB aligned, so the min size to hide is 512MB.\n+ */\n+\n+#if defined(CONFIG_FSL_MC_ENET)\n+#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE\t\t(512UL * 1024 * 1024)\n+#endif\n+\n+#define CONFIG_FSL_CAAM\t\t\t/* Enable SEC/CAAM */\n+\n+/* Command line configuration */\n+#define CONFIG_CMD_GREPENV\n+#define CONFIG_CMD_CACHE\n+\n+/* Miscellaneous configurable options */\n+#define CONFIG_SYS_LOAD_ADDR\t(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)\n+\n+/* Physical Memory Map */\n+#define CONFIG_CHIP_SELECTS_PER_CTRL\t4\n+\n+#define CONFIG_NR_DRAM_BANKS\t\t2\n+\n+#define CONFIG_HWCONFIG\n+#define HWCONFIG_BUFFER_SIZE\t\t128\n+\n+/* #define CONFIG_DISPLAY_CPUINFO */\n+\n+/* Allow to overwrite serial and ethaddr */\n+#define CONFIG_ENV_OVERWRITE\n+\n+/* Initial environment variables */\n+#define CONFIG_EXTRA_ENV_SETTINGS\t\t\\\n+\t\"hwconfig=fsl_ddr:bank_intlv=auto\\0\"\t\\\n+\t\"loadaddr=0x80100000\\0\"\t\t\t\\\n+\t\"kernel_addr=0x100000\\0\"\t\t\\\n+\t\"ramdisk_addr=0x800000\\0\"\t\t\\\n+\t\"ramdisk_size=0x2000000\\0\"\t\t\\\n+\t\"fdt_high=0xa0000000\\0\"\t\t\t\\\n+\t\"initrd_high=0xffffffffffffffff\\0\"\t\\\n+\t\"kernel_start=0x581000000\\0\"\t\t\\\n+\t\"kernel_load=0xa0000000\\0\"\t\t\\\n+\t\"kernel_size=0x2800000\\0\"\t\t\\\n+\t\"console=ttyAMA0,38400n8\\0\"\t\t\\\n+\t\"mcinitcmd=fsl_mc start mc 0x580a00000\"\t\\\n+\t\" 0x580e00000 \\0\"\n+\n+#define CONFIG_BOOTARGS\t\t\"console=ttyS0,115200 root=/dev/ram0 \" \\\n+\t\t\t\t\"earlycon=uart8250,mmio,0x21c0500 \" \\\n+\t\t\t\t\"ramdisk_size=0x3000000 default_hugepagesz=2m\" \\\n+\t\t\t\t\" hugepagesz=2m hugepages=256\"\n+#if defined(CONFIG_QSPI_BOOT)\n+#define CONFIG_BOOTCOMMAND\t\"sf probe 0:0;\" \\\n+\t\t\t\t\"sf read 0x80200000 0xd00000 0x100000;\"\\\n+\t\t\t\t\" fsl_mc apply dpl 0x80200000 &&\" \\\n+\t\t\t\t\" sf read $kernel_load $kernel_start\" \\\n+\t\t\t\t\" $kernel_size && bootm $kernel_load\"\n+#else /* NOR BOOT*/\n+#define CONFIG_BOOTCOMMAND\t\"fsl_mc apply dpl 0x580d00000 &&\" \\\n+\t\t\t\t\" cp.b $kernel_start $kernel_load\" \\\n+\t\t\t\t\" $kernel_size && bootm $kernel_load\"\n+#endif\n+\n+/* Monitor Command Prompt */\n+#define CONFIG_SYS_CBSIZE\t\t512\t/* Console I/O Buffer Size */\n+#define CONFIG_SYS_PBSIZE\t\t(CONFIG_SYS_CBSIZE + \\\n+\t\t\t\t\tsizeof(CONFIG_SYS_PROMPT) + 16)\n+#define CONFIG_SYS_PROMPT_HUSH_PS2\t\"> \"\n+#define CONFIG_SYS_BARGSIZE\t\tCONFIG_SYS_CBSIZE /* Boot args buffer */\n+#define CONFIG_SYS_LONGHELP\n+#define CONFIG_CMDLINE_EDITING\t\t1\n+#define CONFIG_AUTO_COMPLETE\n+#define CONFIG_SYS_MAXARGS\t\t64\t/* max command args */\n+\n+#define CONFIG_PANIC_HANG\t/* do not reset board on panic */\n+\n+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */\n+\n+#endif /* __LS1088_COMMON_H */\ndiff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h\nnew file mode 100644\nindex 0000000..bab83b1\n--- /dev/null\n+++ b/include/configs/ls1088ardb.h\n@@ -0,0 +1,319 @@\n+/*\n+ * Copyright 2017 NXP\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __LS1088A_RDB_H\n+#define __LS1088A_RDB_H\n+\n+#include \"ls1088a_common.h\"\n+\n+#define CONFIG_DISPLAY_BOARDINFO_LATE\n+\n+#if defined(CONFIG_QSPI_BOOT)\n+#define CONFIG_ENV_IS_IN_SPI_FLASH\n+#define CONFIG_ENV_SIZE\t\t\t0x2000 /* 8KB */\n+#define CONFIG_ENV_OFFSET\t\t0x300000 /* 3MB */\n+#define CONFIG_ENV_SECT_SIZE\t\t0x40000\n+#else\n+#define CONFIG_ENV_IS_IN_FLASH\n+#define CONFIG_ENV_ADDR\t\t\t(CONFIG_SYS_FLASH_BASE + 0x300000)\n+#define CONFIG_ENV_SECT_SIZE\t\t0x20000\n+#define CONFIG_ENV_SIZE\t\t\t0x20000\n+#endif\n+\n+#if defined(CONFIG_QSPI_BOOT)\n+#define CONFIG_QIXIS_I2C_ACCESS\n+#define SYS_NO_FLASH\n+#undef CONFIG_CMD_IMLS\n+#endif\n+\n+#define CONFIG_SYS_CLK_FREQ\t\t100000000\n+#define CONFIG_DDR_CLK_FREQ\t\t100000000\n+#define COUNTER_FREQUENCY_REAL\t\t25000000\t/* 25MHz */\n+#define COUNTER_FREQUENCY\t\t25000000\t/* 25MHz */\n+\n+#define CONFIG_DDR_SPD\n+#ifdef CONFIG_EMU\n+#define CONFIG_SYS_FSL_DDR_EMU\n+#define CONFIG_SYS_MXC_I2C1_SPEED\t40000000\n+#define CONFIG_SYS_MXC_I2C2_SPEED\t40000000\n+#else\n+#define CONFIG_DDR_ECC\n+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER\n+#define CONFIG_MEM_INIT_VALUE\t\t0xdeadbeef\n+#endif\n+#define SPD_EEPROM_ADDRESS\t0x51\n+#define CONFIG_SYS_SPD_BUS_NUM\t0\t/* SPD on I2C bus 0 */\n+#define CONFIG_DIMM_SLOTS_PER_CTLR\t1\n+\n+\n+#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)\n+#define CONFIG_SYS_NOR0_CSPR_EXT\t(0x0)\n+#define CONFIG_SYS_NOR_AMASK\t\tIFC_AMASK(128 * 1024 * 1024)\n+#define CONFIG_SYS_NOR_AMASK_EARLY\tIFC_AMASK(64 * 1024 * 1024)\n+\n+#define CONFIG_SYS_NOR0_CSPR\t\t\t\t\t\\\n+\t(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)\t\t| \\\n+\tCSPR_PORT_SIZE_16\t\t\t\t\t| \\\n+\tCSPR_MSEL_NOR\t\t\t\t\t\t| \\\n+\tCSPR_V)\n+#define CONFIG_SYS_NOR0_CSPR_EARLY\t\t\t\t\\\n+\t(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)\t| \\\n+\tCSPR_PORT_SIZE_16\t\t\t\t\t| \\\n+\tCSPR_MSEL_NOR\t\t\t\t\t\t| \\\n+\tCSPR_V)\n+#define CONFIG_SYS_NOR_CSOR\tCSOR_NOR_ADM_SHIFT(6)\n+#define CONFIG_SYS_NOR_FTIM0\t(FTIM0_NOR_TACSE(0x1) | \\\n+\t\t\t\tFTIM0_NOR_TEADC(0x1) | \\\n+\t\t\t\tFTIM0_NOR_TEAHC(0x1))\n+#define CONFIG_SYS_NOR_FTIM1\t(FTIM1_NOR_TACO(0x1) | \\\n+\t\t\t\tFTIM1_NOR_TRAD_NOR(0x1))\n+#define CONFIG_SYS_NOR_FTIM2\t(FTIM2_NOR_TCS(0x0) | \\\n+\t\t\t\tFTIM2_NOR_TCH(0x0) | \\\n+\t\t\t\tFTIM2_NOR_TWP(0x1))\n+#define CONFIG_SYS_NOR_FTIM3\t0x04000000\n+#define CONFIG_SYS_IFC_CCR\t0x01000000\n+\n+#ifndef SYS_NO_FLASH\n+#define CONFIG_FLASH_CFI_DRIVER\n+#define CONFIG_SYS_FLASH_CFI\n+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE\n+#define CONFIG_SYS_FLASH_QUIET_TEST\n+#define CONFIG_FLASH_SHOW_PROGRESS\t45 /* count down from 45/5: 9..1 */\n+\n+#define CONFIG_SYS_MAX_FLASH_BANKS\t1\t/* number of banks */\n+#define CONFIG_SYS_MAX_FLASH_SECT\t1024\t/* sectors per device */\n+#define CONFIG_SYS_FLASH_ERASE_TOUT\t60000\t/* Flash Erase Timeout (ms) */\n+#define CONFIG_SYS_FLASH_WRITE_TOUT\t500\t/* Flash Write Timeout (ms) */\n+\n+#define CONFIG_SYS_FLASH_EMPTY_INFO\n+#define CONFIG_SYS_FLASH_BANKS_LIST\t{ CONFIG_SYS_FLASH_BASE }\n+#endif\n+#endif\n+#define CONFIG_NAND_FSL_IFC\n+#define CONFIG_SYS_NAND_MAX_ECCPOS\t256\n+#define CONFIG_SYS_NAND_MAX_OOBFREE\t2\n+\n+#define CONFIG_SYS_NAND_CSPR_EXT\t(0x0)\n+#define CONFIG_SYS_NAND_CSPR\t(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \\\n+\t\t\t\t| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \\\n+\t\t\t\t| CSPR_MSEL_NAND\t/* MSEL = NAND */ \\\n+\t\t\t\t| CSPR_V)\n+#define CONFIG_SYS_NAND_AMASK\tIFC_AMASK(64 * 1024)\n+\n+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \\\n+\t\t\t\t| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \\\n+\t\t\t\t| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \\\n+\t\t\t\t| CSOR_NAND_RAL_3\t/* RAL = 3Byes */ \\\n+\t\t\t\t| CSOR_NAND_PGS_2K\t/* Page Size = 2K */ \\\n+\t\t\t\t| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \\\n+\t\t\t\t| CSOR_NAND_PB(64))\t/*Pages Per Block = 64*/\n+\n+#define CONFIG_SYS_NAND_ONFI_DETECTION\n+\n+/* ONFI NAND Flash mode0 Timing Params */\n+#define CONFIG_SYS_NAND_FTIM0\t\t(FTIM0_NAND_TCCST(0x07) | \\\n+\t\t\t\t\tFTIM0_NAND_TWP(0x18) | \\\n+\t\t\t\t\tFTIM0_NAND_TWCHT(0x07) | \\\n+\t\t\t\t\tFTIM0_NAND_TWH(0x0a))\n+#define CONFIG_SYS_NAND_FTIM1\t\t(FTIM1_NAND_TADLE(0x32) | \\\n+\t\t\t\t\tFTIM1_NAND_TWBE(0x39) | \\\n+\t\t\t\t\tFTIM1_NAND_TRR(0x0e) | \\\n+\t\t\t\t\tFTIM1_NAND_TRP(0x18))\n+#define CONFIG_SYS_NAND_FTIM2\t\t(FTIM2_NAND_TRAD(0x0f) | \\\n+\t\t\t\t\tFTIM2_NAND_TREH(0x0a) | \\\n+\t\t\t\t\tFTIM2_NAND_TWHRE(0x1e))\n+#define CONFIG_SYS_NAND_FTIM3\t\t0x0\n+\n+#define CONFIG_SYS_NAND_BASE_LIST\t{ CONFIG_SYS_NAND_BASE }\n+#define CONFIG_SYS_MAX_NAND_DEVICE\t1\n+#define CONFIG_MTD_NAND_VERIFY_WRITE\n+#define CONFIG_CMD_NAND\n+\n+#define CONFIG_SYS_NAND_BLOCK_SIZE\t(128 * 1024)\n+\n+#define CONFIG_FSL_QIXIS\n+#define CONFIG_SYS_I2C_FPGA_ADDR\t0x66\n+#define QIXIS_LBMAP_SWITCH\t\t2\n+#define QIXIS_QMAP_MASK\t\t\t0xe0\n+#define QIXIS_QMAP_SHIFT\t\t5\n+#define QIXIS_LBMAP_MASK\t\t0x1f\n+#define QIXIS_LBMAP_SHIFT\t\t5\n+#define QIXIS_LBMAP_DFLTBANK\t\t0x00\n+#define QIXIS_LBMAP_ALTBANK\t\t0x20\n+#define QIXIS_LBMAP_SD\t\t\t0x00\n+#define QIXIS_LBMAP_SD_QSPI\t\t0x00\n+#define QIXIS_LBMAP_QSPI\t\t0x00\n+#define QIXIS_RCW_SRC_SD\t\t0x40\n+#define QIXIS_RCW_SRC_QSPI\t\t0x62\n+#define QIXIS_RST_CTL_RESET\t\t0x31\n+#define QIXIS_RCFG_CTL_RECONFIG_IDLE\t0x20\n+#define QIXIS_RCFG_CTL_RECONFIG_START\t0x21\n+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE\t0x08\n+#define\tQIXIS_RST_FORCE_MEM\t\t0x01\n+\n+#define CONFIG_SYS_FPGA_CSPR_EXT\t(0x0)\n+#define CONFIG_SYS_FPGA_CSPR\t\t(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \\\n+\t\t\t\t\t| CSPR_PORT_SIZE_8 \\\n+\t\t\t\t\t| CSPR_MSEL_GPCM \\\n+\t\t\t\t\t| CSPR_V)\n+#define SYS_FPGA_CSPR_FINAL\t(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \\\n+\t\t\t\t\t| CSPR_PORT_SIZE_8 \\\n+\t\t\t\t\t| CSPR_MSEL_GPCM \\\n+\t\t\t\t\t| CSPR_V)\n+\n+#define CONFIG_SYS_FPGA_AMASK\t\tIFC_AMASK(64*1024)\n+#define CONFIG_SYS_FPGA_CSOR\t\tCSOR_GPCM_ADM_SHIFT(0)\n+/* QIXIS Timing parameters*/\n+#define SYS_FPGA_CS_FTIM0\t(FTIM0_GPCM_TACSE(0x0e) | \\\n+\t\t\t\t\tFTIM0_GPCM_TEADC(0x0e) | \\\n+\t\t\t\t\tFTIM0_GPCM_TEAHC(0x0e))\n+#define SYS_FPGA_CS_FTIM1\t(FTIM1_GPCM_TACO(0xff) | \\\n+\t\t\t\t\tFTIM1_GPCM_TRAD(0x3f))\n+#define SYS_FPGA_CS_FTIM2\t(FTIM2_GPCM_TCS(0xf) | \\\n+\t\t\t\t\tFTIM2_GPCM_TCH(0xf) | \\\n+\t\t\t\t\tFTIM2_GPCM_TWP(0x3E))\n+#define SYS_FPGA_CS_FTIM3\t0x0\n+\n+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)\n+#define CONFIG_SYS_CSPR0_EXT\t\tCONFIG_SYS_NAND_CSPR_EXT\n+#define CONFIG_SYS_CSPR0\t\tCONFIG_SYS_NAND_CSPR\n+#define CONFIG_SYS_AMASK0\t\tCONFIG_SYS_NAND_AMASK\n+#define CONFIG_SYS_CSOR0\t\tCONFIG_SYS_NAND_CSOR\n+#define CONFIG_SYS_CS0_FTIM0\t\tCONFIG_SYS_NAND_FTIM0\n+#define CONFIG_SYS_CS0_FTIM1\t\tCONFIG_SYS_NAND_FTIM1\n+#define CONFIG_SYS_CS0_FTIM2\t\tCONFIG_SYS_NAND_FTIM2\n+#define CONFIG_SYS_CS0_FTIM3\t\tCONFIG_SYS_NAND_FTIM3\n+#define CONFIG_SYS_CSPR2_EXT\t\tCONFIG_SYS_FPGA_CSPR_EXT\n+#define CONFIG_SYS_CSPR2\t\tCONFIG_SYS_FPGA_CSPR\n+#define CONFIG_SYS_CSPR2_FINAL\t\tSYS_FPGA_CSPR_FINAL\n+#define CONFIG_SYS_AMASK2\t\tCONFIG_SYS_FPGA_AMASK\n+#define CONFIG_SYS_CSOR2\t\tCONFIG_SYS_FPGA_CSOR\n+#define CONFIG_SYS_CS2_FTIM0\t\tSYS_FPGA_CS_FTIM0\n+#define CONFIG_SYS_CS2_FTIM1\t\tSYS_FPGA_CS_FTIM1\n+#define CONFIG_SYS_CS2_FTIM2\t\tSYS_FPGA_CS_FTIM2\n+#define CONFIG_SYS_CS2_FTIM3\t\tSYS_FPGA_CS_FTIM3\n+#else\n+#define CONFIG_SYS_CSPR0_EXT\t\tCONFIG_SYS_NOR0_CSPR_EXT\n+#define CONFIG_SYS_CSPR0\t\tCONFIG_SYS_NOR0_CSPR_EARLY\n+#define CONFIG_SYS_CSPR0_FINAL\t\tCONFIG_SYS_NOR0_CSPR\n+#define CONFIG_SYS_AMASK0\t\tCONFIG_SYS_NOR_AMASK\n+#define CONFIG_SYS_CSOR0\t\tCONFIG_SYS_NOR_CSOR\n+#define CONFIG_SYS_CS0_FTIM0\t\tCONFIG_SYS_NOR_FTIM0\n+#define CONFIG_SYS_CS0_FTIM1\t\tCONFIG_SYS_NOR_FTIM1\n+#define CONFIG_SYS_CS0_FTIM2\t\tCONFIG_SYS_NOR_FTIM2\n+#define CONFIG_SYS_CS0_FTIM3\t\tCONFIG_SYS_NOR_FTIM3\n+#endif\n+\n+\n+#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000\n+\n+/*\n+ * I2C bus multiplexer\n+ */\n+#define I2C_MUX_PCA_ADDR_PRI\t\t0x77\n+#define I2C_MUX_PCA_ADDR_SEC\t\t0x76 /* Secondary multiplexer */\n+#define I2C_RETIMER_ADDR\t\t0x18\n+#define I2C_MUX_CH_DEFAULT\t\t0x8\n+#define I2C_MUX_CH5\t\t\t0xD\n+/*\n+* RTC configuration\n+*/\n+#define RTC\n+#define CONFIG_RTC_PCF8563 1\n+#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/\n+#define CONFIG_CMD_DATE\n+\n+/* EEPROM */\n+#define CONFIG_ID_EEPROM\n+#define CONFIG_SYS_I2C_EEPROM_NXID\n+#define CONFIG_SYS_EEPROM_BUS_NUM\t\t0\n+#define CONFIG_SYS_I2C_EEPROM_ADDR\t\t0x57\n+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN\t\t1\n+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS\t3\n+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS\t5\n+\n+/* QSPI device */\n+#if defined(CONFIG_QSPI_BOOT)\n+#define CONFIG_FSL_QSPI\n+#define CONFIG_SPI_FLASH_SPANSION\n+#define FSL_QSPI_FLASH_SIZE\t\t(1 << 26)\n+#define FSL_QSPI_FLASH_NUM\t\t2\n+#endif\n+\n+#define CONFIG_CMD_MEMINFO\n+#define CONFIG_CMD_MEMTEST\n+#define CONFIG_SYS_MEMTEST_START\t0x80000000\n+#define CONFIG_SYS_MEMTEST_END\t\t0x9fffffff\n+\n+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE\n+\n+#define CONFIG_FSL_MEMAC\n+\n+/* Initial environment variables */\n+#if defined(CONFIG_QSPI_BOOT)\n+#undef CONFIG_EXTRA_ENV_SETTINGS\n+#define CONFIG_EXTRA_ENV_SETTINGS\t\t\\\n+\t\"hwconfig=fsl_ddr:bank_intlv=auto\\0\"\t\\\n+\t\"loadaddr=0x90100000\\0\"\t\t\t\\\n+\t\"kernel_addr=0x100000\\0\"\t\t\\\n+\t\"ramdisk_addr=0x800000\\0\"\t\t\\\n+\t\"ramdisk_size=0x2000000\\0\"\t\t\\\n+\t\"fdt_high=0xa0000000\\0\"\t\t\t\\\n+\t\"initrd_high=0xffffffffffffffff\\0\"\t\\\n+\t\"kernel_start=0x1000000\\0\"\t\t\\\n+\t\"kernel_load=0xa0000000\\0\"\t\t\\\n+\t\"kernel_size=0x2800000\\0\"\t\t\\\n+\t\"mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;\"\t\\\n+\t\"sf read 0x80100000 0xE00000 0x100000;\" \\\n+\t\"fsl_mc start mc 0x80000000 0x80100000\\0\"\t\\\n+\t\"mcmemsize=0x70000000 \\0\"\n+\n+#endif\n+\n+/* MAC/PHY configuration */\n+#ifdef CONFIG_FSL_MC_ENET\n+#define CONFIG_PHYLIB_10G\n+#define CONFIG_PHY_GIGE\n+#define CONFIG_PHYLIB\n+\n+#define CONFIG_PHY_VITESSE\n+#define CONFIG_PHY_AQUANTIA\n+#define AQ_PHY_ADDR1\t\t\t0x00\n+#define AQR105_IRQ_MASK\t\t\t0x00000004\n+\n+#define QSGMII1_PORT1_PHY_ADDR\t\t0x0c\n+#define QSGMII1_PORT2_PHY_ADDR\t\t0x0d\n+#define QSGMII1_PORT3_PHY_ADDR\t\t0x0e\n+#define QSGMII1_PORT4_PHY_ADDR\t\t0x0f\n+#define QSGMII2_PORT1_PHY_ADDR\t\t0x1c\n+#define QSGMII2_PORT2_PHY_ADDR\t\t0x1d\n+#define QSGMII2_PORT3_PHY_ADDR\t\t0x1e\n+#define QSGMII2_PORT4_PHY_ADDR\t\t0x1f\n+\n+#define CONFIG_MII\n+#define CONFIG_ETHPRIME\t\t\"DPMAC1@xgmii\"\n+#define CONFIG_PHY_GIGE\n+#endif\n+\n+/* MMC */\n+#ifdef CONFIG_MMC\n+#define CONFIG_FSL_ESDHC\n+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33\n+#endif\n+\n+#undef CONFIG_CMDLINE_EDITING\n+#include \n+\n+#define BOOT_TARGET_DEVICES(func) \\\n+\tfunc(USB, usb, 0) \\\n+\tfunc(MMC, mmc, 0) \\\n+\tfunc(SCSI, scsi, 0) \\\n+\tfunc(DHCP, dhcp, na)\n+#include \n+\n+#include \n+\n+#endif /* __LS1088A_RDB_H */\n","prefixes":["U-Boot","v5","2/3"]}