{"id":808126,"url":"http://patchwork.ozlabs.org/api/patches/808126/?format=json","web_url":"http://patchwork.ozlabs.org/project/skiboot/patch/1504168018-30755-1-git-send-email-shilpa.bhat@linux.vnet.ibm.com/","project":{"id":44,"url":"http://patchwork.ozlabs.org/api/projects/44/?format=json","name":"skiboot firmware development","link_name":"skiboot","list_id":"skiboot.lists.ozlabs.org","list_email":"skiboot@lists.ozlabs.org","web_url":"http://github.com/open-power/skiboot","scm_url":"http://github.com/open-power/skiboot","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1504168018-30755-1-git-send-email-shilpa.bhat@linux.vnet.ibm.com>","list_archive_url":null,"date":"2017-08-31T08:26:58","name":"opal-prd: Add support for runtime OCC reset in ZZ","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"99c57aee78ea83da69dbc31786d6cb66af9115bc","submitter":{"id":64639,"url":"http://patchwork.ozlabs.org/api/people/64639/?format=json","name":"Shilpasri G Bhat","email":"shilpa.bhat@linux.vnet.ibm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/skiboot/patch/1504168018-30755-1-git-send-email-shilpa.bhat@linux.vnet.ibm.com/mbox/","series":[{"id":769,"url":"http://patchwork.ozlabs.org/api/series/769/?format=json","web_url":"http://patchwork.ozlabs.org/project/skiboot/list/?series=769","date":"2017-08-31T08:26:58","name":"opal-prd: Add support for runtime OCC reset in ZZ","version":1,"mbox":"http://patchwork.ozlabs.org/series/769/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/808126/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/808126/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","skiboot@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","skiboot@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xjb8T6Zjpz9t16\n\tfor ;\n\tThu, 31 Aug 2017 18:27:21 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xjb8T481TzDqT0\n\tfor ;\n\tThu, 31 Aug 2017 18:27:21 +1000 (AEST)","from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com\n\t[148.163.156.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xjb8L5cBjzDqGZ\n\tfor ; Thu, 31 Aug 2017 18:27:14 +1000 (AEST)","from pps.filterd (m0098404.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv7V8QHvJ088271\n\tfor ; Thu, 31 Aug 2017 04:27:11 -0400","from e23smtp02.au.ibm.com (e23smtp02.au.ibm.com [202.81.31.144])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2cpedxshrj-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor ; Thu, 31 Aug 2017 04:27:11 -0400","from localhost\n\tby e23smtp02.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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Violators will be prosecuted; \n\tThu, 31 Aug 2017 18:27:07 +1000","from d23av03.au.ibm.com (d23av03.au.ibm.com [9.190.234.97])\n\tby d23relay06.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id\n\tv7V8R74733947790\n\tfor ; Thu, 31 Aug 2017 18:27:07 +1000","from d23av03.au.ibm.com (localhost [127.0.0.1])\n\tby d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id\n\tv7V8Qw5V014882\n\tfor ; Thu, 31 Aug 2017 18:26:59 +1000","from oc4502181600.ibm.com ([9.79.188.191])\n\tby d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id\n\tv7V8Qsx9014809; Thu, 31 Aug 2017 18:26:56 +1000"],"From":"Shilpasri G Bhat ","To":"skiboot@lists.ozlabs.org","Date":"Thu, 31 Aug 2017 13:56:58 +0530","X-Mailer":"git-send-email 1.8.3.1","X-TM-AS-MML":"disable","x-cbid":"17083108-0004-0000-0000-0000022BBD17","X-IBM-AV-DETECTION":"SAVI=unused REMOTE=unused XFE=unused","x-cbparentid":"17083108-0005-0000-0000-00005E12C548","Message-Id":"<1504168018-30755-1-git-send-email-shilpa.bhat@linux.vnet.ibm.com>","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-08-31_02:, , signatures=0","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=1\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1708310126","Subject":"[Skiboot] [PATCH] opal-prd: Add support for runtime OCC reset in ZZ","X-BeenThere":"skiboot@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Mailing list for skiboot development ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"ego@linux.vnet.ibm.com","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"Skiboot\"\n\t"},"content":"This patch handles OCC_RESET runtime events in host opal-prd and also\nprovides support for calling 'hostinterface->wakeup()' which is\nrequired for doing the reset operation.\n\nSigned-off-by: Shilpasri G Bhat \n---\n- This is based on top of\n https://lists.ozlabs.org/pipermail/skiboot/2017-August/008585.html\n which handles special wakeup in P9.\n\n core/hostservices.c | 28 +++++++++++++++--------\n external/opal-prd/opal-prd.c | 51 +++++++++++++++++++++++++++++++++++++++++-\n external/opal-prd/thunk.S | 2 +-\n hw/occ.c | 53 +++++++++++++++++++++++++++++++++++++++++++-\n hw/prd.c | 8 +++++++\n include/opal-api.h | 10 +++++++++\n include/skiboot.h | 2 ++\n 7 files changed, 142 insertions(+), 12 deletions(-)","diff":"diff --git a/core/hostservices.c b/core/hostservices.c\nindex 345c8c0..799b483 100644\n--- a/core/hostservices.c\n+++ b/core/hostservices.c\n@@ -721,17 +721,23 @@ static int hservice_wakeup(uint32_t i_core, uint32_t i_mode)\n \tstruct cpu_thread *cpu;\n \tint rc = OPAL_SUCCESS;\n \n-\t/*\n-\t * Mask out the top nibble of i_core since it may contain\n-\t * 0x4 (which we use for XSCOM targeting)\n-\t */\n-\ti_core &= 0x0fffffff;\n+\tswitch (proc_gen) {\n+\tcase proc_gen_p8:\n+\t\ti_core &= SPR_PIR_P8_MASK;\n+\t\ti_core <<= 3;\n+\t\tbreak;\n+\tcase proc_gen_p9:\n+\t\ti_core &= SPR_PIR_P9_MASK;\n+\t\ti_core <<= 2;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn OPAL_UNSUPPORTED;\n+\t}\n \n \t/* What do we need to do ? */\n \tswitch(i_mode) {\n \tcase 0: /* Assert special wakeup */\n-\t\t/* XXX Assume P8 */\n-\t\tcpu = find_cpu_by_pir(i_core << 3);\n+\t\tcpu = find_cpu_by_pir(i_core);\n \t\tif (!cpu)\n \t\t\treturn OPAL_PARAMETER;\n \t\tprlog(PR_DEBUG, \"HBRT: Special wakeup assert for core 0x%x,\"\n@@ -742,8 +748,7 @@ static int hservice_wakeup(uint32_t i_core, uint32_t i_mode)\n \t\t\tcpu->hbrt_spec_wakeup++;\n \t\treturn rc;\n \tcase 1: /* Deassert special wakeup */\n-\t\t/* XXX Assume P8 */\n-\t\tcpu = find_cpu_by_pir(i_core << 3);\n+\t\tcpu = find_cpu_by_pir(i_core);\n \t\tif (!cpu)\n \t\t\treturn OPAL_PARAMETER;\n \t\tprlog(PR_DEBUG, \"HBRT: Special wakeup release for core\"\n@@ -774,6 +779,11 @@ static int hservice_wakeup(uint32_t i_core, uint32_t i_mode)\n \t}\n }\n \n+int core_special_wakeup(u32 core, u32 mode)\n+{\n+\treturn hservice_wakeup(core, mode);\n+}\n+\n static struct host_interfaces hinterface = {\n \t.interface_version = HOSTBOOT_RUNTIME_INTERFACE_VERSION,\n \t.puts = hservice_puts,\ndiff --git a/external/opal-prd/opal-prd.c b/external/opal-prd/opal-prd.c\nindex a09a636..614b4b1 100644\n--- a/external/opal-prd/opal-prd.c\n+++ b/external/opal-prd/opal-prd.c\n@@ -506,6 +506,25 @@ int hservice_i2c_write(uint64_t i_master, uint16_t i_devAddr,\n \t\t\t i_offset, i_length, i_data);\n }\n \n+int hservice_wakeup(u32 core, u32 mode)\n+{\n+\tint rc;\n+\tstruct opal_prd_msg msg;\n+\n+\tmsg.hdr.type = OPAL_PRD_MSG_TYPE_CORE_SPECIAL_WAKEUP;\n+\tmsg.hdr.size = htobe16(sizeof(msg));\n+\tmsg.spl_wakeup.core = htobe32(core);\n+\tmsg.spl_wakeup.mode = htobe32(mode);\n+\n+\trc = write(ctx->fd, &msg, sizeof(msg));\n+\tif (rc != sizeof(msg)) {\n+\t\tpr_log(LOG_ERR, \"FW: failed for core %x : %m\\n\", core);\n+\t\treturn rc;\n+\t}\n+\n+\treturn 0;\n+}\n+\n static void ipmi_init(struct opal_prd_ctx *ctx)\n {\n \tinsert_module(\"ipmi_devintf\");\n@@ -1353,9 +1372,24 @@ static int pm_complex_reset(uint64_t chip)\n \treturn rc;\n }\n \n+static bool is_fsp(void)\n+{\n+\tchar *path;\n+\tint rc;\n+\n+\trc = asprintf(&path, \"%s/fsps\", devicetree_base);\n+\tif (rc < 0) {\n+\t\tpr_log(LOG_ERR, \"PRD: error creating '/fsps' path %m\");\n+\t\treturn false;\n+\t}\n+\n+\treturn access(path, F_OK) ? false : true;\n+}\n+\n static int handle_msg_occ_reset(struct opal_prd_ctx *ctx,\n \t\tstruct opal_prd_msg *msg)\n {\n+\tstruct opal_prd_msg omsg;\n \tuint32_t proc;\n \tint rc;\n \n@@ -1365,7 +1399,22 @@ static int handle_msg_occ_reset(struct opal_prd_ctx *ctx,\n \n \trc = pm_complex_reset(proc);\n \n-\treturn rc;\n+\tif (!is_fsp())\n+\t\treturn rc;\n+\n+\t/* Send only for zz */\n+\tomsg.hdr.type = OPAL_PRD_MSG_TYPE_OCC_RESET_STATUS;\n+\tomsg.hdr.size = htobe16(sizeof(omsg));\n+\tomsg.occ_reset_status.chip = htobe64(proc);\n+\tomsg.occ_reset_status.status = htobe64(rc);\n+\n+\trc = write(ctx->fd, &omsg, sizeof(omsg));\n+\tif (rc != sizeof(omsg)) {\n+\t\tpr_log(LOG_ERR, \"FW: Failed to send OCC_RESET status message: %m\");\n+\t\treturn rc;\n+\t}\n+\n+\treturn 0;\n }\n \n static int handle_msg_firmware_notify(struct opal_prd_ctx *ctx,\ndiff --git a/external/opal-prd/thunk.S b/external/opal-prd/thunk.S\nindex cca5890..ee3d7c3 100644\n--- a/external/opal-prd/thunk.S\n+++ b/external/opal-prd/thunk.S\n@@ -183,7 +183,7 @@ hinterface:\n \tDISABLED_THUNK(hservice_lid_load)\n \tDISABLED_THUNK(hservice_lid_unload)\n \tCALLBACK_THUNK(hservice_get_reserved_mem)\n-\tDISABLED_THUNK(hservice_wakeup)\n+\tCALLBACK_THUNK(hservice_wakeup)\n \tCALLBACK_THUNK(hservice_nanosleep)\n \tDISABLED_THUNK(hservice_report_occ_failure)\n \tCALLBACK_THUNK(hservice_clock_gettime)\ndiff --git a/hw/occ.c b/hw/occ.c\nindex 78c6a6a..a53ac92 100644\n--- a/hw/occ.c\n+++ b/hw/occ.c\n@@ -1837,6 +1837,46 @@ out:\n \treturn rc;\n }\n \n+u32 last_seq_id;\n+\n+int fsp_occ_reset_status(u64 chipid, s64 status)\n+{\n+\tstruct fsp_msg *stat;\n+\tint rc = OPAL_NO_MEM;\n+\n+\tif (status == 0) {\n+\t\tstat = fsp_mkmsg(FSP_CMD_RESET_OCC_STAT, 2, 0, last_seq_id);\n+\t\tif (!stat)\n+\t\t\treturn rc;\n+\n+\t\trc = fsp_queue_msg(stat, fsp_freemsg);\n+\t\tif (rc) {\n+\t\t\tfsp_freemsg(stat);\n+\t\t\tlog_simple_error(&e_info(OPAL_RC_OCC_RESET),\n+\t\t\t\t\"OCC: Error %d queueing FSP OCC RESET STATUS message\\n\",\n+\t\t\t\trc);\n+\t\t}\n+\t} else {\n+\t\tstruct proc_chip *chip = get_chip(chipid);\n+\n+\t\tif (!chip)\n+\t\t\treturn OPAL_PARAMETER;\n+\n+\t\tstat = fsp_mkmsg(FSP_CMD_RESET_OCC_STAT, 2,\n+\t\t\t\t 0xfe00 | (chip->pcid & 0xff), last_seq_id);\n+\t\tif (!stat)\n+\t\t\treturn rc;\n+\t\trc = fsp_queue_msg(stat, fsp_freemsg);\n+\t\tif (rc) {\n+\t\t\tfsp_freemsg(stat);\n+\t\t\tlog_simple_error(&e_info(OPAL_RC_OCC_RESET),\n+\t\t\t \"OCC: Error %d queueing FSP OCC RESET STATUS message\\n\",\n+\t\t\t\trc);\n+\t\t}\n+\t}\n+\treturn rc;\n+}\n+\n static void occ_do_reset(u8 scope, u32 dbob_id, u32 seq_id)\n {\n \tstruct fsp_msg *rsp, *stat;\n@@ -1877,7 +1917,18 @@ static void occ_do_reset(u8 scope, u32 dbob_id, u32 seq_id)\n \t * FSP will request OCC to left in stopped state.\n \t */\n \n-\trc = host_services_occ_stop();\n+\tswitch (proc_gen) {\n+\tcase proc_gen_p8:\n+\t\trc = host_services_occ_stop();\n+\t\tbreak;\n+\tcase proc_gen_p9:\n+\t\tlast_seq_id = seq_id;\n+\t\tfor_each_chip(chip)\n+\t\t\tprd_occ_reset(chip->id);\n+\t\treturn;\n+\tdefault:\n+\t\treturn;\n+\t}\n \n \t/* Handle fallback to preload */\n \tif (rc == -ENOENT && chip->homer_base) {\ndiff --git a/hw/prd.c b/hw/prd.c\nindex d076c19..dcda9c8 100644\n--- a/hw/prd.c\n+++ b/hw/prd.c\n@@ -418,6 +418,14 @@ static int64_t opal_prd_msg(struct opal_prd_msg *msg)\n \tcase OPAL_PRD_MSG_TYPE_FIRMWARE_REQUEST:\n \t\trc = prd_msg_handle_firmware_req(msg);\n \t\tbreak;\n+\tcase OPAL_PRD_MSG_TYPE_OCC_RESET_STATUS:\n+\t\trc = fsp_occ_reset_status(msg->occ_reset_status.chip,\n+\t\t\t\t\t msg->occ_reset_status.status);\n+\t\tbreak;\n+\tcase OPAL_PRD_MSG_TYPE_CORE_SPECIAL_WAKEUP:\n+\t\trc = core_special_wakeup(msg->spl_wakeup.core,\n+\t\t\t\t\t msg->spl_wakeup.mode);\n+\t\tbreak;\n \tdefault:\n \t\trc = OPAL_UNSUPPORTED;\n \t}\ndiff --git a/include/opal-api.h b/include/opal-api.h\nindex 0ff0db0..2f303f9 100644\n--- a/include/opal-api.h\n+++ b/include/opal-api.h\n@@ -1052,6 +1052,8 @@ enum opal_prd_msg_type {\n \tOPAL_PRD_MSG_TYPE_FIRMWARE_RESPONSE, /* HBRT <-- OPAL */\n \tOPAL_PRD_MSG_TYPE_FIRMWARE_NOTIFY, /* HBRT <-- OPAL */\n \tOPAL_PRD_MSG_TYPE_SBE_PASSTHROUGH, /* HBRT <-- OPAL */\n+\tOPAL_PRD_MSG_TYPE_OCC_RESET_STATUS, /* HBRT --> OPAL */\n+\tOPAL_PRD_MSG_TYPE_CORE_SPECIAL_WAKEUP, /* HBRT --> OPAL */\n };\n \n struct opal_prd_msg_header {\n@@ -1099,6 +1101,14 @@ struct opal_prd_msg {\n \t\tstruct {\n \t\t\t__be64\tchip;\n \t\t} sbe_passthrough;\n+\t\tstruct {\n+\t\t\t__be64 chip;\n+\t\t\t__be64 status; /* 0 SUCCESS */\n+\t\t} occ_reset_status;\n+\t\tstruct {\n+\t\t\t__be32 core;\n+\t\t\t__be32 mode;\n+\t\t} spl_wakeup;\n \t};\n };\n \ndiff --git a/include/skiboot.h b/include/skiboot.h\nindex 4b7d519..5eb9188 100644\n--- a/include/skiboot.h\n+++ b/include/skiboot.h\n@@ -317,4 +317,6 @@ extern int occ_sensor_group_clear(u32 group_hndl, int token);\n extern void occ_add_sensor_groups(struct dt_node *sg, u32 *phandles,\n \t\t\t\t int nr_phandles, int chipid);\n \n+extern int fsp_occ_reset_status(u64 chipid, s64 status);\n+extern int core_special_wakeup(u32 core, u32 mode);\n #endif /* __SKIBOOT_H */\n","prefixes":[]}