{"id":806104,"url":"http://patchwork.ozlabs.org/api/patches/806104/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1503737883-14236-3-git-send-email-yamada.masahiro@socionext.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1503737883-14236-3-git-send-email-yamada.masahiro@socionext.com>","list_archive_url":null,"date":"2017-08-26T08:57:59","name":"[U-Boot,2/6] ARM: uniphier: move PLLCTRL register macros to each SoC .c file","commit_ref":"a55957b9ad0b912b9e0f705ed64e42274be05276","pull_url":null,"state":"accepted","archived":false,"hash":"784491b88dbe642faa6f77523bcad4c8ba7c5eab","submitter":{"id":65882,"url":"http://patchwork.ozlabs.org/api/people/65882/?format=json","name":"Masahiro Yamada","email":"yamada.masahiro@socionext.com"},"delegate":{"id":38701,"url":"http://patchwork.ozlabs.org/api/users/38701/?format=json","username":"masahir0y","first_name":"Masahiro","last_name":"Yamada","email":"yamada.m@jp.panasonic.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1503737883-14236-3-git-send-email-yamada.masahiro@socionext.com/mbox/","series":[],"comments":"http://patchwork.ozlabs.org/api/patches/806104/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/806104/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=nifty.com header.i=@nifty.com\n\theader.b=\"hGoiAghh\"; dkim-atps=neutral"],"Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xfX6K5zqDz9t3D\n\tfor ;\n\tSat, 26 Aug 2017 18:59:53 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 86F3DC2206F; Sat, 26 Aug 2017 08:59:28 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 92836C2208B;\n\tSat, 26 Aug 2017 08:58:39 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 66618C2206E; Sat, 26 Aug 2017 08:58:35 +0000 (UTC)","from conuserg-09.nifty.com (conuserg-09.nifty.com [210.131.2.76])\n\tby lists.denx.de (Postfix) with ESMTPS id 126D1C2206E\n\tfor ; Sat, 26 Aug 2017 08:58:33 +0000 (UTC)","from grover.sesame (FL1-122-131-185-176.osk.mesh.ad.jp\n\t[122.131.185.176]) (authenticated)\n\tby conuserg-09.nifty.com with ESMTP id v7Q8wANN031195;\n\tSat, 26 Aug 2017 17:58:12 +0900"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.0 required=5.0 tests=T_DKIM_INVALID\n\tautolearn=unavailable autolearn_force=no version=3.4.0","DKIM-Filter":"OpenDKIM Filter v2.10.3 conuserg-09.nifty.com v7Q8wANN031195","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com;\n\ts=dec2015msa; t=1503737892;\n\tbh=jVQtLSyRP5VoMUpJMBHGG+4wNWFvtYcPEMqT3mvFDs8=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=hGoiAghheBFVdY66JoJx0k95/E9k4RRl3/G8YYaQ/7vDRU/A06o+VHR1FGvW01zjk\n\tT5iumJFskz6cU7Ttr8i3WPHGC4n4JMIY2/x0kfSvHvbFZXueckBYXgJI8G0LXWAZVo\n\tco358xph8/6oOyF8HMid4TpjQQwknPb+CPZ/br6n/5b5GUCrj98NxeXQ9gAyY5a06X\n\tXKGUE53MVY7cffyPJQofYuWBCpPqTxux/2IhIaf+X0ihuKsb8BG+yp+HL1hEyU2z2o\n\tLBneBTpYvZw2ObLWs0uktn+O4nBhtAGFUElOjQrTpyh4XuUOtNKibf0sIA6v/o6RBr\n\tgzPQGaGD9kExQ==","X-Nifty-SrcIP":"[122.131.185.176]","From":"Masahiro Yamada ","To":"u-boot@lists.denx.de","Date":"Sat, 26 Aug 2017 17:57:59 +0900","Message-Id":"<1503737883-14236-3-git-send-email-yamada.masahiro@socionext.com>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1503737883-14236-1-git-send-email-yamada.masahiro@socionext.com>","References":"<1503737883-14236-1-git-send-email-yamada.masahiro@socionext.com>","Cc":"Albert Aribaud ","Subject":"[U-Boot] [PATCH 2/6] ARM: uniphier: move PLLCTRL register macros to\n\teach SoC .c file","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"The new SoC PXs3 changed the address of PLL, but still uses the\nsame PLL name. We can not define SC_*PLLCTRL in the common header.\nMove them to per-SoC .c file. Also, fix some PLL comments.\n\nSigned-off-by: Masahiro Yamada \n---\n\n arch/arm/mach-uniphier/clk/pll-ld11.c | 11 +++++++++++\n arch/arm/mach-uniphier/clk/pll-ld20.c | 19 +++++++++++++++++++\n arch/arm/mach-uniphier/sc64-regs.h | 21 ---------------------\n 3 files changed, 30 insertions(+), 21 deletions(-)","diff":"diff --git a/arch/arm/mach-uniphier/clk/pll-ld11.c b/arch/arm/mach-uniphier/clk/pll-ld11.c\nindex b4a97d21610f..1a7ec2952524 100644\n--- a/arch/arm/mach-uniphier/clk/pll-ld11.c\n+++ b/arch/arm/mach-uniphier/clk/pll-ld11.c\n@@ -11,6 +11,17 @@\n #include \"../sc64-regs.h\"\n #include \"pll.h\"\n \n+/* PLL type: SSC */\n+#define SC_CPLLCTRL\t(SC_BASE_ADDR | 0x1400)\t/* CPU/ARM */\n+#define SC_SPLLCTRL\t(SC_BASE_ADDR | 0x1410)\t/* misc */\n+#define SC_MPLLCTRL\t(SC_BASE_ADDR | 0x1430)\t/* DSP */\n+#define SC_VSPLLCTRL\t(SC_BASE_ADDR | 0x1440)\t/* Video codec, VPE etc. */\n+#define SC_DPLLCTRL\t(SC_BASE_ADDR | 0x1460)\t/* DDR memory */\n+\n+/* PLL type: VPLL27 */\n+#define SC_VPLL27FCTRL\t(SC_BASE_ADDR | 0x1500)\n+#define SC_VPLL27ACTRL\t(SC_BASE_ADDR | 0x1520)\n+\n void uniphier_ld11_pll_init(void)\n {\n \tuniphier_ld20_sscpll_init(SC_CPLLCTRL, 1960, 1, 2);\t/* 2000MHz -> 1960MHz */\ndiff --git a/arch/arm/mach-uniphier/clk/pll-ld20.c b/arch/arm/mach-uniphier/clk/pll-ld20.c\nindex 50b91598d64d..5e072c6dff77 100644\n--- a/arch/arm/mach-uniphier/clk/pll-ld20.c\n+++ b/arch/arm/mach-uniphier/clk/pll-ld20.c\n@@ -11,6 +11,25 @@\n #include \"../sc64-regs.h\"\n #include \"pll.h\"\n \n+/* PLL type: SSC */\n+#define SC_CPLLCTRL\t(SC_BASE_ADDR | 0x1400)\t/* CPU/ARM */\n+#define SC_SPLLCTRL\t(SC_BASE_ADDR | 0x1410)\t/* misc */\n+#define SC_SPLL2CTRL\t(SC_BASE_ADDR | 0x1420)\t/* DSP */\n+#define SC_MPLLCTRL\t(SC_BASE_ADDR | 0x1430)\t/* Video codec */\n+#define SC_VPPLLCTRL\t(SC_BASE_ADDR | 0x1440)\t/* VPE etc. */\n+#define SC_GPPLLCTRL\t(SC_BASE_ADDR | 0x1450)\t/* GPU/Mali */\n+#define SC_DPLL0CTRL\t(SC_BASE_ADDR | 0x1460)\t/* DDR memory 0 */\n+#define SC_DPLL1CTRL\t(SC_BASE_ADDR | 0x1470)\t/* DDR memory 1 */\n+#define SC_DPLL2CTRL\t(SC_BASE_ADDR | 0x1480)\t/* DDR memory 2 */\n+\n+/* PLL type: VPLL27 */\n+#define SC_VPLL27FCTRL\t(SC_BASE_ADDR | 0x1500)\n+#define SC_VPLL27ACTRL\t(SC_BASE_ADDR | 0x1520)\n+\n+/* PLL type: DSPLL */\n+#define SC_VPLL8KCTRL\t(SC_BASE_ADDR | 0x1540)\n+#define SC_A2PLLCTRL\t(SC_BASE_ADDR | 0x15C0)\n+\n void uniphier_ld20_pll_init(void)\n {\n \tuniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);\ndiff --git a/arch/arm/mach-uniphier/sc64-regs.h b/arch/arm/mach-uniphier/sc64-regs.h\nindex d3aa18530d97..d0a51f239c38 100644\n--- a/arch/arm/mach-uniphier/sc64-regs.h\n+++ b/arch/arm/mach-uniphier/sc64-regs.h\n@@ -12,27 +12,6 @@\n \n #define SC_BASE_ADDR\t\t0x61840000\n \n-/* PLL type: SSC */\n-#define SC_CPLLCTRL\t(SC_BASE_ADDR | 0x1400)\t/* LD11/20: CPU/ARM */\n-#define SC_SPLLCTRL\t(SC_BASE_ADDR | 0x1410)\t/* LD11/20: misc */\n-#define SC_SPLL2CTRL\t(SC_BASE_ADDR | 0x1420)\t/* LD20: IPP */\n-#define SC_MPLLCTRL\t(SC_BASE_ADDR | 0x1430)\t/* LD11/20: Video codec */\n-#define SC_VSPLLCTRL\t(SC_BASE_ADDR | 0x1440)\t/* LD11 */\n-#define SC_VPPLLCTRL\t(SC_BASE_ADDR | 0x1440)\t/* LD20: VPE etc. */\n-#define SC_GPPLLCTRL\t(SC_BASE_ADDR | 0x1450)\t/* LD20: GPU/Mali */\n-#define SC_DPLLCTRL\t(SC_BASE_ADDR | 0x1460)\t/* LD11: DDR memory */\n-#define SC_DPLL0CTRL\t(SC_BASE_ADDR | 0x1460)\t/* LD20: DDR memory 0 */\n-#define SC_DPLL1CTRL\t(SC_BASE_ADDR | 0x1470)\t/* LD20: DDR memory 1 */\n-#define SC_DPLL2CTRL\t(SC_BASE_ADDR | 0x1480)\t/* LD20: DDR memory 2 */\n-\n-/* PLL type: VPLL27 */\n-#define SC_VPLL27FCTRL\t(SC_BASE_ADDR | 0x1500)\n-#define SC_VPLL27ACTRL\t(SC_BASE_ADDR | 0x1520)\n-\n-/* PLL type: DSPLL */\n-#define SC_VPLL8KCTRL\t(SC_BASE_ADDR | 0x1540)\n-#define SC_A2PLLCTRL\t(SC_BASE_ADDR | 0x15C0)\n-\n #define SC_RSTCTRL\t\t(SC_BASE_ADDR | 0x2000)\n #define SC_RSTCTRL3\t\t(SC_BASE_ADDR | 0x2008)\n #define SC_RSTCTRL4\t\t(SC_BASE_ADDR | 0x200c)\n","prefixes":["U-Boot","2/6"]}