{"id":805089,"url":"http://patchwork.ozlabs.org/api/patches/805089/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1503504610-12880-3-git-send-email-aisheng.dong@nxp.com/","project":{"id":37,"url":"http://patchwork.ozlabs.org/api/projects/37/?format=json","name":"Devicetree Bindings","link_name":"devicetree-bindings","list_id":"devicetree.vger.kernel.org","list_email":"devicetree@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1503504610-12880-3-git-send-email-aisheng.dong@nxp.com>","list_archive_url":null,"date":"2017-08-23T16:10:05","name":"[2/7] dt-bindings: PM / OPP: add clocks per OPP node support","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":true,"hash":"fd4ec92127ae346d771ed826f9eab85f530fddc1","submitter":{"id":71420,"url":"http://patchwork.ozlabs.org/api/people/71420/?format=json","name":"Aisheng Dong","email":"aisheng.dong@nxp.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1503504610-12880-3-git-send-email-aisheng.dong@nxp.com/mbox/","series":[],"comments":"http://patchwork.ozlabs.org/api/patches/805089/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/805089/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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helo=tx30smr01.am.freescale.net;","From":"Dong Aisheng ","To":"","CC":",\n\t, ,\n\t, , ,\n\t, , ,\n\tDong Aisheng , Rob Herring ,\n\tFrank Rowand , ","Subject":"[PATCH 2/7] dt-bindings: PM / OPP: add clocks per OPP node support","Date":"Thu, 24 Aug 2017 00:10:05 +0800","Message-ID":"<1503504610-12880-3-git-send-email-aisheng.dong@nxp.com>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1503504610-12880-1-git-send-email-aisheng.dong@nxp.com>","References":"<1503504610-12880-1-git-send-email-aisheng.dong@nxp.com>","X-EOPAttributedMessage":"0","X-Matching-Connectors":"131479782237307310;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); ()","X-Forefront-Antispam-Report":"CIP:192.88.168.50; IPV:NLI; CTRY:US; EFV:NLI;\n\tSFV:NSPM;\n\tSFS:(10009020)(6009001)(336005)(39860400002)(39380400002)(2980300002)(1110001)(1109001)(339900001)(189002)(199003)(97736004)(50466002)(48376002)(2351001)(33646002)(356003)(68736007)(7416002)(5003940100001)(305945005)(6916009)(36756003)(106466001)(54906002)(4326008)(105606002)(189998001)(2906002)(77096006)(110136004)(53936002)(50986999)(39060400002)(76176999)(81166006)(47776003)(8676002)(626005)(6666003)(50226002)(8656003)(8936002)(498600001)(104016004)(85426001)(5660300001)(2950100002)(86362001)(81156014);\n\tDIR:OUT; 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BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(400006)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:CO2PR03MB2261; ","X-Forefront-PRVS":"040866B734","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"23 Aug 2017 16:10:23.5123\n\t(UTC)","X-MS-Exchange-CrossTenant-Id":"5afe0b00-7697-4969-b663-5eab37d5f47e","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"CO2PR03MB2261","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"},"content":"It's used for platforms where different OPPs may use different clocks.\nWith this extended binding, user could specify the correct clock for each\nOPP node.\n\nCc: Viresh Kumar \nCc: Nishanth Menon \nCc: Stephen Boyd \nCc: \"Rafael J. Wysocki\" \nCc: Rob Herring \nCc: Frank Rowand \nCc: devicetree@vger.kernel.org\nSigned-off-by: Dong Aisheng \n---\n Documentation/devicetree/bindings/opp/opp.txt | 52 +++++++++++++++++++++++++++\n 1 file changed, 52 insertions(+)","diff":"diff --git a/Documentation/devicetree/bindings/opp/opp.txt b/Documentation/devicetree/bindings/opp/opp.txt\nindex e36d261..40a4340 100644\n--- a/Documentation/devicetree/bindings/opp/opp.txt\n+++ b/Documentation/devicetree/bindings/opp/opp.txt\n@@ -152,6 +152,11 @@ Optional properties:\n hierarchy can be contained in multiple 32 bit values. i.e. in the\n above example, Z1 & Z2 refer to the version hierarchy Z.\n \n+- clocks: Clock phandle and specifier used for this opp.\n+\n+- clock-names: clock names for this opp. The valid clock names are platform\n+\t specific.\n+\n - status: Marks the node enabled/disabled.\n \n Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states together.\n@@ -528,3 +533,50 @@ Example 6: opp-microvolt-, opp-microamp-:\n \t\t};\n \t};\n };\n+\n+Example 7: Single core ARM cortex A7, switch separate clocks for each OPP:\n+\n+/ {\n+\tcpus {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tcpu@0 {\n+\t\t\tcompatible = \"arm,cortex-a7\";\n+\t\t\treg = <0>;\n+\t\t\tnext-level-cache = <&L2>;\n+\t\t\tclocks = <&clk_controller 0>;\n+\t\t\tclock-names = \"cpu\";\n+\t\t\tcpu-supply = <&cpu_supply0>;\n+\t\t\toperating-points-v2 = <&cpu0_opp_table>;\n+\t\t};\n+\t};\n+\n+\tcpu0_opp_table: opp_table0 {\n+\t\tcompatible = \"operating-points-v2\";\n+\t\topp-shared;\n+\n+\t\topp-1000000000 {\n+\t\t\topp-hz = /bits/ 64 <1000000000>;\n+\t\t\topp-microvolt = <975000 970000 985000>;\n+\t\t\topp-microamp = <70000>;\n+\t\t\tclock-latency-ns = <300000>;\n+\t\t\tclocks = <&clk_controller 0>;\n+\t\t\topp-suspend;\n+\t\t};\n+\t\topp-1100000000 {\n+\t\t\topp-hz = /bits/ 64 <1100000000>;\n+\t\t\topp-microvolt = <1000000 980000 1010000>;\n+\t\t\topp-microamp = <80000>;\n+\t\t\tclocks = <&clk_controller 1>;\n+\t\t\tclock-latency-ns = <310000>;\n+\t\t};\n+\t\topp-1200000000 {\n+\t\t\topp-hz = /bits/ 64 <1200000000>;\n+\t\t\topp-microvolt = <1025000>;\n+\t\t\tclocks = <&clk_controller 2>;\n+\t\t\tclock-latency-ns = <290000>;\n+\t\t\tturbo-mode;\n+\t\t};\n+\t};\n+};\n","prefixes":["2/7"]}