{"id":804737,"url":"http://patchwork.ozlabs.org/api/patches/804737/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/1503464171-6471-3-git-send-email-okaya@codeaurora.org/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1503464171-6471-3-git-send-email-okaya@codeaurora.org>","list_archive_url":null,"date":"2017-08-23T04:56:09","name":"[V12,3/5] PCI: Factor out pci_bus_wait_crs()","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"366b915d85e9d6f844f57667da2857f3a88caa2d","submitter":{"id":67496,"url":"http://patchwork.ozlabs.org/api/people/67496/?format=json","name":"Sinan Kaya","email":"okaya@codeaurora.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/1503464171-6471-3-git-send-email-okaya@codeaurora.org/mbox/","series":[],"comments":"http://patchwork.ozlabs.org/api/patches/804737/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/804737/checks/","tags":{},"related":[],"headers":{"Return-Path":"<linux-pci-owner@vger.kernel.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"fjz7jZDm\"; \n\tdkim=pass (1024-bit key) header.d=codeaurora.org\n\theader.i=@codeaurora.org header.b=\"YUvnAnII\"; \n\tdkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none)\n\theader.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=okaya@codeaurora.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xcZsJ1Q50z9s8V\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 23 Aug 2017 14:56:52 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753309AbdHWE4V (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tWed, 23 Aug 2017 00:56:21 -0400","from smtp.codeaurora.org ([198.145.29.96]:53264 \"EHLO\n\tsmtp.codeaurora.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751436AbdHWE4U (ORCPT\n\t<rfc822; linux-pci@vger.kernel.org>); Wed, 23 Aug 2017 00:56:20 -0400","by smtp.codeaurora.org (Postfix, from userid 1000)\n\tid 857236071C; Wed, 23 Aug 2017 04:56:19 +0000 (UTC)","from drakthul.qualcomm.com (global_nat1_iad_fw.qualcomm.com\n\t[129.46.232.65])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\t(Authenticated sender: okaya@smtp.codeaurora.org)\n\tby smtp.codeaurora.org (Postfix) with ESMTPSA id 09F2C6070B;\n\tWed, 23 Aug 2017 04:56:17 +0000 (UTC)"],"DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1503464179;\n\tbh=EkSQrPrJfWIbM7IEsRU9zoEO8mN40PLlCT8rmYfe65w=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=fjz7jZDme9/dH+4JSyXV2ECHQka4ys9BFu03uoIVbNXIQXD92L/aoToPzMPknPxmT\n\tnD+CdsKHdgAeIAEWJZQzrZvynt0psv1gI1Abfb9Ybz5wByryMUi82ZIoEIqmsHcO5y\n\tMAJZLkq7iTMArkJiijT/PQblCAm5n4wYLjKwG/u8=","v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1503464178;\n\tbh=EkSQrPrJfWIbM7IEsRU9zoEO8mN40PLlCT8rmYfe65w=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=YUvnAnIIGt+zJDHBfy/ByvMJNwnApE1+Jyb6lUWFNC24FkXxiEql6fVc2zaZBfLcn\n\tOP7ChU8ky8uGuZJDo3sZ1O120sYUkMg/O0DuEol/wN1szk91kpmH4/4t5RyrynCm8B\n\taKC4dJ2pFJm68k/uaYrLG25c2y2nmNAkFd+jz3Jk="],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org","X-Spam-Level":"","X-Spam-Status":"No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DMARC-Filter":"OpenDMARC Filter v1.3.2 smtp.codeaurora.org 09F2C6070B","From":"Sinan Kaya <okaya@codeaurora.org>","To":"linux-pci@vger.kernel.org, timur@codeaurora.org,\n\talex.williamson@redhat.com","Cc":"linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tSinan Kaya <okaya@codeaurora.org>, Bjorn Helgaas <bhelgaas@google.com>,\n\tlinux-kernel@vger.kernel.org","Subject":"[PATCH V12 3/5] PCI: Factor out pci_bus_wait_crs()","Date":"Wed, 23 Aug 2017 00:56:09 -0400","Message-Id":"<1503464171-6471-3-git-send-email-okaya@codeaurora.org>","X-Mailer":"git-send-email 1.9.1","In-Reply-To":"<1503464171-6471-1-git-send-email-okaya@codeaurora.org>","References":"<1503464171-6471-1-git-send-email-okaya@codeaurora.org>","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"<linux-pci.vger.kernel.org>","X-Mailing-List":"linux-pci@vger.kernel.org"},"content":"Configuration Request Retry Status (CRS) was previously hidden inside\npci_bus_read_dev_vendor_id().  We want to add support for CRS in other\nsituations, such as waiting for a device to become ready after a Function\nLevel Reset.\n\nMove CRS handling into pci_bus_wait_crs() so it can be called from other\nplaces.\n\nSigned-off-by: Sinan Kaya <okaya@codeaurora.org>\n---\n drivers/pci/pci.h   |  1 +\n drivers/pci/probe.c | 46 ++++++++++++++++++++++++++++------------------\n 2 files changed, 29 insertions(+), 18 deletions(-)","diff":"diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h\nindex 7fa583a..56d2515 100644\n--- a/drivers/pci/pci.h\n+++ b/drivers/pci/pci.h\n@@ -239,6 +239,7 @@ static inline bool pci_bus_crs_visibility_pending(u32 l)\n {\n \treturn (l & 0xffff) == 0x0001;\n }\n+bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 l, int timeout);\n bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,\n \t\t\t\tint crs_timeout);\n int pci_setup_device(struct pci_dev *dev);\ndiff --git a/drivers/pci/probe.c b/drivers/pci/probe.c\nindex 2849e0e..93b89dd 100644\n--- a/drivers/pci/probe.c\n+++ b/drivers/pci/probe.c\n@@ -1824,30 +1824,23 @@ struct pci_dev *pci_alloc_dev(struct pci_bus *bus)\n }\n EXPORT_SYMBOL(pci_alloc_dev);\n \n-bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,\n-\t\t\t\tint crs_timeout)\n+bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 l, int timeout)\n {\n \tint delay = 1;\n \n-\tif (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))\n-\t\treturn false;\n+\tif ((l & 0xffff) != 0x0001)\n+\t\treturn true;\t/* not a CRS completion */\n \n-\t/* some broken boards return 0 or ~0 if a slot is empty: */\n-\tif (*l == 0xffffffff || *l == 0x00000000 ||\n-\t    *l == 0x0000ffff || *l == 0xffff0000)\n-\t\treturn false;\n+\tif (!timeout)\n+\t\treturn false;\t/* CRS, but caller doesn't want to wait */\n \n \t/*\n-\t * Configuration Request Retry Status.  Some root ports return the\n-\t * actual device ID instead of the synthetic ID (0xFFFF) required\n-\t * by the PCIe spec.  Ignore the device ID and only check for\n-\t * (vendor id == 1).\n+\t * We got the reserved Vendor ID that indicates a completion with\n+\t * Configuration Request Retry Status (CRS).  Retry until we get a\n+\t * valid Vendor ID or we time out.\n \t */\n-\twhile ((*l & 0xffff) == 0x0001) {\n-\t\tif (!crs_timeout)\n-\t\t\treturn false;\n-\n-\t\tif (delay > crs_timeout) {\n+\twhile ((l & 0xffff) == 0x0001) {\n+\t\tif (delay > timeout) {\n \t\t\tprintk(KERN_WARNING \"pci %04x:%02x:%02x.%d: not responding\\n\",\n \t\t\t       pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),\n \t\t\t       PCI_FUNC(devfn));\n@@ -1857,12 +1850,29 @@ bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,\n \t\tmsleep(delay);\n \t\tdelay *= 2;\n \n-\t\tif (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))\n+\t\tif (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))\n \t\t\treturn false;\n \t}\n \n \treturn true;\n }\n+\n+bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,\n+\t\t\t\tint timeout)\n+{\n+\tif (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))\n+\t\treturn false;\n+\n+\t/* some broken boards return 0 or ~0 if a slot is empty: */\n+\tif (*l == 0xffffffff || *l == 0x00000000 ||\n+\t    *l == 0x0000ffff || *l == 0xffff0000)\n+\t\treturn false;\n+\n+\tif (pci_bus_crs_visibility_pending(*l))\n+\t\treturn pci_bus_wait_crs(bus, devfn, *l, timeout);\n+\n+\treturn true;\n+}\n EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);\n \n /*\n","prefixes":["V12","3/5"]}