{"id":804550,"url":"http://patchwork.ozlabs.org/api/patches/804550/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1503417002-4307-1-git-send-email-aford173@gmail.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1503417002-4307-1-git-send-email-aford173@gmail.com>","list_archive_url":null,"date":"2017-08-22T15:50:01","name":"[U-Boot,1/2] ARM: OMAP3: am3517_evm: Move header to ti_omap3_common.h","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"1685cb1d0e4a6434448c46edce59008b8be44842","submitter":{"id":67132,"url":"http://patchwork.ozlabs.org/api/people/67132/?format=json","name":"Adam Ford","email":"aford173@gmail.com"},"delegate":{"id":3651,"url":"http://patchwork.ozlabs.org/api/users/3651/?format=json","username":"trini","first_name":"Tom","last_name":"Rini","email":"trini@ti.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1503417002-4307-1-git-send-email-aford173@gmail.com/mbox/","series":[],"comments":"http://patchwork.ozlabs.org/api/patches/804550/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/804550/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"Much of the AM3517 functions are copies of the standard definitions\nused in ti_omap3_common.h. Moving to include a common file\nreduces the amount of duplicative code and clutter. A few\nAM3517 specific functions (like EMIF4) are explictly defined\nand a few items are undefined or redefined, but overall the number\nof lines of code shink.\n\nSigned-off-by: Adam Ford \n---\n include/configs/am3517_evm.h | 48 +++++---------------------------------------\n 1 file changed, 5 insertions(+), 43 deletions(-)","diff":"diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h\nindex e957a28..9bf50e6 100644\n--- a/include/configs/am3517_evm.h\n+++ b/include/configs/am3517_evm.h\n@@ -14,7 +14,6 @@\n #define __CONFIG_H\n \n #define CONFIG_NR_DRAM_BANKS\t2\t/* CS1 may or may not be populated */\n-\n #define CONFIG_EMIF4\t/* The chip has EMIF4 controller */\n \n /*\n@@ -27,39 +26,26 @@\n #define CONFIG_SYS_SPL_MALLOC_START\t0x80208000\n #define CONFIG_SYS_SPL_MALLOC_SIZE\t0x100000\n \n-#include \t\t/* get chip and board defs */\n-#include \n+#include \n+#undef CONFIG_SDRC\t/* Disable SDRC since we have EMIF4 */\n \n #define CONFIG_MISC_INIT_R\n-#define CONFIG_CMDLINE_TAG\t\t/* enable passing of ATAGs */\n-#define CONFIG_SETUP_MEMORY_TAGS\n-#define CONFIG_INITRD_TAG\n #define CONFIG_REVISION_TAG\n \n-/* Clock Defines */\n-#define V_OSCK\t\t\t26000000\t/* Clock output from T2 */\n-#define V_SCLK\t\t\t(V_OSCK >> 1)\n-\n-/* Size of malloc() pool */\n-#define CONFIG_SYS_MALLOC_LEN\t\t(16 << 20)\n-\n /* Hardware drivers */\n \n /* NS16550 Configuration */\n-#define V_NS16550_CLK\t\t\t48000000\t/* 48MHz (APLL96/2) */\n #define CONFIG_SYS_NS16550_SERIAL\n #define CONFIG_SYS_NS16550_REG_SIZE\t(-4)\n-#define CONFIG_SYS_NS16550_CLK\t\tV_NS16550_CLK\n \n /* select serial console configuration */\n #define CONFIG_CONS_INDEX\t\t3\n #define CONFIG_SYS_NS16550_COM3\t\tOMAP34XX_UART3\n #define CONFIG_SERIAL3\t\t\t3\t/* UART3 on AM3517 EVM */\n \n+\n /* allow to overwrite serial and ethaddr */\n #define CONFIG_ENV_OVERWRITE\n-#define CONFIG_SYS_BAUDRATE_TABLE\t{4800, 9600, 19200, 38400, 57600,\\\n-\t\t\t\t\t115200}\n \n /*\n * USB configuration\n@@ -104,16 +90,10 @@\n \n /* Board NAND Info. */\n #ifdef CONFIG_NAND\n-#define CONFIG_NAND_OMAP_GPMC\n #define CONFIG_NAND_OMAP_GPMC_PREFETCH\n #define CONFIG_BCH\n #define CONFIG_SYS_NAND_ADDR\t\tNAND_BASE\t/* physical address */\n \t\t\t\t\t\t\t/* to access nand */\n-#define CONFIG_SYS_NAND_BASE\t\tNAND_BASE\t/* physical address */\n-\t\t\t\t\t\t\t/* to access */\n-\t\t\t\t\t\t\t/* nand at CS0 */\n-#define CONFIG_SYS_MAX_NAND_DEVICE\t1\t\t/* Max number of */\n-\t\t\t\t\t\t\t/* NAND devices */\n #define CONFIG_SYS_NAND_BUSWIDTH_16BIT\n #define CONFIG_SYS_NAND_5_ADDR_CYCLE\n #define CONFIG_SYS_NAND_PAGE_COUNT\t64\n@@ -233,8 +213,6 @@\n /* We set the max number of command args high to avoid HUSH bugs. */\n #define CONFIG_SYS_MAXARGS\t\t64\n \n-/* Console I/O Buffer Size */\n-#define CONFIG_SYS_CBSIZE\t\t512\n /* Print Buffer Size */\n #define CONFIG_SYS_PBSIZE\t\t(CONFIG_SYS_CBSIZE \\\n \t\t\t\t\t+ sizeof(CONFIG_SYS_PROMPT) + 16)\n@@ -246,27 +224,10 @@\n #define CONFIG_SYS_MEMTEST_END\t\t(OMAP34XX_SDRC_CS0 + \\\n \t\t\t\t\t0x01F00000) /* 31MB */\n \n-#define CONFIG_SYS_LOAD_ADDR\t\t(OMAP34XX_SDRC_CS0) /* default load */\n-\t\t\t\t\t\t\t\t/* address */\n-\n-/*\n- * AM3517 has 12 GP timers, they can be driven by the system clock\n- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).\n- * This rate is divided by a local divisor.\n- */\n-#define CONFIG_SYS_TIMERBASE\t\tOMAP34XX_GPT2\n-#define CONFIG_SYS_PTV\t\t\t2\t/* Divisor: 2^(PTV+1) => 8 */\n-\n /* Physical Memory Map */\n-#define PHYS_SDRAM_1\t\t\tOMAP34XX_SDRC_CS0\n-#define PHYS_SDRAM_2\t\t\tOMAP34XX_SDRC_CS1\n #define CONFIG_SYS_CS0_SIZE\t\t(256 * 1024 * 1024)\n-#define CONFIG_SYS_SDRAM_BASE\t\tPHYS_SDRAM_1\n #define CONFIG_SYS_INIT_RAM_ADDR\t0x4020f800\n #define CONFIG_SYS_INIT_RAM_SIZE\t0x800\n-#define CONFIG_SYS_INIT_SP_ADDR\t\t(CONFIG_SYS_INIT_RAM_ADDR + \\\n-\t\t\t\t\t CONFIG_SYS_INIT_RAM_SIZE - \\\n-\t\t\t\t\t GENERATED_GBL_DATA_SIZE)\n \n /* FLASH and environment organization */\n \n@@ -291,11 +252,12 @@\n \n /* Defines for SPL */\n #define CONFIG_SPL_FRAMEWORK\n-#define CONFIG_SPL_NAND_SIMPLE\n+#undef CONFIG_SPL_TEXT_BASE\n #define CONFIG_SPL_TEXT_BASE\t\t0x40200000\n #define CONFIG_SPL_MAX_SIZE\t\t(SRAM_SCRATCH_SPACE_ADDR - \\\n \t\t\t\t\t CONFIG_SPL_TEXT_BASE)\n \n+#undef CONFIG_SPL_BSS_START_ADDR\n #define CONFIG_SPL_BSS_START_ADDR\t0x80000000\n #define CONFIG_SPL_BSS_MAX_SIZE\t\t0x80000\t\t/* 512 KB */\n \n","prefixes":["U-Boot","1/2"]}