{"id":804325,"url":"http://patchwork.ozlabs.org/api/patches/804325/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20170822082258.5801-1-lokeshvutla@ti.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170822082258.5801-1-lokeshvutla@ti.com>","list_archive_url":null,"date":"2017-08-22T08:22:58","name":"[U-Boot] board: ti: am571x: Add 666MHz support for AM571x IDK","commit_ref":"209742fa8858a201af2f32e05b1fb72ef299540e","pull_url":null,"state":"accepted","archived":false,"hash":"a0e56b767c603e12b507b9938990ebdcea2c070c","submitter":{"id":14145,"url":"http://patchwork.ozlabs.org/api/people/14145/?format=json","name":"Lokesh Vutla","email":"lokeshvutla@ti.com"},"delegate":{"id":3651,"url":"http://patchwork.ozlabs.org/api/users/3651/?format=json","username":"trini","first_name":"Tom","last_name":"Rini","email":"trini@ti.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20170822082258.5801-1-lokeshvutla@ti.com/mbox/","series":[],"comments":"http://patchwork.ozlabs.org/api/patches/804325/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/804325/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"nHVY/OuV\";\n\tdkim-atps=neutral"],"Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xc3bC5M0Rz9s83\n\tfor ;\n\tTue, 22 Aug 2017 18:27:50 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 354E4C21E65; Tue, 22 Aug 2017 08:27:38 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id DC837C21D7B;\n\tTue, 22 Aug 2017 08:27:35 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 61626C21D7B; Tue, 22 Aug 2017 08:27:34 +0000 (UTC)","from fllnx209.ext.ti.com (fllnx209.ext.ti.com [198.47.19.16])\n\tby lists.denx.de (Postfix) with ESMTPS id B42B7C21C41\n\tfor ; Tue, 22 Aug 2017 08:27:33 +0000 (UTC)","from dlelxv90.itg.ti.com ([172.17.2.17])\n\tby fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v7M8R6VX015452; \n\tTue, 22 Aug 2017 03:27:06 -0500","from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35])\n\tby dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7M8R1lk011377; \n\tTue, 22 Aug 2017 03:27:01 -0500","from DLEE112.ent.ti.com (157.170.170.23) by DLEE105.ent.ti.com\n\t(157.170.170.35) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tTue, 22 Aug 2017 03:27:01 -0500","from dflp32.itg.ti.com (10.64.6.15) by DLEE112.ent.ti.com\n\t(157.170.170.23) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Tue, 22 Aug 2017 03:27:01 -0500","from a0131933.india.ti.com (ileax41-snat.itg.ti.com\n\t[10.172.224.153])\n\tby dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7M8QwW6010054;\n\tTue, 22 Aug 2017 03:26:59 -0500"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1503390426;\n\tbh=AdCJvmpiMUtH2FX7Y5OtAu1qIk1y35SlyzJnHuaQ+ns=;\n\th=From:To:CC:Subject:Date;\n\tb=nHVY/OuVFgRSAXYtlF1uwXlBhoBScHR0JGNKp+Qr8bCz55tnGVfZhyzG7M5B0MH4o\n\tE6vxQ1uYmjBUy4Qs4dfvVvJ8wwWmPxBdOwiIpfMKS8FeEsCv4MwxOZqGRuIX//Zcsz\n\tcxAuQCO9YUmQO3EmVY1FHjbj4jcjd4nxY7EpdXXU=","From":"Lokesh Vutla ","To":"Tom Rini , ","Date":"Tue, 22 Aug 2017 13:52:58 +0530","Message-ID":"<20170822082258.5801-1-lokeshvutla@ti.com>","X-Mailer":"git-send-email 2.13.0","MIME-Version":"1.0","X-EXCLAIMER-MD-CONFIG":"e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180","Cc":"Tero Kristo ","Subject":"[U-Boot] [PATCH] board: ti: am571x: Add 666MHz support for AM571x\n\tIDK","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"From: Steve Kipisz \n\nAM571x supports DDR running at 666MHz. Right now it is\nclocked at 532MHz which is lower than what is supported.\nIn order to have maximum performance on AM571-IDK,\nswitch DDR to 666MHz.\n\nSigned-off-by: Steve Kipisz \nSigned-off-by: Lokesh Vutla \n---\n arch/arm/include/asm/omap_common.h | 1 +\n board/ti/am57xx/board.c | 35 +++++++++++++++++++++++++++++++++--\n 2 files changed, 34 insertions(+), 2 deletions(-)","diff":"diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h\nindex d7e453e579..8b296c9685 100644\n--- a/arch/arm/include/asm/omap_common.h\n+++ b/arch/arm/include/asm/omap_common.h\n@@ -596,6 +596,7 @@ extern struct prcm_regs const omap4_prcm;\n extern struct prcm_regs const dra7xx_prcm;\n extern struct dplls const **dplls_data;\n extern struct dplls dra7xx_dplls;\n+extern struct dplls dra72x_dplls;\n extern struct vcores_data const **omap_vcores;\n extern const u32 sys_clk_array[8];\n extern struct omap_sys_ctrl_regs const **ctrl;\ndiff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c\nindex 7e7056cf71..3d15cb1dbf 100644\n--- a/board/ti/am57xx/board.c\n+++ b/board/ti/am57xx/board.c\n@@ -223,11 +223,39 @@ static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {\n \t0x0\n };\n \n+static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {\n+\t.sdram_config_init\t\t= 0x61863332,\n+\t.sdram_config\t\t\t= 0x61863332,\n+\t.sdram_config2\t\t\t= 0x08000000,\n+\t.ref_ctrl\t\t\t= 0x0000514d,\n+\t.ref_ctrl_final\t\t\t= 0x0000144a,\n+\t.sdram_tim1\t\t\t= 0xd333887c,\n+\t.sdram_tim2\t\t\t= 0x40b37fe3,\n+\t.sdram_tim3\t\t\t= 0x409f8ada,\n+\t.read_idle_ctrl\t\t\t= 0x00050000,\n+\t.zq_config\t\t\t= 0x5007190b,\n+\t.temp_alert_config\t\t= 0x00000000,\n+\t.emif_ddr_phy_ctlr_1_init\t= 0x0024400f,\n+\t.emif_ddr_phy_ctlr_1\t\t= 0x0e24400f,\n+\t.emif_ddr_ext_phy_ctrl_1\t= 0x10040100,\n+\t.emif_ddr_ext_phy_ctrl_2\t= 0x00910091,\n+\t.emif_ddr_ext_phy_ctrl_3\t= 0x00950095,\n+\t.emif_ddr_ext_phy_ctrl_4\t= 0x009b009b,\n+\t.emif_ddr_ext_phy_ctrl_5\t= 0x009e009e,\n+\t.emif_rd_wr_lvl_rmp_win\t\t= 0x00000000,\n+\t.emif_rd_wr_lvl_rmp_ctl\t\t= 0x80000000,\n+\t.emif_rd_wr_lvl_ctl\t\t= 0x00000000,\n+\t.emif_rd_wr_exec_thresh\t\t= 0x00000305\n+};\n+\n void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)\n {\n \tswitch (emif_nr) {\n \tcase 1:\n-\t\t*regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;\n+\t\tif (board_is_am571x_idk())\n+\t\t\t*regs = &am571x_emif1_ddr3_666mhz_emif_regs;\n+\t\telse\n+\t\t\t*regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;\n \t\tbreak;\n \tcase 2:\n \t\t*regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;\n@@ -513,7 +541,10 @@ void vcores_init(void)\n void hw_data_init(void)\n {\n \t*prcm = &dra7xx_prcm;\n-\t*dplls_data = &dra7xx_dplls;\n+\tif (is_dra72x())\n+\t\t*dplls_data = &dra72x_dplls;\n+\telse\n+\t\t*dplls_data = &dra7xx_dplls;\n \t*ctrl = &dra7xx_ctrl;\n }\n \n","prefixes":["U-Boot"]}