{"id":803864,"url":"http://patchwork.ozlabs.org/api/patches/803864/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20170821072101.29375-9-lokeshvutla@ti.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170821072101.29375-9-lokeshvutla@ti.com>","list_archive_url":null,"date":"2017-08-21T07:20:56","name":"[U-Boot,v2,08/13] board: ti: dra76-evm: Add the pinmux data","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"17a588e199710250f7b4ef4bebb7501eec3e955a","submitter":{"id":14145,"url":"http://patchwork.ozlabs.org/api/people/14145/?format=json","name":"Lokesh Vutla","email":"lokeshvutla@ti.com"},"delegate":{"id":3651,"url":"http://patchwork.ozlabs.org/api/users/3651/?format=json","username":"trini","first_name":"Tom","last_name":"Rini","email":"trini@ti.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20170821072101.29375-9-lokeshvutla@ti.com/mbox/","series":[],"comments":"http://patchwork.ozlabs.org/api/patches/803864/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/803864/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com 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ESMTP id v7L7PMQj002510;\n\tMon, 21 Aug 2017 02:25:22 -0500","from DLEE106.ent.ti.com (157.170.170.36) by DLEE101.ent.ti.com\n\t(157.170.170.31) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tMon, 21 Aug 2017 02:25:21 -0500","from dflp32.itg.ti.com (10.64.6.15) by DLEE106.ent.ti.com\n\t(157.170.170.36) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Mon, 21 Aug 2017 02:25:21 -0500","from a0131933.india.ti.com (ileax41-snat.itg.ti.com\n\t[10.172.224.153])\n\tby dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7L7P3Zi010673;\n\tMon, 21 Aug 2017 02:25:20 -0500"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.8 required=5.0 tests=RCVD_IN_DNSWL_NONE,\n\tT_DKIM_INVALID,\n\tUPPERCASE_50_75 autolearn=no autolearn_force=no version=3.4.0","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1503300322;\n\tbh=FXC5KrNpuseikbStabn6G2q7xqjxedjiVc0HiddAvdE=;\n\th=From:To:CC:Subject:Date:In-Reply-To:References;\n\tb=fTiQ+Wz1O/EK8gl0WqehL1bD38WE3ntGmg9VsO5xAJTNnxO/cyCyajnbYBAVAmb9s\n\tm6vsySO/6Bf2Bv8IMpQ3BzSyiaR4sSsZLMZuLHwcL3pBoYHfEALZiSPkpXKYJzxyVf\n\tmZ1rFJY2JdEMwl1NL9ehIcBP7X/lh1R8AY7oEb+4=","From":"Lokesh Vutla ","To":"Tom Rini , ","Date":"Mon, 21 Aug 2017 12:50:56 +0530","Message-ID":"<20170821072101.29375-9-lokeshvutla@ti.com>","X-Mailer":"git-send-email 2.13.0","In-Reply-To":"<20170821072101.29375-1-lokeshvutla@ti.com>","References":"<20170821072101.29375-1-lokeshvutla@ti.com>","MIME-Version":"1.0","X-EXCLAIMER-MD-CONFIG":"e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180","Cc":"Tero Kristo ","Subject":"[U-Boot] [PATCH v2 08/13] board: ti: dra76-evm: Add the pinmux data","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"Adding pinmux and IODELAY data for dra76-evm.\n\nReviewed-by: Tom Rini \nSigned-off-by: Vignesh R \nSigned-off-by: Lokesh Vutla \n---\n board/ti/dra7xx/evm.c | 6 +\n board/ti/dra7xx/mux_data.h | 294 +++++++++++++++++++++++++++++++++++++++++++++\n 2 files changed, 300 insertions(+)","diff":"diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c\nindex 53226f3167..ad63abd759 100644\n--- a/board/ti/dra7xx/evm.c\n+++ b/board/ti/dra7xx/evm.c\n@@ -783,6 +783,12 @@ void recalibrate_iodelay(void)\n \t\tiodelay = dra742_es1_1_iodelay_cfg_array;\n \t\tniodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);\n \t\tbreak;\n+\tcase DRA762_ES1_0:\n+\t\tpads = dra76x_core_padconf_array;\n+\t\tnpads = ARRAY_SIZE(dra76x_core_padconf_array);\n+\t\tiodelay = dra76x_es1_0_iodelay_cfg_array;\n+\t\tniodelays = ARRAY_SIZE(dra76x_es1_0_iodelay_cfg_array);\n+\t\tbreak;\n \tdefault:\n \tcase DRA752_ES2_0:\n \t\tpads = dra74x_core_padconf_array;\ndiff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h\nindex 2cc4be31b2..3c3a19a0e1 100644\n--- a/board/ti/dra7xx/mux_data.h\n+++ b/board/ti/dra7xx/mux_data.h\n@@ -698,6 +698,194 @@ const struct pad_conf_entry dra74x_core_padconf_array[] = {\n \t{WAKEUP2, (M14)},\t\t/* Wakeup2.gpio1_2 */\n };\n \n+const struct pad_conf_entry dra76x_core_padconf_array[] = {\n+\t{GPMC_AD0, (M3 | PIN_INPUT | MANUAL_MODE)},\t/* gpmc_ad0.vout3_d0 */\n+\t{GPMC_AD1, (M3 | PIN_INPUT | MANUAL_MODE)},\t/* gpmc_ad1.vout3_d1 */\n+\t{GPMC_AD2, (M3 | PIN_INPUT | MANUAL_MODE)},\t/* gpmc_ad2.vout3_d2 */\n+\t{GPMC_AD3, (M3 | PIN_INPUT | MANUAL_MODE)},\t/* gpmc_ad3.vout3_d3 */\n+\t{GPMC_AD4, (M3 | PIN_INPUT | MANUAL_MODE)},\t/* gpmc_ad4.vout3_d4 */\n+\t{GPMC_AD5, (M3 | PIN_INPUT | MANUAL_MODE)},\t/* gpmc_ad5.vout3_d5 */\n+\t{GPMC_AD6, (M3 | PIN_INPUT | MANUAL_MODE)},\t/* gpmc_ad6.vout3_d6 */\n+\t{GPMC_AD7, (M3 | PIN_INPUT | MANUAL_MODE)},\t/* gpmc_ad7.vout3_d7 */\n+\t{GPMC_AD8, (M3 | PIN_INPUT | MANUAL_MODE)},\t/* gpmc_ad8.vout3_d8 */\n+\t{GPMC_AD9, (M3 | PIN_INPUT | MANUAL_MODE)},\t/* gpmc_ad9.vout3_d9 */\n+\t{GPMC_AD10, (M3 | PIN_INPUT | MANUAL_MODE)},\t/* gpmc_ad10.vout3_d10 */\n+\t{GPMC_AD11, (M3 | PIN_INPUT | MANUAL_MODE)},\t/* gpmc_ad11.vout3_d11 */\n+\t{GPMC_AD12, (M3 | PIN_INPUT | MANUAL_MODE)},\t/* gpmc_ad12.vout3_d12 */\n+\t{GPMC_AD13, (M3 | PIN_INPUT | MANUAL_MODE)},\t/* gpmc_ad13.vout3_d13 */\n+\t{GPMC_AD14, (M3 | PIN_INPUT | MANUAL_MODE)},\t/* gpmc_ad14.vout3_d14 */\n+\t{GPMC_AD15, (M3 | PIN_INPUT | MANUAL_MODE)},\t/* gpmc_ad15.vout3_d15 */\n+\t{GPMC_A0, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* gpmc_a0.vout3_d16 */\n+\t{GPMC_A1, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* gpmc_a1.vout3_d17 */\n+\t{GPMC_A2, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* gpmc_a2.vout3_d18 */\n+\t{GPMC_A3, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* gpmc_a3.vout3_d19 */\n+\t{GPMC_A4, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* gpmc_a4.vout3_d20 */\n+\t{GPMC_A5, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* gpmc_a5.vout3_d21 */\n+\t{GPMC_A6, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* gpmc_a6.vout3_d22 */\n+\t{GPMC_A7, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* gpmc_a7.vout3_d23 */\n+\t{GPMC_A8, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* gpmc_a8.vout3_hsync */\n+\t{GPMC_A9, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* gpmc_a9.vout3_vsync */\n+\t{GPMC_A10, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* gpmc_a10.vout3_de */\n+\t{GPMC_A11, (M14 | PIN_INPUT_PULLUP)},\t/* gpmc_a11.gpio2_1 */\n+\t{GPMC_A12, (M14 | PIN_INPUT_PULLUP)},\t/* gpmc_a12.gpio2_2 */\n+\t{GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* gpmc_a13.qspi1_rtclk */\n+\t{GPMC_A14, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* gpmc_a14.qspi1_d3 */\n+\t{GPMC_A15, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* gpmc_a15.qspi1_d2 */\n+\t{GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* gpmc_a16.qspi1_d0 */\n+\t{GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* gpmc_a17.qspi1_d1 */\n+\t{GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* gpmc_a18.qspi1_sclk */\n+\t{GPMC_A19, (M1 | PIN_INPUT_PULLDOWN)},\t/* gpmc_a19.mmc2_dat4 */\n+\t{GPMC_A20, (M1 | PIN_INPUT_PULLDOWN)},\t/* gpmc_a20.mmc2_dat5 */\n+\t{GPMC_A21, (M1 | PIN_INPUT_PULLDOWN)},\t/* gpmc_a21.mmc2_dat6 */\n+\t{GPMC_A22, (M1 | PIN_INPUT_PULLDOWN)},\t/* gpmc_a22.mmc2_dat7 */\n+\t{GPMC_A23, (M1 | PIN_INPUT_PULLDOWN)},\t/* gpmc_a23.mmc2_clk */\n+\t{GPMC_A24, (M1 | PIN_INPUT_PULLDOWN)},\t/* gpmc_a24.mmc2_dat0 */\n+\t{GPMC_A25, (M1 | PIN_INPUT_PULLDOWN)},\t/* gpmc_a25.mmc2_dat1 */\n+\t{GPMC_A26, (M1 | PIN_INPUT_PULLDOWN)},\t/* gpmc_a26.mmc2_dat2 */\n+\t{GPMC_A27, (M1 | PIN_INPUT_PULLDOWN)},\t/* gpmc_a27.mmc2_dat3 */\n+\t{GPMC_CS1, (M1 | PIN_INPUT_PULLUP)},\t/* gpmc_cs1.mmc2_cmd */\n+\t{GPMC_CS0, (M0 | PIN_INPUT_PULLUP)},\t/* gpmc_cs0.gpmc_cs0 */\n+\t{GPMC_CS2, (M1 | PIN_INPUT_PULLUP | MANUAL_MODE)},\t/* gpmc_cs2.qspi1_cs0 */\n+\t{GPMC_CS3, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)},\t/* gpmc_cs3.vout3_clk */\n+\t{GPMC_ADVN_ALE, (M0 | PIN_INPUT_PULLUP)},\t/* gpmc_advn_ale.gpmc_advn_ale */\n+\t{GPMC_OEN_REN, (M0 | PIN_INPUT_PULLUP)},\t/* gpmc_oen_ren.gpmc_oen_ren */\n+\t{GPMC_WEN, (M0 | PIN_INPUT_PULLUP)},\t/* gpmc_wen.gpmc_wen */\n+\t{GPMC_BEN0, (M0 | PIN_INPUT_PULLUP)},\t/* gpmc_ben0.gpmc_ben0 */\n+\t{GPMC_WAIT0, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},\t/* gpmc_wait0.gpmc_wait0 */\n+\t{VIN1A_FLD0, (M14 | PIN_INPUT_PULLUP)},\t/* vin1a_fld0.gpio3_1 */\n+\t{VIN2A_CLK0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vin2a_clk0.vin2a_clk0 */\n+\t{VIN2A_DE0, (M15 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vin2a_de0.Driveroff */\n+\t{VIN2A_FLD0, (M14 | PIN_INPUT_PULLDOWN)},\t/* vin2a_fld0.gpio3_30 */\n+\t{VIN2A_HSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vin2a_hsync0.vin2a_hsync0 */\n+\t{VIN2A_VSYNC0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vin2a_vsync0.vin2a_vsync0 */\n+\t{VIN2A_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vin2a_d0.vin2a_d0 */\n+\t{VIN2A_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vin2a_d1.vin2a_d1 */\n+\t{VIN2A_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vin2a_d2.vin2a_d2 */\n+\t{VIN2A_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vin2a_d3.vin2a_d3 */\n+\t{VIN2A_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vin2a_d4.vin2a_d4 */\n+\t{VIN2A_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vin2a_d5.vin2a_d5 */\n+\t{VIN2A_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vin2a_d6.vin2a_d6 */\n+\t{VIN2A_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vin2a_d7.vin2a_d7 */\n+\t{VIN2A_D8, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vin2a_d8.vin2a_d8 */\n+\t{VIN2A_D9, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vin2a_d9.vin2a_d9 */\n+\t{VIN2A_D10, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vin2a_d10.vin2a_d10 */\n+\t{VIN2A_D11, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vin2a_d11.vin2a_d11 */\n+\t{VIN2A_D12, (M3 | PIN_INPUT | MANUAL_MODE)},\t/* vin2a_d12.rgmii1_txc */\n+\t{VIN2A_D13, (M3 | PIN_INPUT | MANUAL_MODE)},\t/* vin2a_d13.rgmii1_txctl */\n+\t{VIN2A_D14, (M3 | PIN_INPUT | MANUAL_MODE)},\t/* vin2a_d14.rgmii1_txd3 */\n+\t{VIN2A_D15, (M3 | PIN_INPUT | MANUAL_MODE)},\t/* vin2a_d15.rgmii1_txd2 */\n+\t{VIN2A_D16, (M3 | PIN_INPUT | MANUAL_MODE)},\t/* vin2a_d16.rgmii1_txd1 */\n+\t{VIN2A_D17, (M3 | PIN_INPUT | MANUAL_MODE)},\t/* vin2a_d17.rgmii1_txd0 */\n+\t{VIN2A_D18, (M3 | PIN_INPUT | MANUAL_MODE)},\t/* vin2a_d18.rgmii1_rxc */\n+\t{VIN2A_D19, (M3 | PIN_INPUT | MANUAL_MODE)},\t/* vin2a_d19.rgmii1_rxctl */\n+\t{VIN2A_D20, (M3 | PIN_INPUT | MANUAL_MODE)},\t/* vin2a_d20.rgmii1_rxd3 */\n+\t{VIN2A_D21, (M3 | PIN_INPUT | MANUAL_MODE)},\t/* vin2a_d21.rgmii1_rxd2 */\n+\t{VIN2A_D22, (M3 | PIN_INPUT | MANUAL_MODE)},\t/* vin2a_d22.rgmii1_rxd1 */\n+\t{VIN2A_D23, (M3 | PIN_INPUT | MANUAL_MODE)},\t/* vin2a_d23.rgmii1_rxd0 */\n+\t{VOUT1_CLK, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vout1_clk.vout1_clk */\n+\t{VOUT1_DE, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vout1_de.vout1_de */\n+\t{VOUT1_FLD, (M14 | PIN_INPUT_PULLUP)},\t/* vout1_fld.gpio4_21 */\n+\t{VOUT1_HSYNC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vout1_hsync.vout1_hsync */\n+\t{VOUT1_VSYNC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vout1_vsync.vout1_vsync */\n+\t{VOUT1_D0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vout1_d0.vout1_d0 */\n+\t{VOUT1_D1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vout1_d1.vout1_d1 */\n+\t{VOUT1_D2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vout1_d2.vout1_d2 */\n+\t{VOUT1_D3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vout1_d3.vout1_d3 */\n+\t{VOUT1_D4, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vout1_d4.vout1_d4 */\n+\t{VOUT1_D5, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vout1_d5.vout1_d5 */\n+\t{VOUT1_D6, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vout1_d6.vout1_d6 */\n+\t{VOUT1_D7, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vout1_d7.vout1_d7 */\n+\t{VOUT1_D8, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vout1_d8.vout1_d8 */\n+\t{VOUT1_D9, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vout1_d9.vout1_d9 */\n+\t{VOUT1_D10, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vout1_d10.vout1_d10 */\n+\t{VOUT1_D11, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vout1_d11.vout1_d11 */\n+\t{VOUT1_D12, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vout1_d12.vout1_d12 */\n+\t{VOUT1_D13, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vout1_d13.vout1_d13 */\n+\t{VOUT1_D14, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vout1_d14.vout1_d14 */\n+\t{VOUT1_D15, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vout1_d15.vout1_d15 */\n+\t{VOUT1_D16, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vout1_d16.vout1_d16 */\n+\t{VOUT1_D17, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vout1_d17.vout1_d17 */\n+\t{VOUT1_D18, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vout1_d18.vout1_d18 */\n+\t{VOUT1_D19, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vout1_d19.vout1_d19 */\n+\t{VOUT1_D20, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vout1_d20.vout1_d20 */\n+\t{VOUT1_D21, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vout1_d21.vout1_d21 */\n+\t{VOUT1_D22, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vout1_d22.vout1_d22 */\n+\t{VOUT1_D23, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},\t/* vout1_d23.vout1_d23 */\n+\t{MDIO_MCLK, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},\t/* mdio_mclk.mdio_mclk */\n+\t{MDIO_D, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},\t/* mdio_d.mdio_d */\n+\t{RGMII0_TXC, (M0 | PIN_INPUT | MANUAL_MODE)},\t/* rgmii0_txc.rgmii0_txc */\n+\t{RGMII0_TXCTL, (M0 | PIN_INPUT | MANUAL_MODE)},\t/* rgmii0_txctl.rgmii0_txctl */\n+\t{RGMII0_TXD3, (M0 | PIN_INPUT | MANUAL_MODE)},\t/* rgmii0_txd3.rgmii0_txd3 */\n+\t{RGMII0_TXD2, (M0 | PIN_INPUT | MANUAL_MODE)},\t/* rgmii0_txd2.rgmii0_txd2 */\n+\t{RGMII0_TXD1, (M0 | PIN_INPUT | MANUAL_MODE)},\t/* rgmii0_txd1.rgmii0_txd1 */\n+\t{RGMII0_TXD0, (M0 | PIN_INPUT | MANUAL_MODE)},\t/* rgmii0_txd0.rgmii0_txd0 */\n+\t{RGMII0_RXC, (M0 | PIN_INPUT | MANUAL_MODE)},\t/* rgmii0_rxc.rgmii0_rxc */\n+\t{RGMII0_RXCTL, (M0 | PIN_INPUT | MANUAL_MODE)},\t/* rgmii0_rxctl.rgmii0_rxctl */\n+\t{RGMII0_RXD3, (M0 | PIN_INPUT | MANUAL_MODE)},\t/* rgmii0_rxd3.rgmii0_rxd3 */\n+\t{RGMII0_RXD2, (M0 | PIN_INPUT | MANUAL_MODE)},\t/* rgmii0_rxd2.rgmii0_rxd2 */\n+\t{RGMII0_RXD1, (M0 | PIN_INPUT | MANUAL_MODE)},\t/* rgmii0_rxd1.rgmii0_rxd1 */\n+\t{RGMII0_RXD0, (M0 | PIN_INPUT | MANUAL_MODE)},\t/* rgmii0_rxd0.rgmii0_rxd0 */\n+\t{USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)},\t/* usb1_drvvbus.usb1_drvvbus */\n+\t{USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)},\t/* usb2_drvvbus.usb2_drvvbus */\n+\t{GPIO6_14, (M9 | PIN_INPUT_PULLUP)},\t/* gpio6_14.i2c3_sda */\n+\t{GPIO6_15, (M9 | PIN_INPUT_PULLUP)},\t/* gpio6_15.i2c3_scl */\n+\t{GPIO6_16, (M0 | PIN_INPUT_PULLUP)},\t/* gpio6_16.gpio6_16 */\n+\t{XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)},\t/* xref_clk2.atl_clk2 */\n+\t{MCASP1_ACLKX, (M14 | 0x00070000)},\t/* mcasp1_aclkx.gpio7_31 */\n+\t{MCASP1_FSX, (M14 | PIN_INPUT | SLEWCONTROL)},\t/* mcasp1_fsx.gpio7_30 */\n+\t{MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)},\t/* mcasp1_axr0.i2c5_sda */\n+\t{MCASP1_AXR1, (M10 | 0x000f0000)},\t/* mcasp1_axr1.i2c5_scl */\n+\t{MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)},\t/* mcasp1_axr2.gpio5_4 */\n+\t{MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)},\t/* mcasp1_axr3.gpio5_5 */\n+\t{MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)},\t/* mcasp1_axr4.gpio5_6 */\n+\t{MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)},\t/* mcasp1_axr5.gpio5_7 */\n+\t{MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)},\t/* mcasp1_axr6.gpio5_8 */\n+\t{MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)},\t/* mcasp1_axr7.gpio5_9 */\n+\t{MCASP1_AXR12, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},\t/* mcasp1_axr12.mcasp7_axr0 */\n+\t{MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)},\t/* mcasp1_axr13.mcasp7_axr1 */\n+\t{MCASP1_AXR14, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},\t/* mcasp1_axr14.mcasp7_aclkx */\n+\t{MCASP1_AXR15, (M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10)},\t/* mcasp1_axr15.mcasp7_fsx */\n+\t{MCASP2_ACLKR, (M15 | PIN_INPUT_PULLUP)},\t/* mcasp2_aclkr.Driveroff */\n+\t{MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)},\t/* mcasp3_aclkx.mcasp3_aclkx */\n+\t{MCASP3_FSX, (M0 | PIN_INPUT_SLEW)},\t/* mcasp3_fsx.mcasp3_fsx */\n+\t{MCASP3_AXR0, (M0 | PIN_INPUT_SLEW)},\t/* mcasp3_axr0.mcasp3_axr0 */\n+\t{MCASP3_AXR1, (M0 | PIN_INPUT_SLEW | VIRTUAL_MODE6)},\t/* mcasp3_axr1.mcasp3_axr1 */\n+\t{MMC1_CLK, (M0 | PIN_INPUT_PULLUP)},\t/* mmc1_clk.mmc1_clk */\n+\t{MMC1_CMD, (M0 | PIN_INPUT_PULLUP)},\t/* mmc1_cmd.mmc1_cmd */\n+\t{MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)},\t/* mmc1_dat0.mmc1_dat0 */\n+\t{MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)},\t/* mmc1_dat1.mmc1_dat1 */\n+\t{MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)},\t/* mmc1_dat2.mmc1_dat2 */\n+\t{MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)},\t/* mmc1_dat3.mmc1_dat3 */\n+\t{MMC1_SDCD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},\t/* mmc1_sdcd.mmc1_sdcd */\n+\t{MMC1_SDWP, (M14 | PIN_INPUT_SLEW)},\t/* mmc1_sdwp.gpio6_28 */\n+\t{SPI1_SCLK, (M0 | PIN_INPUT_PULLDOWN)},\t/* spi1_sclk.spi1_sclk */\n+\t{SPI1_D1, (M0 | PIN_INPUT_PULLDOWN)},\t/* spi1_d1.spi1_d1 */\n+\t{SPI1_D0, (M0 | PIN_INPUT_PULLDOWN)},\t/* spi1_d0.spi1_d0 */\n+\t{SPI1_CS0, (M0 | PIN_INPUT_PULLUP)},\t/* spi1_cs0.spi1_cs0 */\n+\t{SPI1_CS2, (M6 | 0x000f0000)},\t/* spi1_cs2.hdmi1_hpd */\n+\t{SPI1_CS3, (M6 | 0x000f0000)},\t/* spi1_cs3.hdmi1_cec */\n+\t{SPI2_SCLK, (M1 | PIN_INPUT_PULLDOWN)},\t/* spi2_sclk.uart3_rxd */\n+\t{SPI2_D1, (M1 | PIN_INPUT_SLEW)},\t/* spi2_d1.uart3_txd */\n+\t{SPI2_D0, (M1 | PIN_INPUT_SLEW)},\t/* spi2_d0.uart3_ctsn */\n+\t{SPI2_CS0, (M1 | PIN_INPUT_PULLUP | SLEWCONTROL)},\t/* spi2_cs0.uart3_rtsn */\n+\t{DCAN1_TX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},\t/* dcan1_tx.dcan1_tx */\n+\t{DCAN1_RX, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},\t/* dcan1_rx.dcan1_rx */\n+\t{UART1_RXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},\t/* uart1_rxd.uart1_rxd */\n+\t{UART1_TXD, (M0 | PIN_INPUT_PULLUP | SLEWCONTROL)},\t/* uart1_txd.uart1_txd */\n+\t{UART1_CTSN, (M3 | PIN_INPUT_PULLUP)},\t/* uart1_ctsn.mmc4_clk */\n+\t{UART1_RTSN, (M3 | PIN_INPUT_PULLUP)},\t/* uart1_rtsn.mmc4_cmd */\n+\t{UART2_RXD, (M3 | PIN_INPUT_PULLUP)},\t/* N/A.mmc4_dat0 */\n+\t{UART2_TXD, (M3 | PIN_INPUT_PULLUP)},\t/* uart2_txd.mmc4_dat1 */\n+\t{UART2_CTSN, (M3 | PIN_INPUT_PULLUP)},\t/* uart2_ctsn.mmc4_dat2 */\n+\t{UART2_RTSN, (M3 | PIN_INPUT_PULLUP)},\t/* uart2_rtsn.mmc4_dat3 */\n+\t{I2C2_SDA, (M1 | PIN_INPUT_PULLUP)},\t/* i2c2_sda.hdmi1_ddc_scl */\n+\t{I2C2_SCL, (M1 | PIN_INPUT_PULLUP)},\t/* i2c2_scl.hdmi1_ddc_sda */\n+\t{WAKEUP0, (M14 | PIN_OUTPUT)},\t/* N/A.gpio1_0 */\n+\t{WAKEUP1, (M14 | PIN_OUTPUT)},\t/* N/A.gpio1_1 */\n+\t{WAKEUP2, (M1 | PIN_OUTPUT)},\t/* N/A.sys_nirq2 */\n+\t{WAKEUP3, (M1 | PIN_OUTPUT)},\t/* N/A.sys_nirq1 */\n+};\n+\n #ifdef CONFIG_IODELAY_RECALIBRATION\n const struct iodelay_cfg_entry dra742_es1_1_iodelay_cfg_array[] = {\n \t{0x06F0, 480, 0},\t/* CFG_RGMII0_RXC_IN */\n@@ -826,6 +1014,112 @@ const struct iodelay_cfg_entry dra742_es2_0_iodelay_cfg_array[] = {\n \t{0x0188, 590, 0}, /* CFG_GPMC_A18_OUT */\n \t{0x0374, 0, 0}, /* CFG_GPMC_CS2_OUT */\n };\n+\n+const struct iodelay_cfg_entry dra76x_es1_0_iodelay_cfg_array[] = {\n+\t{0x011C, 787, 0},\t/* CFG_GPMC_A0_OUT */\n+\t{0x0128, 1181, 0},\t/* CFG_GPMC_A10_OUT */\n+\t{0x0144, 0, 0},\t/* CFG_GPMC_A13_IN */\n+\t{0x0150, 2149, 1052},\t/* CFG_GPMC_A14_IN */\n+\t{0x015C, 2121, 997},\t/* CFG_GPMC_A15_IN */\n+\t{0x0168, 2159, 1134},\t/* CFG_GPMC_A16_IN */\n+\t{0x0170, 0, 0},\t/* CFG_GPMC_A16_OUT */\n+\t{0x0174, 2135, 1085},\t/* CFG_GPMC_A17_IN */\n+\t{0x0188, 0, 0},\t/* CFG_GPMC_A18_OUT */\n+\t{0x01A0, 592, 0},\t/* CFG_GPMC_A1_OUT */\n+\t{0x020C, 641, 0},\t/* CFG_GPMC_A2_OUT */\n+\t{0x0218, 1481, 0},\t/* CFG_GPMC_A3_OUT */\n+\t{0x0224, 1775, 0},\t/* CFG_GPMC_A4_OUT */\n+\t{0x0230, 785, 0},\t/* CFG_GPMC_A5_OUT */\n+\t{0x023C, 848, 0},\t/* CFG_GPMC_A6_OUT */\n+\t{0x0248, 851, 0},\t/* CFG_GPMC_A7_OUT */\n+\t{0x0254, 1783, 0},\t/* CFG_GPMC_A8_OUT */\n+\t{0x0260, 951, 0},\t/* CFG_GPMC_A9_OUT */\n+\t{0x026C, 1091, 0},\t/* CFG_GPMC_AD0_OUT */\n+\t{0x0278, 1027, 0},\t/* CFG_GPMC_AD10_OUT */\n+\t{0x0284, 824, 0},\t/* CFG_GPMC_AD11_OUT */\n+\t{0x0290, 1196, 0},\t/* CFG_GPMC_AD12_OUT */\n+\t{0x029C, 754, 0},\t/* CFG_GPMC_AD13_OUT */\n+\t{0x02A8, 665, 0},\t/* CFG_GPMC_AD14_OUT */\n+\t{0x02B4, 1027, 0},\t/* CFG_GPMC_AD15_OUT */\n+\t{0x02C0, 937, 0},\t/* CFG_GPMC_AD1_OUT */\n+\t{0x02CC, 1168, 0},\t/* CFG_GPMC_AD2_OUT */\n+\t{0x02D8, 872, 0},\t/* CFG_GPMC_AD3_OUT */\n+\t{0x02E4, 1092, 0},\t/* CFG_GPMC_AD4_OUT */\n+\t{0x02F0, 576, 0},\t/* CFG_GPMC_AD5_OUT */\n+\t{0x02FC, 1113, 0},\t/* CFG_GPMC_AD6_OUT */\n+\t{0x0308, 943, 0},\t/* CFG_GPMC_AD7_OUT */\n+\t{0x0314, 0, 0},\t/* CFG_GPMC_AD8_OUT */\n+\t{0x0320, 0, 0},\t/* CFG_GPMC_AD9_OUT */\n+\t{0x0374, 0, 0},\t/* CFG_GPMC_CS2_OUT */\n+\t{0x0380, 1801, 948},\t/* CFG_GPMC_CS3_OUT */\n+\t{0x06F0, 451, 0},\t/* CFG_RGMII0_RXC_IN */\n+\t{0x06FC, 127, 1571},\t/* CFG_RGMII0_RXCTL_IN */\n+\t{0x0708, 165, 1178},\t/* CFG_RGMII0_RXD0_IN */\n+\t{0x0714, 136, 1302},\t/* CFG_RGMII0_RXD1_IN */\n+\t{0x0720, 0, 1520},\t/* CFG_RGMII0_RXD2_IN */\n+\t{0x072C, 28, 1690},\t/* CFG_RGMII0_RXD3_IN */\n+\t{0x0740, 121, 0},\t/* CFG_RGMII0_TXC_OUT */\n+\t{0x074C, 60, 0},\t/* CFG_RGMII0_TXCTL_OUT */\n+\t{0x0758, 153, 0},\t/* CFG_RGMII0_TXD0_OUT */\n+\t{0x0764, 35, 0},\t/* CFG_RGMII0_TXD1_OUT */\n+\t{0x0770, 0, 0},\t/* CFG_RGMII0_TXD2_OUT */\n+\t{0x077C, 172, 0},\t/* CFG_RGMII0_TXD3_OUT */\n+\t{0x0A38, 0, 0},\t/* CFG_VIN2A_CLK0_IN */\n+\t{0x0A44, 2180, 0},\t/* CFG_VIN2A_D0_IN */\n+\t{0x0A50, 2297, 110},\t/* CFG_VIN2A_D10_IN */\n+\t{0x0A5C, 1938, 0},\t/* CFG_VIN2A_D11_IN */\n+\t{0x0A70, 147, 0},\t/* CFG_VIN2A_D12_OUT */\n+\t{0x0A7C, 110, 0},\t/* CFG_VIN2A_D13_OUT */\n+\t{0x0A88, 18, 0},\t/* CFG_VIN2A_D14_OUT */\n+\t{0x0A94, 82, 0},\t/* CFG_VIN2A_D15_OUT */\n+\t{0x0AA0, 33, 0},\t/* CFG_VIN2A_D16_OUT */\n+\t{0x0AAC, 0, 0},\t/* CFG_VIN2A_D17_OUT */\n+\t{0x0AB0, 417, 0},\t/* CFG_VIN2A_D18_IN */\n+\t{0x0ABC, 156, 843},\t/* CFG_VIN2A_D19_IN */\n+\t{0x0AC8, 2326, 309},\t/* CFG_VIN2A_D1_IN */\n+\t{0x0AD4, 223, 1413},\t/* CFG_VIN2A_D20_IN */\n+\t{0x0AE0, 169, 1415},\t/* CFG_VIN2A_D21_IN */\n+\t{0x0AEC, 43, 1150},\t/* CFG_VIN2A_D22_IN */\n+\t{0x0AF8, 0, 1210},\t/* CFG_VIN2A_D23_IN */\n+\t{0x0B04, 2057, 0},\t/* CFG_VIN2A_D2_IN */\n+\t{0x0B10, 2440, 257},\t/* CFG_VIN2A_D3_IN */\n+\t{0x0B1C, 2142, 0},\t/* CFG_VIN2A_D4_IN */\n+\t{0x0B28, 2455, 252},\t/* CFG_VIN2A_D5_IN */\n+\t{0x0B34, 1883, 0},\t/* CFG_VIN2A_D6_IN */\n+\t{0x0B40, 2229, 0},\t/* CFG_VIN2A_D7_IN */\n+\t{0x0B4C, 2250, 151},\t/* CFG_VIN2A_D8_IN */\n+\t{0x0B58, 2279, 27},\t/* CFG_VIN2A_D9_IN */\n+\t{0x0B7C, 2233, 0},\t/* CFG_VIN2A_HSYNC0_IN */\n+\t{0x0B88, 1936, 0},\t/* CFG_VIN2A_VSYNC0_IN */\n+\t{0x0B9C, 1281, 497},\t/* CFG_VOUT1_CLK_OUT */\n+\t{0x0BA8, 379, 0},\t/* CFG_VOUT1_D0_OUT */\n+\t{0x0BB4, 441, 0},\t/* CFG_VOUT1_D10_OUT */\n+\t{0x0BC0, 461, 0},\t/* CFG_VOUT1_D11_OUT */\n+\t{0x0BCC, 1189, 0},\t/* CFG_VOUT1_D12_OUT */\n+\t{0x0BD8, 312, 0},\t/* CFG_VOUT1_D13_OUT */\n+\t{0x0BE4, 298, 0},\t/* CFG_VOUT1_D14_OUT */\n+\t{0x0BF0, 284, 0},\t/* CFG_VOUT1_D15_OUT */\n+\t{0x0BFC, 152, 0},\t/* CFG_VOUT1_D16_OUT */\n+\t{0x0C08, 216, 0},\t/* CFG_VOUT1_D17_OUT */\n+\t{0x0C14, 408, 0},\t/* CFG_VOUT1_D18_OUT */\n+\t{0x0C20, 519, 0},\t/* CFG_VOUT1_D19_OUT */\n+\t{0x0C2C, 475, 0},\t/* CFG_VOUT1_D1_OUT */\n+\t{0x0C38, 316, 0},\t/* CFG_VOUT1_D20_OUT */\n+\t{0x0C44, 59, 0},\t/* CFG_VOUT1_D21_OUT */\n+\t{0x0C50, 221, 0},\t/* CFG_VOUT1_D22_OUT */\n+\t{0x0C5C, 96, 0},\t/* CFG_VOUT1_D23_OUT */\n+\t{0x0C68, 264, 0},\t/* CFG_VOUT1_D2_OUT */\n+\t{0x0C74, 421, 0},\t/* CFG_VOUT1_D3_OUT */\n+\t{0x0C80, 1257, 0},\t/* CFG_VOUT1_D4_OUT */\n+\t{0x0C8C, 432, 0},\t/* CFG_VOUT1_D5_OUT */\n+\t{0x0C98, 436, 0},\t/* CFG_VOUT1_D6_OUT */\n+\t{0x0CA4, 440, 0},\t/* CFG_VOUT1_D7_OUT */\n+\t{0x0CB0, 81, 100},\t/* CFG_VOUT1_D8_OUT */\n+\t{0x0CBC, 471, 0},\t/* CFG_VOUT1_D9_OUT */\n+\t{0x0CC8, 0, 0},\t/* CFG_VOUT1_DE_OUT */\n+\t{0x0CE0, 0, 0},\t/* CFG_VOUT1_HSYNC_OUT */\n+\t{0x0CEC, 815, 0},\t/* CFG_VOUT1_VSYNC_OUT */\n+};\n #endif\n \n #endif /* _MUX_DATA_DRA7XX_H_ */\n","prefixes":["U-Boot","v2","08/13"]}