{"id":803168,"url":"http://patchwork.ozlabs.org/api/patches/803168/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1503052823-17206-1-git-send-email-Ashish.Kumar@nxp.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1503052823-17206-1-git-send-email-Ashish.Kumar@nxp.com>","list_archive_url":null,"date":"2017-08-18T10:40:22","name":"[U-Boot,v2,1/2] armv8: fsl-layerscape: Support to add RGMII for ls1088aqds","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"1d35c036839e1d3123293dc6b4ca12979e9cf274","submitter":{"id":68053,"url":"http://patchwork.ozlabs.org/api/people/68053/?format=json","name":"Ashish Kumar","email":"Ashish.kumar@nxp.com"},"delegate":{"id":2666,"url":"http://patchwork.ozlabs.org/api/users/2666/?format=json","username":"yorksun","first_name":"York","last_name":"Sun","email":"yorksun@freescale.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1503052823-17206-1-git-send-email-Ashish.Kumar@nxp.com/mbox/","series":[],"comments":"http://patchwork.ozlabs.org/api/patches/803168/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/803168/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(400006)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:CY4PR03MB3317; ","X-Forefront-PRVS":"040359335D","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"18 Aug 2017 10:40:20.2739\n\t(UTC)","X-MS-Exchange-CrossTenant-Id":"5afe0b00-7697-4969-b663-5eab37d5f47e","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"CY4PR03MB3317","Cc":"Amrita Kumari ","Subject":"[U-Boot] [PATCH v2 1/2] armv8: fsl-layerscape: Support to add RGMII\n\tfor ls1088aqds","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"This patch adds support for RGMII protocol\n\nNXP's LDPAA2 support RGMII protocol. LS1088A is the\nfirst Soc supporting both RGMII and SGMII.\n\nSigned-off-by: Prabhakar Kushwaha \nSigned-off-by: Amrita Kumari \nSigned-off-by: Ashish Kumar \n---\ndepends upon base platform patches\n\nThis is v2 for https://patchwork.ozlabs.org/patch/755617/\nv2:\n1.Add description for EC1 and EC2\n2.Rename SYS_HAS_RGMII to SYS_FSL_HAS_RGMII \n\n arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 21 +++++++++++++++++\n arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 4 ++++\n .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 1 +\n .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 6 +++++\n board/freescale/ls1088a/eth_ls1088aqds.c | 1 -\n drivers/net/ldpaa_eth/ldpaa_wriop.c | 9 ++++++++\n drivers/net/ldpaa_eth/ls1088a.c | 27 ++++++++++++++++++++++\n include/fsl-mc/ldpaa_wriop.h | 2 ++\n 8 files changed, 70 insertions(+), 1 deletion(-)","diff":"diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\nindex be9e401..91e04f3 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\n@@ -56,6 +56,8 @@ config ARCH_LS1088A\n \tselect SYS_FSL_DDR\n \tselect SYS_FSL_DDR_LE\n \tselect SYS_FSL_DDR_VER_50\n+\tselect SYS_FSL_EC1\n+\tselect SYS_FSL_EC2\n \tselect SYS_FSL_ERRATUM_A009803\n \tselect SYS_FSL_ERRATUM_A009942\n \tselect SYS_FSL_ERRATUM_A010165\n@@ -63,6 +65,7 @@ config ARCH_LS1088A\n \tselect SYS_FSL_ERRATUM_A008850\n \tselect SYS_FSL_HAS_CCI400\n \tselect SYS_FSL_HAS_DDR4\n+\tselect SYS_FSL_HAS_RGMII\n \tselect SYS_FSL_HAS_SEC\n \tselect SYS_FSL_SEC_COMPAT_5\n \tselect SYS_FSL_SEC_LE\n@@ -405,6 +408,18 @@ config RESV_RAM\n \t be at the high end of physical memory. The reserve RAM may be\n \t excluded from memory bank(s) passed to OS, or marked as reserved.\n \n+config SYS_FSL_EC1\n+\tbool\n+\thelp\n+\t Ethernet controller 1, this is connected to MAC3.\n+\t Provides DPAA2 capabilities\n+\n+config SYS_FSL_EC2\n+\tbool\n+\thelp\n+\t Ethernet controller 2, this is connected to MAC4.\n+\t Provides DPAA2 capabilities\n+\n config SYS_FSL_ERRATUM_A008336\n \tbool\n \n@@ -429,6 +444,12 @@ config SYS_FSL_ERRATUM_A009660\n config SYS_FSL_ERRATUM_A009929\n \tbool\n \n+\n+config SYS_FSL_HAS_RGMII\n+\tbool\n+\tdepends on SYS_FSL_EC1 || SYS_FSL_EC2\n+\n+\n config SYS_MC_RSV_MEM_ALIGN\n \thex \"Management Complex reserved memory alignment\"\n \tdepends on RESV_RAM\ndiff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c\nindex ec58065..3c9a5ed 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c\n@@ -517,6 +517,10 @@ int arch_early_init_r(void)\n \t\t\tprintf(\"Did not wake secondary cores\\n\");\n \t}\n \n+#ifdef CONFIG_SYS_FSL_HAS_RGMII\n+\tfsl_rgmii_init();\n+#endif\n+\n #ifdef CONFIG_SYS_HAS_SERDES\n \tfsl_serdes_init();\n #endif\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h\nindex a2c7578..12fd6b8 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h\n@@ -159,6 +159,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device);\n enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);\n int is_serdes_prtcl_valid(int serdes, u32 prtcl);\n int serdes_get_number(int serdes, int cfg);\n+void fsl_rgmii_init(void);\n \n #ifdef CONFIG_FSL_LSCH2\n const char *serdes_clock_to_string(u32 clock);\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\nindex 99a7413..ffc5fa2 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\n@@ -247,6 +247,12 @@ struct ccsr_gur {\n #define FSL_CHASSIS3_SRDS1_REGSR\t29\n #define FSL_CHASSIS3_SRDS2_REGSR\t29\n #elif defined(CONFIG_ARCH_LS1088A)\n+#define FSL_CHASSIS3_EC1_REGSR 26\n+#define FSL_CHASSIS3_EC2_REGSR 26\n+#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK 0x00000007\n+#define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT 0\n+#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK 0x00000038\n+#define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT 3\n #define\tFSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK\t0xFFFF0000\n #define\tFSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT\t16\n #define\tFSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK\t0x0000FFFF\ndiff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c\nindex 3e78ac7..a73896d 100644\n--- a/board/freescale/ls1088a/eth_ls1088aqds.c\n+++ b/board/freescale/ls1088a/eth_ls1088aqds.c\n@@ -597,7 +597,6 @@ int board_eth_init(bd_t *bis)\n \n \t/* Register the real MDIO1 bus */\n \tfm_memac_mdio_init(bis, memac_mdio0_info);\n-\n \t/* Register the muxing front-ends to the MDIO buses */\n \tls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII1);\n \tls1088a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_RGMII2);\ndiff --git a/drivers/net/ldpaa_eth/ldpaa_wriop.c b/drivers/net/ldpaa_eth/ldpaa_wriop.c\nindex f7f26c2..831a330 100644\n--- a/drivers/net/ldpaa_eth/ldpaa_wriop.c\n+++ b/drivers/net/ldpaa_eth/ldpaa_wriop.c\n@@ -37,6 +37,15 @@ void wriop_init_dpmac(int sd, int dpmac_id, int lane_prtcl)\n \t}\n }\n \n+void wriop_init_dpmac_enet_if(int dpmac_id, phy_interface_t enet_if)\n+{\n+\tdpmac_info[dpmac_id].enabled = 1;\n+\tdpmac_info[dpmac_id].id = dpmac_id;\n+\tdpmac_info[dpmac_id].phy_addr = -1;\n+\tdpmac_info[dpmac_id].enet_if = enet_if;\n+}\n+\n+\n /*TODO what it do */\n static int wriop_dpmac_to_index(int dpmac_id)\n {\ndiff --git a/drivers/net/ldpaa_eth/ls1088a.c b/drivers/net/ldpaa_eth/ls1088a.c\nindex 703945c..061935e 100644\n--- a/drivers/net/ldpaa_eth/ls1088a.c\n+++ b/drivers/net/ldpaa_eth/ls1088a.c\n@@ -8,6 +8,7 @@\n #include \n #include \n #include \n+#include \n \n u32 dpmac_to_devdisr[] = {\n \t[WRIOP1_DPMAC1] = FSL_CHASSIS3_DEVDISR2_DPMAC1,\n@@ -85,3 +86,29 @@ void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)\n \t\tbreak;\n \t}\n }\n+\n+#ifdef CONFIG_SYS_FSL_HAS_RGMII\n+void fsl_rgmii_init(void)\n+{\n+\tstruct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);\n+\tu32 ec;\n+\n+#ifdef CONFIG_SYS_FSL_EC1\n+\tec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR - 1])\n+\t\t& FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK;\n+\tec >>= FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT;\n+\n+\tif (!ec)\n+\t\twriop_init_dpmac_enet_if(4, PHY_INTERFACE_MODE_RGMII);\n+#endif\n+\n+#ifdef CONFIG_SYS_FSL_EC2\n+\tec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR - 1])\n+\t\t& FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK;\n+\tec >>= FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT;\n+\n+\tif (!ec)\n+\t\twriop_init_dpmac_enet_if(5, PHY_INTERFACE_MODE_RGMII);\n+#endif\n+}\n+#endif\ndiff --git a/include/fsl-mc/ldpaa_wriop.h b/include/fsl-mc/ldpaa_wriop.h\nindex 8ae0fc0..0ca4956 100644\n--- a/include/fsl-mc/ldpaa_wriop.h\n+++ b/include/fsl-mc/ldpaa_wriop.h\n@@ -69,4 +69,6 @@ void wriop_dpmac_disable(int);\n void wriop_dpmac_enable(int);\n phy_interface_t wriop_dpmac_enet_if(int, int);\n void wriop_init_dpmac_qsgmii(int, int);\n+void wriop_init_rgmii(void);\n+void wriop_init_dpmac_enet_if(int , phy_interface_t);\n #endif\t/* __LDPAA_WRIOP_H */\n","prefixes":["U-Boot","v2","1/2"]}