{"id":802407,"url":"http://patchwork.ozlabs.org/api/patches/802407/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1502955089-2049-5-git-send-email-ran.wang_1@nxp.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1502955089-2049-5-git-send-email-ran.wang_1@nxp.com>","list_archive_url":null,"date":"2017-08-17T07:31:26","name":"[U-Boot,v3,5/8] armv7: Add workaround for USB erratum A-009008","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"294ef4acc3c7a0b093268a76d5290cfe2d635dde","submitter":{"id":71939,"url":"http://patchwork.ozlabs.org/api/people/71939/?format=json","name":"Ran Wang","email":"ran.wang_1@nxp.com"},"delegate":{"id":2666,"url":"http://patchwork.ozlabs.org/api/users/2666/?format=json","username":"yorksun","first_name":"York","last_name":"Sun","email":"yorksun@freescale.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1502955089-2049-5-git-send-email-ran.wang_1@nxp.com/mbox/","series":[],"comments":"http://patchwork.ozlabs.org/api/patches/802407/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/802407/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(400006)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:CO2PR03MB2261; ","X-Forefront-PRVS":"0402872DA1","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"17 Aug 2017 07:48:43.5037\n\t(UTC)","X-MS-Exchange-CrossTenant-Id":"5afe0b00-7697-4969-b663-5eab37d5f47e","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"CO2PR03MB2261","Cc":"Priyanka Jain , ran.wang_1@nxp.com","Subject":"[U-Boot] [PATCH v3 5/8] armv7: Add workaround for USB erratum\n\tA-009008","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"USB High Speed (HS) EYE Height Adjustment\nUSB HS speed eye diagram fails with the default value at\nmany corners, particularly at a high temperature\n\nOptimal eye at TXVREFTUNE value to 1001 is ovserved, change\nset the same value.\n\nSigned-off-by: Sriram Dash \nSigned-off-by: Suresh Gupta \nSigned-off-by: Ran Wang \n---\nChange in v3:\n- none\n\nChange in v2:\n\tIn function erratum_a009008():\n\t1.Put a blank line after variable declaration.\n\n arch/arm/cpu/armv7/ls102xa/Kconfig | 6 ++++++\n arch/arm/cpu/armv7/ls102xa/soc.c | 15 +++++++++++++++\n arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 4 ++++\n 3 files changed, 25 insertions(+)","diff":"diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig\nindex 6a013b2..96e9782 100644\n--- a/arch/arm/cpu/armv7/ls102xa/Kconfig\n+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig\n@@ -5,6 +5,7 @@ config ARCH_LS1021A\n \tselect SYS_FSL_ERRATUM_A009663\n \tselect SYS_FSL_ERRATUM_A009942\n \tselect SYS_FSL_ERRATUM_A010315\n+\tselect SYS_FSL_ERRATUM_A009008\n \tselect SYS_FSL_SRDS_1\n \tselect SYS_HAS_SERDES\n \tselect SYS_FSL_DDR_BE if SYS_FSL_DDR\n@@ -51,6 +52,11 @@ config SECURE_BOOT\n config SYS_FSL_ERRATUM_A010315\n \tbool \"Workaround for PCIe erratum A010315\"\n \n+config SYS_FSL_ERRATUM_A009008\n+\tbool\n+\thelp\n+\t\tWorkaround for USB erratum A009008\n+\n config SYS_FSL_SRDS_1\n \tbool\n \ndiff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c\nindex b84a1a6..ac060bb 100644\n--- a/arch/arm/cpu/armv7/ls102xa/soc.c\n+++ b/arch/arm/cpu/armv7/ls102xa/soc.c\n@@ -60,6 +60,18 @@ unsigned int get_soc_major_rev(void)\n \treturn major;\n }\n \n+static void erratum_a009008(void)\n+{\n+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008\n+\tu32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;\n+\tu32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4);\n+\n+\tval &= ~(0xF << 6);\n+\tout_be32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6));\n+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */\n+}\n+\n+\n void s_init(void)\n {\n }\n@@ -146,6 +158,9 @@ int arch_soc_init(void)\n \t */\n \tout_be32(&scfg->eddrtqcfg, 0x63b20042);\n \n+\t/* Erratum */\n+\terratum_a009008();\n+\n \treturn 0;\n }\n \ndiff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h\nindex c34fd63..6ea8c4b 100644\n--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h\n+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h\n@@ -173,6 +173,10 @@ struct ccsr_gur {\n #define SCFG_PMCINTECR_ETSECERRG1\t0x00040000\n #define SCFG_CLUSTERPMCR_WFIL2EN\t0x80000000\n \n+#define SCFG_BASE\t\t\t0x01570000\n+#define SCFG_USB3PRM1CR\t\t\t0x070\n+#define USB_TXVREFTUNE\t\t\t0x9\n+\n /* Supplemental Configuration Unit */\n struct ccsr_scfg {\n \tu32 dpslpcr;\n","prefixes":["U-Boot","v3","5/8"]}