{"id":802397,"url":"http://patchwork.ozlabs.org/api/patches/802397/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1502955089-2049-4-git-send-email-ran.wang_1@nxp.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1502955089-2049-4-git-send-email-ran.wang_1@nxp.com>","list_archive_url":null,"date":"2017-08-17T07:31:25","name":"[U-Boot,v3,4/8] armv8: Add workaround for USB erratum A-009007","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"ebc41d89270a9ed7c0f9d4894e9040ebaaeb9e51","submitter":{"id":71939,"url":"http://patchwork.ozlabs.org/api/people/71939/?format=json","name":"Ran Wang","email":"ran.wang_1@nxp.com"},"delegate":{"id":2666,"url":"http://patchwork.ozlabs.org/api/users/2666/?format=json","username":"yorksun","first_name":"York","last_name":"Sun","email":"yorksun@freescale.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1502955089-2049-4-git-send-email-ran.wang_1@nxp.com/mbox/","series":[],"comments":"http://patchwork.ozlabs.org/api/patches/802397/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/802397/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(400006)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:DM5PR03MB3322; ","X-Forefront-PRVS":"0402872DA1","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"17 Aug 2017 07:48:39.5828\n\t(UTC)","X-MS-Exchange-CrossTenant-Id":"5afe0b00-7697-4969-b663-5eab37d5f47e","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"DM5PR03MB3322","Cc":"Priyanka Jain , ran.wang_1@nxp.com","Subject":"[U-Boot] [PATCH v3 4/8] armv8: Add workaround for USB erratum\n\tA-009007","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"Rx Compliance tests may fail intermittently at high\njitter frequencies using default register values.\n\nChanges identified in setup makes the Rx compliance test pass.\n\nSigned-off-by: Sriram Dash \nSigned-off-by: Rajesh Bhagat \nSigned-off-by: Suresh Gupta \nSigned-off-by: Ran Wang \n---\nChange in v3:\n- none\n\nChange in v2:\n\tIn function erratum_a009007():\n\t1.Put a blank line after variable declaration.\n\t2.Create a mcro to run for each USB for easier to read and maintain.\n\n arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 12 ++++++-\n arch/arm/cpu/armv8/fsl-layerscape/soc.c | 40 ++++++++++++++++++++++\n .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 8 +++++\n .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 9 +++++\n 4 files changed, 68 insertions(+), 1 deletion(-)","diff":"diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\nindex a2de86b..1744ed9 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\n@@ -25,6 +25,7 @@ config ARCH_LS1043A\n \tselect SYS_FSL_ERRATUM_A009008\n \tselect SYS_FSL_ERRATUM_A009798\n \tselect SYS_FSL_ERRATUM_A008997\n+\tselect SYS_FSL_ERRATUM_A009007\n \tselect SYS_FSL_HAS_DDR3\n \tselect SYS_FSL_HAS_DDR4\n \tselect ARCH_EARLY_INIT_R\n@@ -49,6 +50,7 @@ config ARCH_LS1046A\n \tselect SYS_FSL_ERRATUM_A009008\n \tselect SYS_FSL_ERRATUM_A009798\n \tselect SYS_FSL_ERRATUM_A008997\n+\tselect SYS_FSL_ERRATUM_A009007\n \tselect SYS_FSL_HAS_DDR4\n \tselect SYS_FSL_SRDS_2\n \tselect ARCH_EARLY_INIT_R\n@@ -88,6 +90,7 @@ config ARCH_LS2080A\n \tselect SYS_FSL_ERRATUM_A009008\n \tselect SYS_FSL_ERRATUM_A009798\n \tselect SYS_FSL_ERRATUM_A008997\n+\tselect SYS_FSL_ERRATUM_A009007\n \tselect ARCH_EARLY_INIT_R\n \tselect BOARD_EARLY_INIT_F\n \n@@ -238,7 +241,14 @@ config SYS_FSL_ERRATUM_A009798\n \tbool \"Workaround for USB PHY erratum A009798\"\n \n config SYS_FSL_ERRATUM_A008997\n-\tbool \"Workaround for USB PHY erratum A008997\"\n+\tbool\n+\thelp\n+\t\tWorkaround for USB PHY erratum A008997\n+\n+config SYS_FSL_ERRATUM_A009007\n+\tbool\n+\thelp\n+\t\tWorkaround for USB PHY erratum A009007\n \n config MAX_CPUS\n \tint \"Maximum number of CPUs permitted for Layerscape\"\ndiff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c\nindex f0dac99..624ee82 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c\n@@ -124,6 +124,44 @@ static void erratum_a008997(void)\n #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */\n }\n \n+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)\n+\n+#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy)\t\\\n+\tout_be16((phy) + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1);\t\\\n+\tout_be16((phy) + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2);\t\\\n+\tout_be16((phy) + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3);\t\\\n+\tout_be16((phy) + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)\n+\n+#elif defined(CONFIG_ARCH_LS2080A)\n+\n+#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy)\t\\\n+\tout_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \\\n+\tout_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \\\n+\tout_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \\\n+\tout_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)\n+\n+#endif\n+\n+static void erratum_a009007(void)\n+{\n+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)\n+\tvoid __iomem *usb_phy = (void __iomem *)USB_PHY1;\n+\n+\tPROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);\n+\n+\tusb_phy = (void __iomem *)USB_PHY2;\n+\tPROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);\n+\n+\tusb_phy = (void __iomem *)USB_PHY3;\n+\tPROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);\n+#elif defined(CONFIG_ARCH_LS2080A)\n+\tvoid __iomem *dcsr = (void __iomem *)DCSR_BASE;\n+\n+\tPROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);\n+\tPROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);\n+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */\n+}\n+\n #if defined(CONFIG_FSL_LSCH3)\n /*\n * This erratum requires setting a value to eddrtqcr1 to\n@@ -273,6 +311,7 @@ void fsl_lsch3_early_init_f(void)\n \terratum_a009008();\n \terratum_a009798();\n \terratum_a008997();\n+\terratum_a009007();\n #ifdef CONFIG_CHAIN_OF_TRUST\n \t/* In case of Secure Boot, the IBR configures the SMMU\n \t* to allow only Secure transactions.\n@@ -551,6 +590,7 @@ void fsl_lsch2_early_init_f(void)\n \terratum_a009008();\n \terratum_a009798();\n \terratum_a008997();\n+\terratum_a009007();\n }\n #endif\n \ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h\nindex 2e52078..69fd79c 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h\n@@ -347,6 +347,14 @@ struct ccsr_gur {\n #define USB_TXVREFTUNE\t\t\t0x9\n #define USB_SQRXTUNE\t\t\t0xFC7FFFFF\n #define USB_PCSTXSWINGFULL\t\t0x47\n+#define USB_PHY1\t\t\t0x084F0000\n+#define USB_PHY2\t\t\t0x08500000\n+#define USB_PHY3\t\t\t0x08510000\n+#define USB_PHY_RX_OVRD_IN_HI\t\t0x200c\n+#define USB_PHY_RX_EQ_VAL_1\t\t0x0000\n+#define USB_PHY_RX_EQ_VAL_2\t\t0x0080\n+#define USB_PHY_RX_EQ_VAL_3\t\t0x0380\n+#define USB_PHY_RX_EQ_VAL_4\t\t0x0b80\n \n #define SCFG_SNPCNFGCR_SECRDSNP\t\t0x80000000\n #define SCFG_SNPCNFGCR_SECWRSNP\t\t0x40000000\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\nindex 2d309d5..238d647 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\n@@ -137,6 +137,15 @@\n #define USB_SQRXTUNE\t\t\t0xFC7FFFFF\n #define SCFG_QSPICLKCTLR\t0x10\n \n+#define DCSR_BASE\t\t0x700000000ULL\n+#define DCSR_USB_PHY1\t\t\t0x4600000\n+#define DCSR_USB_PHY2\t\t\t0x4610000\n+#define DCSR_USB_PHY_RX_OVRD_IN_HI\t0x200C\n+#define USB_PHY_RX_EQ_VAL_1\t\t0x0000\n+#define USB_PHY_RX_EQ_VAL_2\t\t0x0080\n+#define USB_PHY_RX_EQ_VAL_3\t\t0x0380\n+#define USB_PHY_RX_EQ_VAL_4\t\t0x0b80\n+\n #define TP_ITYP_AV\t\t0x00000001\t/* Initiator available */\n #define TP_ITYP_TYPE(x)\t(((x) & 0x6) >> 1)\t/* Initiator Type */\n #define TP_ITYP_TYPE_ARM\t0x0\n","prefixes":["U-Boot","v3","4/8"]}