{"id":801455,"url":"http://patchwork.ozlabs.org/api/patches/801455/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-i2c/patch/20170815072102.23067-1-andrew@aj.id.au/","project":{"id":35,"url":"http://patchwork.ozlabs.org/api/projects/35/?format=json","name":"Linux I2C development","link_name":"linux-i2c","list_id":"linux-i2c.vger.kernel.org","list_email":"linux-i2c@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170815072102.23067-1-andrew@aj.id.au>","list_archive_url":null,"date":"2017-08-15T07:21:02","name":"i2c: aspeed: Retain delay/setup/hold values when configuring bus frequency","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"624e48c3ff555795529a70b0dbda7c4d055f8827","submitter":{"id":68332,"url":"http://patchwork.ozlabs.org/api/people/68332/?format=json","name":"Andrew Jeffery","email":"andrew@aj.id.au"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-i2c/patch/20170815072102.23067-1-andrew@aj.id.au/mbox/","series":[],"comments":"http://patchwork.ozlabs.org/api/patches/801455/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/801455/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-i2c-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=aj.id.au header.i=@aj.id.au header.b=\"l2Onq2+6\";\n\tdkim=pass (2048-bit key;\n\tunprotected) header.d=messagingengine.com\n\theader.i=@messagingengine.com header.b=\"llInxmLf\"; \n\tdkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xWkSN20NMz9t32\n\tfor ;\n\tTue, 15 Aug 2017 17:21:56 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753336AbdHOHVm (ORCPT );\n\tTue, 15 Aug 2017 03:21:42 -0400","from out4-smtp.messagingengine.com ([66.111.4.28]:58943 \"EHLO\n\tout4-smtp.messagingengine.com\" rhost-flags-OK-OK-OK-OK)\n\tby vger.kernel.org with ESMTP id S1753260AbdHOHVk (ORCPT\n\t); Tue, 15 Aug 2017 03:21:40 -0400","from compute4.internal (compute4.nyi.internal [10.202.2.44])\n\tby mailout.nyi.internal (Postfix) with ESMTP id 4A68A2083F;\n\tTue, 15 Aug 2017 03:21:40 -0400 (EDT)","from frontend2 ([10.202.2.161])\n\tby compute4.internal (MEProxy); Tue, 15 Aug 2017 03:21:40 -0400","from keelia.au.ibm.com (unknown [203.0.153.9])\n\tby mail.messagingengine.com (Postfix) with ESMTPA id 75E56244B4;\n\tTue, 15 Aug 2017 03:21:36 -0400 (EDT)"],"DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/relaxed; d=aj.id.au; h=cc\n\t:date:from:message-id:subject:to:x-me-sender:x-me-sender\n\t:x-sasl-enc:x-sasl-enc; s=fm1; bh=OgKfMeb2Y9tE1TVykTcqQUGm11+u9B\n\tLmCxt1DDfx4O4=; b=l2Onq2+6+wT9UPaW9vQQf/1auTDId8hCV/xpRQQhghfjL9\n\tItefnjtGvZyw6UssHQo1R0XBRTNftnY65hw8VLrwFLpJSuRu0ll4AxmbrZzb2jhw\n\t+FuipAha5yeqemfpEvAx+43k7ezoFrK4219BQIa3FrUlhuK8oqrfeEt3m1kCJVD2\n\tAOrtsUb3NWJ3LrdbvEnR1bbsbfMkFUxwQc2D7lPuBRT662gAQS509lF9oOd3bjVO\n\tyCm3Cv+vq922cfU0evT2qK9qr1wFON9kbDm2sQEmE1xrR3WdCXhGnihZH9C+a+XW\n\tqi0NdMRkS3BgzTG6GeiGgeF4AABQY397NbismPlw==","v=1; a=rsa-sha256; c=relaxed/relaxed; d=\n\tmessagingengine.com; h=cc:date:from:message-id:subject:to\n\t:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=fm1; bh=OgKfMe\n\tb2Y9tE1TVykTcqQUGm11+u9BLmCxt1DDfx4O4=; b=llInxmLfLQVVzVXhzjELdQ\n\tbbm72m4UqYfSvI3z4eBTjZtJ7N8V1dI0KL/OFuUMDZsH6g7Vd9MOh7UOPU9lmfgI\n\tbpBE8zygqaqxGLptJLAC6rWqJ+dan5JFNYfxI8jq1rMnrrx45gY/FiIgWnfADylt\n\tO+frk5Bo8YEIZiLupCFWktzalPKTTtq0R5xSxUxJR4dhhFax0TGsmn0vzhClZmvY\n\tBeYJiUOFV0X/1I570FulvGAGMv4JjM/HNWLKZb4R+qRN13DNSQuZheqrl8HZ51qk\n\tLpTm7/0HaMkjy2lDvDrjjXBTLkoLDnoTRejCtdLDECdzp5aE/cxAXvzd5Dbh4NhQ\n\t=="],"X-ME-Sender":"","X-Sasl-enc":"XAJMdXutb/OF+0vpf8QojVymBc5bo71OzcGHCO3ZIQbV 1502781699","From":"Andrew Jeffery ","To":"linux-i2c@vger.kernel.org","Cc":"Andrew Jeffery , wsa@the-dreams.de,\n\tbrendanhiggins@google.com, benh@kernel.crashing.org,\n\tjoel@jms.id.au, openbmc@lists.ozlabs.org,\n\tlinux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org,\n\tryan_chen@aspeedtech.com","Subject":"[PATCH] i2c: aspeed: Retain delay/setup/hold values when\n\tconfiguring bus frequency","Date":"Tue, 15 Aug 2017 16:51:02 +0930","Message-Id":"<20170815072102.23067-1-andrew@aj.id.au>","X-Mailer":"git-send-email 2.11.0","Sender":"linux-i2c-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-i2c@vger.kernel.org"},"content":"In addition to the base, low and high clock configuration, the AC timing\nregister #1 on the AST2400 houses fields controlling:\n\n1. tBUF: Minimum delay between Stop and Start conditions\n2. tHDSTA: Hold time for the Start condition\n3. tACST: Setup time for Start and Stop conditions, and hold time for the\n Repeated Start condition\n\nThese values are defined in hardware on the AST2500 and therefore don't\nneed to be set.\n\naspeed_i2c_init_clk() was performing a direct write of the generated\nclock values rather than a read/mask/modify/update sequence to retain\ntBUF, tHDSTA and tACST, and therefore cleared the tBUF, tHDSTA and tACST\nfields on the AST2400. This resulted in a delay/setup/hold time of 1\nbase clock, which in some configurations is not enough for some devices\n(e.g. the MAX31785 fan controller, with an APB of 48MHz and a desired\nbus speed of 100kHz).\n\nSigned-off-by: Andrew Jeffery \n---\n drivers/i2c/busses/i2c-aspeed.c | 9 ++++++++-\n 1 file changed, 8 insertions(+), 1 deletion(-)","diff":"diff --git a/drivers/i2c/busses/i2c-aspeed.c b/drivers/i2c/busses/i2c-aspeed.c\nindex ee76e6dddc4b..284f8670dbeb 100644\n--- a/drivers/i2c/busses/i2c-aspeed.c\n+++ b/drivers/i2c/busses/i2c-aspeed.c\n@@ -53,6 +53,9 @@\n #define ASPEED_I2CD_MASTER_EN\t\t\t\tBIT(0)\n \n /* 0x04 : I2CD Clock and AC Timing Control Register #1 */\n+#define ASPEED_I2CD_TIME_TBUF_MASK\t\t\tGENMASK(31, 28)\n+#define ASPEED_I2CD_TIME_THDSTA_MASK\t\t\tGENMASK(27, 24)\n+#define ASPEED_I2CD_TIME_TACST_MASK\t\t\tGENMASK(23, 20)\n #define ASPEED_I2CD_TIME_SCL_HIGH_SHIFT\t\t\t16\n #define ASPEED_I2CD_TIME_SCL_HIGH_MASK\t\t\tGENMASK(19, 16)\n #define ASPEED_I2CD_TIME_SCL_LOW_SHIFT\t\t\t12\n@@ -744,7 +747,11 @@ static int aspeed_i2c_init_clk(struct aspeed_i2c_bus *bus)\n \tu32 divisor, clk_reg_val;\n \n \tdivisor = DIV_ROUND_UP(bus->parent_clk_frequency, bus->bus_frequency);\n-\tclk_reg_val = bus->get_clk_reg_val(divisor);\n+\tclk_reg_val = readl(bus->base + ASPEED_I2C_AC_TIMING_REG1);\n+\tclk_reg_val &= (ASPEED_I2CD_TIME_TBUF_MASK |\n+\t\t\tASPEED_I2CD_TIME_THDSTA_MASK |\n+\t\t\tASPEED_I2CD_TIME_TACST_MASK);\n+\tclk_reg_val |= bus->get_clk_reg_val(divisor);\n \twritel(clk_reg_val, bus->base + ASPEED_I2C_AC_TIMING_REG1);\n \twritel(ASPEED_NO_TIMEOUT_CTRL, bus->base + ASPEED_I2C_AC_TIMING_REG2);\n \n","prefixes":[]}