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\n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;","From":"Zhao Qiang ","To":"","Subject":"[PATCH v10 1/4] irqchip/qeic: move qeic driver from\n\tdrivers/soc/fsl/qe","Date":"Mon, 7 Aug 2017 11:07:13 +0800","Message-ID":"<1502075236-24078-2-git-send-email-qiang.zhao@nxp.com>","X-Mailer":"git-send-email 2.1.0.27.g96db324","In-Reply-To":"<1502075236-24078-1-git-send-email-qiang.zhao@nxp.com>","References":"<1502075236-24078-1-git-send-email-qiang.zhao@nxp.com>","X-EOPAttributedMessage":"0","X-Matching-Connectors":"131465498463583285;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); ()","X-Forefront-Antispam-Report":"CIP:192.88.168.50; IPV:NLI; CTRY:US; EFV:NLI;\n\tSFV:NSPM;\n\tSFS:(10009020)(6009001)(336005)(39860400002)(39450400003)(39840400002)(39380400002)(39850400002)(39400400002)(39410400002)(2980300002)(1109001)(1110001)(339900001)(199003)(189002)(97736004)(48376002)(626005)(8676002)(189998001)(50226002)(81166006)(81156014)(8936002)(5003940100001)(47776003)(86362001)(575784001)(104016004)(2906002)(68736007)(2950100002)(76176999)(50986999)(53936002)(6666003)(54906002)(356003)(106466001)(77096006)(2351001)(6916009)(110136004)(38730400002)(33646002)(36756003)(50466002)(8656003)(5660300001)(4326008)(305945005)(85426001)(105606002)(498600001)(2004002);\n\tDIR:OUT; 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BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(400006)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:CY1PR0301MB0906; ","X-Forefront-PRVS":"0392679D18","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"07 Aug 2017 03:24:06.1555\n\t(UTC)","X-MS-Exchange-CrossTenant-Id":"5afe0b00-7697-4969-b663-5eab37d5f47e","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"CY1PR0301MB0906","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"oss@buserror.net, Zhao Qiang ,\n\tlinuxppc-dev@lists.ozlabs.org, xiaobo.xie@nxp.com,\n\tlinux-kernel@vger.kernel.org","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"},"content":"move the driver from drivers/soc/fsl/qe to drivers/irqchip,\nmerge qe_ic.h and qe_ic.c into irq-qeic.c.\n\nSigned-off-by: Zhao Qiang \n---\n MAINTAINERS | 6 ++\n drivers/irqchip/Makefile | 1 +\n drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} | 95 ++++++++++++++++++-\n drivers/soc/fsl/qe/Makefile | 2 +-\n drivers/soc/fsl/qe/qe_ic.h | 103 ---------------------\n 5 files changed, 100 insertions(+), 107 deletions(-)\n rename drivers/{soc/fsl/qe/qe_ic.c => irqchip/irq-qeic.c} (85%)\n delete mode 100644 drivers/soc/fsl/qe/qe_ic.h","diff":"diff --git a/MAINTAINERS b/MAINTAINERS\nindex 567343b..1288329 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -5462,6 +5462,12 @@ F:\tdrivers/soc/fsl/qe/\n F:\tinclude/soc/fsl/*qe*.h\n F:\tinclude/soc/fsl/*ucc*.h\n \n+FREESCALE QEIC DRIVERS\n+M:\tQiang Zhao \n+L:\tlinux-kernel@vger.kernel.org\n+S:\tMaintained\n+F:\tdrivers/irqchip/irq-qeic.c\n+\n FREESCALE QUICC ENGINE UCC ETHERNET DRIVER\n M:\tLi Yang \n L:\tnetdev@vger.kernel.org\ndiff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile\nindex e88d856..b8eae87 100644\n--- a/drivers/irqchip/Makefile\n+++ b/drivers/irqchip/Makefile\n@@ -78,3 +78,4 @@ obj-$(CONFIG_EZNPS_GIC)\t\t\t+= irq-eznps.o\n obj-$(CONFIG_ARCH_ASPEED)\t\t+= irq-aspeed-vic.o irq-aspeed-i2c-ic.o\n obj-$(CONFIG_STM32_EXTI) \t\t+= irq-stm32-exti.o\n obj-$(CONFIG_QCOM_IRQ_COMBINER)\t\t+= qcom-irq-combiner.o\n+obj-$(CONFIG_QUICC_ENGINE)\t\t+= irq-qeic.o\ndiff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/irqchip/irq-qeic.c\nsimilarity index 85%\nrename from drivers/soc/fsl/qe/qe_ic.c\nrename to drivers/irqchip/irq-qeic.c\nindex ec2ca86..9b4660c 100644\n--- a/drivers/soc/fsl/qe/qe_ic.c\n+++ b/drivers/irqchip/irq-qeic.c\n@@ -1,7 +1,7 @@\n /*\n- * arch/powerpc/sysdev/qe_lib/qe_ic.c\n+ * drivers/irqchip/irq-qeic.c\n *\n- * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.\n+ * Copyright (C) 2016 Freescale Semiconductor, Inc. All rights reserved.\n *\n * Author: Li Yang \n * Based on code from Shlomi Gridish \n@@ -30,7 +30,96 @@\n #include \n #include \n \n-#include \"qe_ic.h\"\n+#define NR_QE_IC_INTS\t\t64\n+\n+/* QE IC registers offset */\n+#define QEIC_CICR\t\t0x00\n+#define QEIC_CIVEC\t\t0x04\n+#define QEIC_CRIPNR\t\t0x08\n+#define QEIC_CIPNR\t\t0x0c\n+#define QEIC_CIPXCC\t\t0x10\n+#define QEIC_CIPYCC\t\t0x14\n+#define QEIC_CIPWCC\t\t0x18\n+#define QEIC_CIPZCC\t\t0x1c\n+#define QEIC_CIMR\t\t0x20\n+#define QEIC_CRIMR\t\t0x24\n+#define QEIC_CICNR\t\t0x28\n+#define QEIC_CIPRTA\t\t0x30\n+#define QEIC_CIPRTB\t\t0x34\n+#define QEIC_CRICR\t\t0x3c\n+#define QEIC_CHIVEC\t\t0x60\n+\n+/* Interrupt priority registers */\n+#define CIPCC_SHIFT_PRI0\t29\n+#define CIPCC_SHIFT_PRI1\t26\n+#define CIPCC_SHIFT_PRI2\t23\n+#define CIPCC_SHIFT_PRI3\t20\n+#define CIPCC_SHIFT_PRI4\t13\n+#define CIPCC_SHIFT_PRI5\t10\n+#define CIPCC_SHIFT_PRI6\t7\n+#define CIPCC_SHIFT_PRI7\t4\n+\n+/* CICR priority modes */\n+#define CICR_GWCC\t\t0x00040000\n+#define CICR_GXCC\t\t0x00020000\n+#define CICR_GYCC\t\t0x00010000\n+#define CICR_GZCC\t\t0x00080000\n+#define CICR_GRTA\t\t0x00200000\n+#define CICR_GRTB\t\t0x00400000\n+#define CICR_HPIT_SHIFT\t\t8\n+#define CICR_HPIT_MASK\t\t0x00000300\n+#define CICR_HP_SHIFT\t\t24\n+#define CICR_HP_MASK\t\t0x3f000000\n+\n+/* CICNR */\n+#define CICNR_WCC1T_SHIFT\t20\n+#define CICNR_ZCC1T_SHIFT\t28\n+#define CICNR_YCC1T_SHIFT\t12\n+#define CICNR_XCC1T_SHIFT\t4\n+\n+/* CRICR */\n+#define CRICR_RTA1T_SHIFT\t20\n+#define CRICR_RTB1T_SHIFT\t28\n+\n+/* Signal indicator */\n+#define SIGNAL_MASK\t\t3\n+#define SIGNAL_HIGH\t\t2\n+#define SIGNAL_LOW\t\t0\n+\n+struct qe_ic {\n+\t/* Control registers offset */\n+\tu32 __iomem *regs;\n+\n+\t/* The remapper for this QEIC */\n+\tstruct irq_domain *irqhost;\n+\n+\t/* The \"linux\" controller struct */\n+\tstruct irq_chip hc_irq;\n+\n+\t/* VIRQ numbers of QE high/low irqs */\n+\tunsigned int virq_high;\n+\tunsigned int virq_low;\n+};\n+\n+/*\n+ * QE interrupt controller internal structure\n+ */\n+struct qe_ic_info {\n+\t/* location of this source at the QIMR register. */\n+\tu32\tmask;\n+\n+\t/* Mask register offset */\n+\tu32\tmask_reg;\n+\n+\t/*\n+\t * for grouped interrupts sources - the interrupt\n+\t * code as appears at the group priority register\n+\t */\n+\tu8\tpri_code;\n+\n+\t/* Group priority register offset */\n+\tu32\tpri_reg;\n+};\n \n static DEFINE_RAW_SPINLOCK(qe_ic_lock);\n \ndiff --git a/drivers/soc/fsl/qe/Makefile b/drivers/soc/fsl/qe/Makefile\nindex 2031d38..51e4726 100644\n--- a/drivers/soc/fsl/qe/Makefile\n+++ b/drivers/soc/fsl/qe/Makefile\n@@ -1,7 +1,7 @@\n #\n # Makefile for the linux ppc-specific parts of QE\n #\n-obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_common.o qe_ic.o qe_io.o\n+obj-$(CONFIG_QUICC_ENGINE)+= qe.o qe_common.o qe_io.o\n obj-$(CONFIG_CPM)\t+= qe_common.o\n obj-$(CONFIG_UCC)\t+= ucc.o\n obj-$(CONFIG_UCC_SLOW)\t+= ucc_slow.o\ndiff --git a/drivers/soc/fsl/qe/qe_ic.h b/drivers/soc/fsl/qe/qe_ic.h\ndeleted file mode 100644\nindex 926a2ed..0000000\n--- a/drivers/soc/fsl/qe/qe_ic.h\n+++ /dev/null\n@@ -1,103 +0,0 @@\n-/*\n- * drivers/soc/fsl/qe/qe_ic.h\n- *\n- * QUICC ENGINE Interrupt Controller Header\n- *\n- * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.\n- *\n- * Author: Li Yang \n- * Based on code from Shlomi Gridish \n- *\n- * This program is free software; you can redistribute it and/or modify it\n- * under the terms of the GNU General Public License as published by the\n- * Free Software Foundation; either version 2 of the License, or (at your\n- * option) any later version.\n- */\n-#ifndef _POWERPC_SYSDEV_QE_IC_H\n-#define _POWERPC_SYSDEV_QE_IC_H\n-\n-#include \n-\n-#define NR_QE_IC_INTS\t\t64\n-\n-/* QE IC registers offset */\n-#define QEIC_CICR\t\t0x00\n-#define QEIC_CIVEC\t\t0x04\n-#define QEIC_CRIPNR\t\t0x08\n-#define QEIC_CIPNR\t\t0x0c\n-#define QEIC_CIPXCC\t\t0x10\n-#define QEIC_CIPYCC\t\t0x14\n-#define QEIC_CIPWCC\t\t0x18\n-#define QEIC_CIPZCC\t\t0x1c\n-#define QEIC_CIMR\t\t0x20\n-#define QEIC_CRIMR\t\t0x24\n-#define QEIC_CICNR\t\t0x28\n-#define QEIC_CIPRTA\t\t0x30\n-#define QEIC_CIPRTB\t\t0x34\n-#define QEIC_CRICR\t\t0x3c\n-#define QEIC_CHIVEC\t\t0x60\n-\n-/* Interrupt priority registers */\n-#define CIPCC_SHIFT_PRI0\t29\n-#define CIPCC_SHIFT_PRI1\t26\n-#define CIPCC_SHIFT_PRI2\t23\n-#define CIPCC_SHIFT_PRI3\t20\n-#define CIPCC_SHIFT_PRI4\t13\n-#define CIPCC_SHIFT_PRI5\t10\n-#define CIPCC_SHIFT_PRI6\t7\n-#define CIPCC_SHIFT_PRI7\t4\n-\n-/* CICR priority modes */\n-#define CICR_GWCC\t\t0x00040000\n-#define CICR_GXCC\t\t0x00020000\n-#define CICR_GYCC\t\t0x00010000\n-#define CICR_GZCC\t\t0x00080000\n-#define CICR_GRTA\t\t0x00200000\n-#define CICR_GRTB\t\t0x00400000\n-#define CICR_HPIT_SHIFT\t\t8\n-#define CICR_HPIT_MASK\t\t0x00000300\n-#define CICR_HP_SHIFT\t\t24\n-#define CICR_HP_MASK\t\t0x3f000000\n-\n-/* CICNR */\n-#define CICNR_WCC1T_SHIFT\t20\n-#define CICNR_ZCC1T_SHIFT\t28\n-#define CICNR_YCC1T_SHIFT\t12\n-#define CICNR_XCC1T_SHIFT\t4\n-\n-/* CRICR */\n-#define CRICR_RTA1T_SHIFT\t20\n-#define CRICR_RTB1T_SHIFT\t28\n-\n-/* Signal indicator */\n-#define SIGNAL_MASK\t\t3\n-#define SIGNAL_HIGH\t\t2\n-#define SIGNAL_LOW\t\t0\n-\n-struct qe_ic {\n-\t/* Control registers offset */\n-\tvolatile u32 __iomem *regs;\n-\n-\t/* The remapper for this QEIC */\n-\tstruct irq_domain *irqhost;\n-\n-\t/* The \"linux\" controller struct */\n-\tstruct irq_chip hc_irq;\n-\n-\t/* VIRQ numbers of QE high/low irqs */\n-\tunsigned int virq_high;\n-\tunsigned int virq_low;\n-};\n-\n-/*\n- * QE interrupt controller internal structure\n- */\n-struct qe_ic_info {\n-\tu32\tmask;\t /* location of this source at the QIMR register. */\n-\tu32\tmask_reg; /* Mask register offset */\n-\tu8\tpri_code; /* for grouped interrupts sources - the interrupt\n-\t\t\t code as appears at the group priority register */\n-\tu32\tpri_reg; /* Group priority register offset */\n-};\n-\n-#endif /* _POWERPC_SYSDEV_QE_IC_H */\n","prefixes":["v10","1/4"]}