{"id":783379,"url":"http://patchwork.ozlabs.org/api/patches/783379/?format=json","web_url":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1499074673-30576-2-git-send-email-anju@linux.vnet.ibm.com/","project":{"id":2,"url":"http://patchwork.ozlabs.org/api/projects/2/?format=json","name":"Linux PPC development","link_name":"linuxppc-dev","list_id":"linuxppc-dev.lists.ozlabs.org","list_email":"linuxppc-dev@lists.ozlabs.org","web_url":"https://github.com/linuxppc/wiki/wiki","scm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git","webscm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/","list_archive_url":"https://lore.kernel.org/linuxppc-dev/","list_archive_url_format":"https://lore.kernel.org/linuxppc-dev/{}/","commit_url_format":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}"},"msgid":"<1499074673-30576-2-git-send-email-anju@linux.vnet.ibm.com>","list_archive_url":"https://lore.kernel.org/linuxppc-dev/1499074673-30576-2-git-send-email-anju@linux.vnet.ibm.com/","date":"2017-07-03T09:37:47","name":"[v12,01/10] powerpc/powernv: Data structure and macros definitions for IMC","commit_ref":null,"pull_url":null,"state":"superseded","archived":true,"hash":"4bcbe8cc95e2fd0895ad54cb42d4010a356d84a8","submitter":{"id":67491,"url":"http://patchwork.ozlabs.org/api/people/67491/?format=json","name":"Anju T Sudhakar","email":"anju@linux.vnet.ibm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1499074673-30576-2-git-send-email-anju@linux.vnet.ibm.com/mbox/","series":[],"comments":"http://patchwork.ozlabs.org/api/patches/783379/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/783379/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3x1MZZ66cDz9s0g\n\tfor ;\n\tMon, 3 Jul 2017 19:40:54 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3x1MZZ5MBKzDrC0\n\tfor ;\n\tMon, 3 Jul 2017 19:40:54 +1000 (AEST)","from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n\t[148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3x1MWP3LHlzDr44\n\tfor ;\n\tMon, 3 Jul 2017 19:38:09 +1000 (AEST)","from pps.filterd (m0098417.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id\n\tv639XiPI085685\n\tfor ; Mon, 3 Jul 2017 05:38:06 -0400","from e23smtp08.au.ibm.com (e23smtp08.au.ibm.com [202.81.31.141])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2bem6g9bcb-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor ; Mon, 03 Jul 2017 05:38:06 -0400","from localhost\n\tby e23smtp08.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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Violators will be prosecuted; \n\tMon, 3 Jul 2017 19:38:02 +1000","from d23av03.au.ibm.com (d23av03.au.ibm.com [9.190.234.97])\n\tby d23relay10.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id\n\tv639c1Jr6947110\n\tfor ; Mon, 3 Jul 2017 19:38:01 +1000","from d23av03.au.ibm.com (localhost [127.0.0.1])\n\tby d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id\n\tv639bqi0027577\n\tfor ; Mon, 3 Jul 2017 19:37:53 +1000","from xenial-xerus.in.ibm.com (xenial-xerus.in.ibm.com [9.124.35.20]\n\t(may be forged))\n\tby d23av03.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id\n\tv639bkFO027271; Mon, 3 Jul 2017 19:37:49 +1000"],"From":"Anju T Sudhakar ","To":"mpe@ellerman.id.au","Subject":"[PATCH v12 01/10] powerpc/powernv: Data structure and macros\n\tdefinitions for IMC","Date":"Mon, 3 Jul 2017 15:07:47 +0530","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1499074673-30576-1-git-send-email-anju@linux.vnet.ibm.com>","References":"<1499074673-30576-1-git-send-email-anju@linux.vnet.ibm.com>","X-TM-AS-MML":"disable","x-cbid":"17070309-0048-0000-0000-0000024EFA25","X-IBM-AV-DETECTION":"SAVI=unused REMOTE=unused XFE=unused","x-cbparentid":"17070309-0049-0000-0000-000048002566","Message-Id":"<1499074673-30576-2-git-send-email-anju@linux.vnet.ibm.com>","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-07-03_06:, , signatures=0","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=1\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000\n\tdefinitions=main-1707030160","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"stewart@linux.vnet.ibm.com, ego@linux.vnet.ibm.com, mikey@neuling.org,\n\tmaddy@linux.vnet.ibm.com, hemant@linux.vnet.ibm.com,\n\tlinux-kernel@vger.kernel.org, eranian@google.com,\n\tanju@linux.vnet.ibm.com, anton@samba.org, sukadev@linux.vnet.ibm.com,\n\tlinuxppc-dev@lists.ozlabs.org, dja@axtens.net","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"},"content":"From: Madhavan Srinivasan \n\nCreate a new header file to add the data structures and\nmacros needed for In-Memory Collection (IMC) counter support.\n\nSigned-off-by: Anju T Sudhakar \nSigned-off-by: Hemant Kumar \nSigned-off-by: Madhavan Srinivasan \n---\n arch/powerpc/include/asm/imc-pmu.h | 99 ++++++++++++++++++++++++++++++++++++++\n 1 file changed, 99 insertions(+)\n create mode 100644 arch/powerpc/include/asm/imc-pmu.h","diff":"diff --git a/arch/powerpc/include/asm/imc-pmu.h b/arch/powerpc/include/asm/imc-pmu.h\nnew file mode 100644\nindex 000000000000..ffaea0b9c13e\n--- /dev/null\n+++ b/arch/powerpc/include/asm/imc-pmu.h\n@@ -0,0 +1,99 @@\n+#ifndef PPC_POWERNV_IMC_PMU_DEF_H\n+#define PPC_POWERNV_IMC_PMU_DEF_H\n+\n+/*\n+ * IMC Nest Performance Monitor counter support.\n+ *\n+ * Copyright (C) 2017 Madhavan Srinivasan, IBM Corporation.\n+ * (C) 2017 Anju T Sudhakar, IBM Corporation.\n+ * (C) 2017 Hemant K Shaw, IBM Corporation.\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * as published by the Free Software Foundation; either version\n+ * 2 of the License, or later version.\n+ */\n+\n+#include \n+#include \n+#include \n+#include \n+#include \n+\n+/*\n+ * For static allocation of some of the structures.\n+ */\n+#define IMC_MAX_PMUS\t\t\t32\n+\n+/*\n+ * This macro is used for memory buffer allocation of\n+ * event names and event string\n+ */\n+#define IMC_MAX_NAME_VAL_LEN\t\t96\n+\n+/*\n+ * Currently Microcode supports a max of 256KB of counter memory\n+ * in the reserved memory region. Max pages to mmap (considering 4K PAGESIZE).\n+ */\n+#define IMC_MAX_PAGES\t\t\t64\n+\n+/*\n+ *Compatbility macros for IMC devices\n+ */\n+#define IMC_DTB_COMPAT\t\t\t\"ibm,opal-in-memory-counters\"\n+#define IMC_DTB_UNIT_COMPAT\t\t\"ibm,imc-counters\"\n+\n+/*\n+ * Structure to hold memory address information for imc units.\n+ */\n+struct imc_mem_info {\n+\tu32 id;\n+\tu64 *vbase[IMC_MAX_PAGES];\n+};\n+\n+/*\n+ * Place holder for nest pmu events and values.\n+ */\n+struct imc_events {\n+\tchar *ev_name;\n+\tchar *ev_value;\n+};\n+\n+#define IMC_FORMAT_ATTR\t\t0\n+#define IMC_CPUMASK_ATTR\t1\n+#define IMC_EVENT_ATTR\t\t2\n+#define IMC_NULL_ATTR\t\t3\n+\n+/*\n+ * Device tree parser code detects IMC pmu support and\n+ * registers new IMC pmus. This structure will hold the\n+ * pmu functions, events, counter memory information\n+ * and attrs for each imc pmu and will be referenced at\n+ * the time of pmu registration.\n+ */\n+struct imc_pmu {\n+\tstruct pmu pmu;\n+\tint domain;\n+\t/*\n+\t * flag to notify whether the memory is mmaped\n+\t * or allocated by kernel.\n+\t */\n+\tint imc_counter_mmaped;\n+\tstruct imc_mem_info *mem_info;\n+\tstruct imc_events *events;\n+\tu32 counter_mem_size;\n+\t/*\n+\t * Attribute groups for the PMU. Slot 0 used for\n+\t * format attribute, slot 1 used for cpusmask attribute,\n+\t * slot 2 used for event attribute. Slot 3 keep as\n+\t * NULL.\n+\t */\n+\tconst struct attribute_group *attr_groups[4];\n+};\n+\n+/*\n+ * Domains for IMC PMUs\n+ */\n+#define IMC_DOMAIN_NEST\t\t1\n+\n+#endif /* PPC_POWERNV_IMC_PMU_DEF_H */\n","prefixes":["v12","01/10"]}