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BCL:0; PCL:0;\n\tRULEID:(22001)(201703131430075)(201703131517081); SRVR:BY2PR03MB173; ","X-Microsoft-Antispam-PRVS":"","X-Exchange-Antispam-Report-Test":"UriScan:(185117386973197);","X-Exchange-Antispam-Report-CFA-Test":"BCL:0; PCL:0;\n\tRULEID:(6095135)(601004)(2401047)(13024025)(13018025)(13023025)(8121501046)(5005006)(13017025)(13015025)(10201501046)(3002001)(93006095)(93001095)(6055026)(6096035)(201703131430075)(201703131441075)(201703131448075)(201703131433075)(201703161259150)(20161123565025)(20161123561025)(20161123556025)(20161123563025)(20161123559100);\n\tSRVR:BY2PR03MB173; BCL:0; PCL:0; RULEID:(400006); SRVR:BY2PR03MB173; ","X-Forefront-PRVS":"0310C78181","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"17 May 2017 12:20:50.8004\n\t(UTC)","X-MS-Exchange-CrossTenant-Id":"5afe0b00-7697-4969-b663-5eab37d5f47e","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"BY2PR03MB173","Cc":"\"yinbo.zhu\" ","Subject":"[U-Boot] [PATCH 13/14] drivers:usb:xhci:fsl: Implement Erratum\n\tA-010151 for FSL USB3 controller","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"From: Sriram Dash \n\nCurrently the controller by default enables the Receive Detect feature in P3\nmode in USB 3.0 PHY. However, USB 3.0 PHY does not reliably support receive\ndetection in P3 mode.\nEnabling the USB3 controller to configure USB in P2 mode whenever the Receive\nDetect feature is required.\n\nSigned-off-by: Sriram Dash \nSigned-off-by: Rajesh Bhagat \nSigned-off-by: yinbo.zhu \n---\n drivers/usb/host/xhci-dwc3.c | 5 +++++\n drivers/usb/host/xhci-fsl.c | 7 +++++++\n include/linux/usb/dwc3.h | 1 +\n 3 files changed, 13 insertions(+)","diff":"diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c\nindex 33961cd..adbd9b5 100644\n--- a/drivers/usb/host/xhci-dwc3.c\n+++ b/drivers/usb/host/xhci-dwc3.c\n@@ -97,3 +97,8 @@ void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)\n \tsetbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |\n \t\t\tGFLADJ_30MHZ(val));\n }\n+\n+void dwc3_set_rxdetect_power_mode(struct dwc3 *dwc3_reg, u32 val)\n+{\n+\tsetbits_le32(&dwc3_reg->g_usb3pipectl[0], val);\n+}\ndiff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c\nindex 3a16624..e8e90fa 100644\n--- a/drivers/usb/host/xhci-fsl.c\n+++ b/drivers/usb/host/xhci-fsl.c\n@@ -86,6 +86,13 @@ static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)\n \tfsl_xhci_set_beat_burst_length(fsl_xhci->dwc3_reg);\n \n \t/*\n+\t* A-010151: USB controller to configure USB in P2 mode\n+\t* whenever the Receive Detect feature is required\n+\t*/\n+\tdwc3_set_rxdetect_power_mode(fsl_xhci->dwc3_reg,\n+\t\t\t\t DWC3_GUSB3PIPECTL_DISRXDETP3);\n+\n+\t/*\n \t * A-010151: The dwc3 phy TSMC 28-nm HPM 0.9/1.8 V does not\n \t * reliably support Rx Detect in P3 mode(P3 is the default\n \t * setting). Therefore, some USB3.0 devices may not be detected\ndiff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h\nindex c1b23b2..873b4db 100644\n--- a/include/linux/usb/dwc3.h\n+++ b/include/linux/usb/dwc3.h\n@@ -220,5 +220,6 @@ void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode);\n void dwc3_core_soft_reset(struct dwc3 *dwc3_reg);\n int dwc3_core_init(struct dwc3 *dwc3_reg);\n void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val);\n+void dwc3_set_rxdetect_power_mode(struct dwc3 *dwc3_reg, u32 val);\n #endif\n #endif /* __DWC3_H_ */\n","prefixes":["U-Boot","13/14"]}