{"id":751945,"url":"http://patchwork.ozlabs.org/api/patches/751945/?format=json","web_url":"http://patchwork.ozlabs.org/project/skiboot/patch/20170418191220.3166-6-npiggin@gmail.com/","project":{"id":44,"url":"http://patchwork.ozlabs.org/api/projects/44/?format=json","name":"skiboot firmware development","link_name":"skiboot","list_id":"skiboot.lists.ozlabs.org","list_email":"skiboot@lists.ozlabs.org","web_url":"http://github.com/open-power/skiboot","scm_url":"http://github.com/open-power/skiboot","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170418191220.3166-6-npiggin@gmail.com>","list_archive_url":null,"date":"2017-04-18T19:12:20","name":"[OPAL] cpu-features: add base and POWER8, POWER9 /cpus/ibm, powerpc-cpu-features dt","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":false,"hash":"8a2c703386783f2c450cb47f83591d578c993583","submitter":{"id":69518,"url":"http://patchwork.ozlabs.org/api/people/69518/?format=json","name":"Nicholas Piggin","email":"npiggin@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/skiboot/patch/20170418191220.3166-6-npiggin@gmail.com/mbox/","series":[],"comments":"http://patchwork.ozlabs.org/api/patches/751945/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/751945/checks/","tags":{},"related":[],"headers":{"Return-Path":"<skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>","X-Original-To":["incoming@patchwork.ozlabs.org","skiboot@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","skiboot@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3w6w5q0Cvrz9s2x\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 19 Apr 2017 05:23:27 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3w6w5p6RgczDq9d\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 19 Apr 2017 05:23:26 +1000 (AEST)","from mail-pg0-x241.google.com (mail-pg0-x241.google.com\n\t[IPv6:2607:f8b0:400e:c05::241])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3w6vsj1GY4zDq9H;\n\tWed, 19 Apr 2017 05:12:57 +1000 (AEST)","by mail-pg0-x241.google.com with SMTP id o123so348417pga.1;\n\tTue, 18 Apr 2017 12:12:57 -0700 (PDT)","from roar.local0.net (14-202-189-126.tpgi.com.au. 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"Skiboot\"\n\t<skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>"},"content":"Since last time:\n- Added binding specification and design overview documentation.\n- Renamed the dt node to ibm,powerpc specific.\n- Moved dependency building pass into its own function.\n\n---\n core/Makefile.inc                                  |   2 +-\n core/cpufeatures.c                                 | 896 +++++++++++++++++++++\n core/device.c                                      |   7 +\n core/init.c                                        |   1 +\n .../ibm,powerpc-cpu-features/binding.txt           | 226 ++++++\n .../ibm,powerpc-cpu-features/design.txt            | 157 ++++\n include/device.h                                   |   1 +\n include/skiboot.h                                  |   5 +\n 8 files changed, 1294 insertions(+), 1 deletion(-)\n create mode 100644 core/cpufeatures.c\n create mode 100644 doc/device-tree/ibm,powerpc-cpu-features/binding.txt\n create mode 100644 doc/device-tree/ibm,powerpc-cpu-features/design.txt","diff":"diff --git a/core/Makefile.inc b/core/Makefile.inc\nindex b09c30c0..7c247836 100644\n--- a/core/Makefile.inc\n+++ b/core/Makefile.inc\n@@ -8,7 +8,7 @@ CORE_OBJS += pci-opal.o fast-reboot.o device.o exceptions.o trace.o affinity.o\n CORE_OBJS += vpd.o hostservices.o platform.o nvram.o nvram-format.o hmi.o\n CORE_OBJS += console-log.o ipmi.o time-utils.o pel.o pool.o errorlog.o\n CORE_OBJS += timer.o i2c.o rtc.o flash.o sensor.o ipmi-opal.o\n-CORE_OBJS += flash-subpartition.o bitmap.o buddy.o pci-quirk.o\n+CORE_OBJS += flash-subpartition.o bitmap.o buddy.o pci-quirk.o cpufeatures.o\n \n ifeq ($(SKIBOOT_GCOV),1)\n CORE_OBJS += gcov-profiling.o\ndiff --git a/core/cpufeatures.c b/core/cpufeatures.c\nnew file mode 100644\nindex 00000000..1acedc1d\n--- /dev/null\n+++ b/core/cpufeatures.c\n@@ -0,0 +1,896 @@\n+/* Copyright 2017 IBM Corp.\n+ *\n+ * Licensed under the Apache License, Version 2.0 (the \"License\");\n+ * you may not use this file except in compliance with the License.\n+ * You may obtain a copy of the License at\n+ *\n+ * \thttp://www.apache.org/licenses/LICENSE-2.0\n+ *\n+ * Unless required by applicable law or agreed to in writing, software\n+ * distributed under the License is distributed on an \"AS IS\" BASIS,\n+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or\n+ * implied.\n+ * See the License for the specific language governing permissions and\n+ * limitations under the License.\n+ */\n+\n+/*\n+ * This file deals with setting up the /cpus/features device tree\n+ * by discovering CPU hardware and populating feature nodes.\n+ */\n+\n+#include <skiboot.h>\n+#include <cpu.h>\n+#include <ccan/str/str.h>\n+#include <device.h>\n+\n+#ifdef DEBUG\n+#define DBG(fmt, a...)\tprlog(PR_DEBUG, \"CPUFT: \" fmt, ##a)\n+#else\n+#define DBG(fmt, a...)\n+#endif\n+\n+/* Device-tree visible constants follow */\n+#define ISA_V2_07B\t2070\n+#define ISA_V3_0B\t3000\n+\n+#define USABLE_PR\t\t(1U << 0)\n+#define USABLE_OS\t\t(1U << 1)\n+#define USABLE_HV\t\t(1U << 2)\n+\n+#define HV_SUPPORT_HFSCR\t(1U << 0)\n+#define OS_SUPPORT_FSCR\t\t(1U << 0)\n+\n+/* Following are definitions for the match tables, not the DT binding itself */\n+#define ISA_BASE\t0\n+\n+#define HV_NONE\t\t0\n+#define HV_CUSTOM\t1\n+#define HV_HFSCR\t2\n+\n+#define OS_NONE\t\t0\n+#define OS_CUSTOM\t1\n+#define OS_FSCR\t\t2\n+\n+/* CPU bitmasks for match table */\n+#define CPU_P8_DD1\t(1U << 0)\n+#define CPU_P8_DD2\t(1U << 1)\n+#define CPU_P9_DD1\t(1U << 2)\n+#define CPU_P9_DD2\t(1U << 3)\n+\n+#define CPU_P8\t\t(CPU_P8_DD1|CPU_P8_DD2)\n+#define CPU_P9\t\t(CPU_P9_DD1|CPU_P9_DD2)\n+#define CPU_ALL\t\t(CPU_P8|CPU_P9)\n+\n+struct cpu_feature {\n+\tconst char *name;\n+\tuint32_t cpus_supported;\n+\tuint32_t isa;\n+\tuint32_t usable_privilege;\n+\tuint32_t hv_support;\n+\tuint32_t os_support;\n+\tuint32_t hfscr_bit_nr;\n+\tuint32_t fscr_bit_nr;\n+\tuint32_t hwcap_bit_nr;\n+\tconst char *dependencies_names; /* space-delimited names */\n+};\n+\n+/*\n+ * The base (or NULL) cpu feature set is the CPU features available\n+ * when no child nodes of the /cpus/ibm,powerpc-cpu-features node exist. The\n+ * base feature set is POWER8 (ISAv2.07B), less features that are listed\n+ * explicitly.\n+ *\n+ * XXX: currently, the feature dependencies are not necessarily captured\n+ * exactly or completely. This is somewhat acceptable because all\n+ * implementations must be aware of all these features.\n+ */\n+static const struct cpu_feature cpu_features_table[] = {\n+\t/*\n+\t * Big endian as in ISAv2.07B, MSR_LE=0\n+\t */\n+\t{ \"big-endian\",\n+\tCPU_ALL,\n+\tISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * Little endian as in ISAv2.07B, MSR_LE=1.\n+\t *\n+\t * When both big and little endian are defined, there is an LPCR ILE\n+\t * bit and implementation specific way to switch HILE mode, MSR_SLE,\n+\t * etc.\n+\t */\n+\t{ \"little-endian\",\n+\tCPU_ALL,\n+\tISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * MSR_HV=1 mode as in ISAv2.07B (i.e., hypervisor privileged\n+\t * instructions and registers).\n+\t */\n+\t{ \"hypervisor\",\n+\tCPU_ALL,\n+\tISA_BASE, USABLE_HV,\n+\tHV_CUSTOM, OS_NONE,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv2.07B interrupt vectors, registers, and control registers\n+\t * (e.g., AIL, ILE, HV, etc LPCR bits).\n+\t *\n+\t * This does not necessarily specify all possible interrupt types.\n+\t * floating-point, for example requires some ways to handle floating\n+\t * point exceptions, but the low level details of interrupt handler\n+\t * is not a dependency there. There will always be *some* interrupt\n+\t * handler, (and some way to provide memory magagement, etc.).\n+\t */\n+\t{ \"interrupt-facilities\",\n+\tCPU_ALL,\n+\tISA_BASE, USABLE_HV|USABLE_OS,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t{ \"smt\",\n+\tCPU_ALL,\n+\tISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\t-1, -1, 14,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv2.07B Program Priority Registers (PPR)\n+\t * PPR and associated control registers (e.g. RPR, PSPB),\n+\t * priority \"or\" instructions, etc.\n+\t */\n+\t{ \"program-priority-register\",\n+\tCPU_ALL,\n+\tISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_NONE, OS_NONE,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv2.07B Book3S Chapter 5.7.9.1. Virtual Page Class Key Protecion\n+\t * AMR, IAMR, AMOR, UAMOR, etc registers and MMU key bits.\n+\t */\n+\t{ \"virtual-page-class-key-protection\",\n+\tCPU_ALL,\n+\tISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv2.07B SAO storage control attribute\n+\t */\n+\t{ \"strong-access-ordering\",\n+\tCPU_ALL & ~CPU_P9_DD1,\n+\tISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv2.07B no-execute storage control attribute\n+\t */\n+\t{ \"no-execute\",\n+\tCPU_ALL,\n+\tISA_BASE, USABLE_HV|USABLE_OS,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * Cache inhibited attribute supported on large pages.\n+\t */\n+\t{ \"cache-inhibited-large-page\",\n+\tCPU_ALL,\n+\tISA_BASE, USABLE_HV|USABLE_OS,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv2.07B Book3S Chapter 8. Debug Facilities\n+\t * CIEA, CIABR, DEAW, MEte, trace interrupt, etc.\n+\t * Except CFAR, branch tracing.\n+\t */\n+\t{ \"debug-facilities\",\n+\tCPU_ALL,\n+\tISA_BASE, USABLE_HV|USABLE_OS,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv2.07B CFAR\n+\t */\n+\t{ \"come-from-address-register\",\n+\tCPU_ALL,\n+\tISA_BASE, USABLE_HV|USABLE_OS,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\t-1, -1, -1,\n+\t\"debug-facilities\", },\n+\n+\t/*\n+\t * ISAv2.07B Branch tracing (optional in ISA)\n+\t */\n+\t{ \"branch-tracing\",\n+\tCPU_ALL,\n+\tISA_BASE, USABLE_HV|USABLE_OS,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\t-1, -1, -1,\n+\t\"debug-facilities\", },\n+\n+\t/*\n+\t * ISAv2.07B Floating-point Facility\n+\t */\n+\t{ \"floating-point\",\n+\tCPU_ALL,\n+\tISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\tPPC_BITLSHIFT(63), -1, 27,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv2.07B Vector Facility (VMX)\n+\t */\n+\t{ \"vector\",\n+\tCPU_ALL,\n+\tISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\tPPC_BITLSHIFT(62), -1, 28,\n+\t\"floating-point\", },\n+\n+\t/*\n+\t * ISAv2.07B Vector-scalar Facility (VSX)\n+\t */\n+\t{ \"vector-scalar\",\n+\tCPU_ALL,\n+\tISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\t-1, -1, 7,\n+\t\"vector\", },\n+\n+\t{ \"vector-crypto\",\n+\tCPU_ALL,\n+\tISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_NONE, OS_NONE,\n+\t-1, -1, 57,\n+\t\"vector\", },\n+\n+\t/*\n+\t * ISAv2.07B Binary Coded Decimal (BCD)\n+\t * BCD fixed point instructions\n+\t */\n+\t{ \"decimal-integer\",\n+\tCPU_ALL,\n+\tISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_NONE, OS_NONE,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv2.07B Decimal floating-point Facility (DFP)\n+\t */\n+\t{ \"decimal-floating-point\",\n+\tCPU_ALL,\n+\tISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_NONE, OS_NONE,\n+\t-1, -1, 10,\n+\t\"floating-point\", },\n+\n+\t/*\n+\t * ISAv2.07B\n+\t * DSCR, default data prefetch LPCR, etc\n+\t */\n+\t{ \"data-stream-control-register\",\n+\tCPU_ALL,\n+\tISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\tPPC_BITLSHIFT(61), PPC_BITLSHIFT(61), 61,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv2.07B Branch History Rolling Buffer (BHRB)\n+\t */\n+\t{ \"branch-history-rolling-buffer\",\n+\tCPU_ALL,\n+\tISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\tPPC_BITLSHIFT(59), -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv2.07B Transactional Memory Facility (TM or HTM)\n+\t */\n+\t{ \"transactional-memory\",\n+\tCPU_ALL,\n+\tISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\tPPC_BITLSHIFT(58), -1, 62,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv3.0B TM additions\n+\t * TEXASR bit 17, self-induced vs external footprint overflow\n+\t */\n+\t{ \"transactional-memory-v3\",\n+\tCPU_ALL,\n+\tISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_NONE, OS_NONE,\n+\t-1, -1, -1,\n+\t\"transactional-memory\", },\n+\n+\t/*\n+\t * ISAv2.07B Event-Based Branch Facility (EBB)\n+\t */\n+\t{ \"event-based-branch\",\n+\tCPU_ALL,\n+\tISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\tPPC_BITLSHIFT(56), PPC_BITLSHIFT(56), 60,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv2.07B Target Address Register (TAR)\n+\t */\n+\t{ \"target-address-register\",\n+\tCPU_ALL,\n+\tISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\tPPC_BITLSHIFT(55), PPC_BITLSHIFT(55), 58,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv2.07B Control Register (CTRL)\n+\t */\n+\t{ \"control-register\",\n+\tCPU_ALL,\n+\tISA_BASE, USABLE_HV|USABLE_OS,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv2.07B Book3S Chapter 11. Processor Control.\n+\t * msgsnd, msgsndp, doorbell, etc.\n+\t *\n+\t * ISAv3.0B is not compatible (different addressing, HFSCR required\n+\t * for msgsndp).\n+\t */\n+\t{ \"processor-control-facility\",\n+\tCPU_P8_DD2, /* P8 DD1 has no dbell */\n+\tISA_BASE, USABLE_HV|USABLE_OS,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv2.07B PURR, SPURR registers\n+\t */\n+\t{ \"processor-utilization-of-resources-register\",\n+\tCPU_ALL,\n+\tISA_BASE, USABLE_HV|USABLE_OS,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * POWER8 initiate coprocessor store word indexed (icswx) instruction\n+\t */\n+\t{ \"coprocessor-icswx\",\n+\tCPU_P8,\n+\tISA_BASE, USABLE_HV|USABLE_OS,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv2.07B hash based MMU and all instructions, registers,\n+\t * data structures, exceptions, etc.\n+\t */\n+\t{ \"mmu-hash\",\n+\tCPU_P8,\n+\tISA_BASE, USABLE_HV|USABLE_OS,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * POWER8 MCE / machine check exception.\n+\t */\n+\t{ \"machine-check-power8\",\n+\tCPU_P8,\n+\tISA_BASE, USABLE_HV|USABLE_OS,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * POWER8 PMU / performance monitor unit.\n+\t */\n+\t{ \"performance-monitor-power8\",\n+\tCPU_P8,\n+\tISA_BASE, USABLE_HV|USABLE_OS,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv2.07B alignment interrupts set DSISR register\n+\t *\n+\t * POWER CPUs do not used this, and it's removed from ISAv3.0B.\n+\t */\n+\t{ \"alignment-interrupt-dsisr\",\n+\t0,\n+\tISA_BASE, USABLE_HV|USABLE_OS,\n+\tHV_NONE, OS_NONE,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv2.07B / POWER8 doze, nap, sleep, winkle instructions\n+\t * XXX: is Linux we using some BookIV specific implementation details\n+\t * in nap handling? We have no POWER8 specific key here.\n+\t */\n+\t{ \"idle-nap\",\n+\tCPU_P8,\n+\tISA_BASE, USABLE_HV,\n+\tHV_CUSTOM, OS_NONE,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv2.07B wait instruction\n+\t */\n+\t{ \"wait\",\n+\tCPU_P8,\n+\tISA_BASE, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_NONE, OS_NONE,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t{ \"subcore\",\n+\tCPU_P8,\n+\tISA_BASE, USABLE_HV|USABLE_OS,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\t-1, -1, -1,\n+\t\"smt\", },\n+\n+\t/*\n+\t * ISAv3.0B radix based MMU\n+\t */\n+\t{ \"mmu-radix\",\n+\tCPU_P9,\n+\tISA_V3_0B, USABLE_HV|USABLE_OS,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv3.0B hash based MMU, new hash pte format, PCTR, etc\n+\t */\n+\t{ \"mmu-hash-v3\",\n+\tCPU_P9,\n+\tISA_V3_0B, USABLE_HV|USABLE_OS,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv3.0B wait instruction\n+\t */\n+\t{ \"wait-v3\",\n+\tCPU_P9,\n+\tISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_NONE, OS_NONE,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv3.0B stop idle instructions and registers\n+\t * XXX: Same question as for idle-nap\n+\t */\n+\t{ \"idle-stop\",\n+\tCPU_P9,\n+\tISA_V3_0B, USABLE_HV|USABLE_OS,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv3.0B Hypervisor Virtualization Interrupt\n+\t * Also associated system registers, LPCR EE, HEIC, HVICE,\n+\t * system reset SRR1 reason, etc.\n+\t */\n+\t{ \"hypervisor-virtualization-interrupt\",\n+\tCPU_P9,\n+\tISA_V3_0B, USABLE_HV,\n+\tHV_CUSTOM, OS_NONE,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * POWER9 MCE / machine check exception.\n+\t */\n+\t{ \"machine-check-power9\",\n+\tCPU_P9,\n+\tISA_V3_0B, USABLE_HV|USABLE_OS,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * POWER9 PMU / performance monitor unit.\n+\t */\n+\t{ \"performance-monitor-power9\",\n+\tCPU_P9,\n+\tISA_V3_0B, USABLE_HV|USABLE_OS,\n+\tHV_CUSTOM, OS_CUSTOM,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv3.0B scv/rfscv system call instructions and exceptions, fscr bit\n+\t * etc.\n+\t */\n+\t{ \"system-call-vectored\",\n+\tCPU_P9,\n+\tISA_V3_0B, USABLE_OS|USABLE_PR,\n+\tHV_NONE, OS_CUSTOM,\n+\t-1, PPC_BITLSHIFT(51), -1,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv3.0B Book3S Chapter 10. Processor Control.\n+\t * global msgsnd, msgsndp, msgsync, doorbell, etc.\n+\t */\n+\t{ \"processor-control-facility-v3\",\n+\tCPU_P9,\n+\tISA_V3_0B, USABLE_HV|USABLE_OS,\n+\tHV_CUSTOM, OS_NONE,\n+\tPPC_BITLSHIFT(53), -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv3.0B addpcis instruction\n+\t */\n+\t{ \"pc-relative-addressing\",\n+\tCPU_P9,\n+\tISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_NONE, OS_NONE,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv2.07B Book3S Chapter 7. Timer Facilities\n+\t * TB, VTB, DEC, HDEC, IC, etc registers and exceptions.\n+\t * Not including PURR or SPURR registers.\n+\t */\n+\t{ \"timer-facilities\",\n+\tCPU_ALL,\n+\tISA_BASE, USABLE_HV|USABLE_OS,\n+\tHV_NONE, OS_NONE,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv3.0B Book3S Chapter 7. Timer Facilities\n+\t * Large decrementer and hypervisor decrementer\n+\t */\n+\t{ \"timer-facilities-v3\",\n+\tCPU_P9,\n+\tISA_V3_0B, USABLE_HV|USABLE_OS,\n+\tHV_NONE, OS_NONE,\n+\t-1, -1, -1,\n+\t\"timer-facilities\", },\n+\n+\t/*\n+\t * ISAv3.0B deliver a random number instruction (darn)\n+\t */\n+\t{ \"random-number-generator\",\n+\tCPU_P9,\n+\tISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_NONE, OS_NONE,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv3.0B fixed point instructions\n+\t * multiply-add, modulo, count trailing zeroes, cmprb, cmpeqb,\n+\t * extswsli, mfvsrld, mtvsrdd, mtvsrws, addex\n+\t */\n+\t{ \"fixed-point-v3\",\n+\tCPU_P9,\n+\tISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_NONE, OS_NONE,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t{ \"decimal-integer-v3\",\n+\tCPU_P9,\n+\tISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_NONE, OS_NONE,\n+\t-1, -1, -1,\n+\t\"fixed-point-v3 decimal-integer\", },\n+\n+\t/*\n+\t * ISAv3.0B lightweight mffs\n+\t */\n+\t{ \"floating-point-v3\",\n+\tCPU_P9,\n+\tISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_NONE, OS_NONE,\n+\t-1, -1, -1,\n+\t\"floating-point\", },\n+\n+\t{ \"decimal-floating-point-v3\",\n+\tCPU_P9,\n+\tISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_NONE, OS_NONE,\n+\t-1, -1, -1,\n+\t\"floating-point-v3 decimal-floating-point\", },\n+\n+\t{ \"vector-v3\",\n+\tCPU_P9,\n+\tISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_NONE, OS_NONE,\n+\t-1, -1, -1,\n+\t\"vector\", },\n+\n+\t{ \"vector-scalar-v3\",\n+\tCPU_P9,\n+\tISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_NONE, OS_NONE,\n+\t-1, -1, -1,\n+\t\"vector-v3 vector-scalar\" },\n+\n+\t{ \"vector-binary128\",\n+\tCPU_P9,\n+\tISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_NONE, OS_NONE,\n+\t-1, -1, 54,\n+\t\"vector-scalar-v3\", },\n+\n+\t{ \"vector-binary16\",\n+\tCPU_P9,\n+\tISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_NONE, OS_NONE,\n+\t-1, -1, -1,\n+\t\"vector-v3\", },\n+\n+\t/*\n+\t * ISAv3.0B branch instruction and register additions\n+\t * CA32, OV32, mcrxrx, setb\n+\t */\n+\t{ \"branch-v3\",\n+\tCPU_P9,\n+\tISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_NONE, OS_NONE,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv3.0B external exception for EBB\n+\t */\n+\t{ \"event-based-branch-v3\",\n+\tCPU_P9,\n+\tISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_NONE, OS_NONE,\n+\t-1, -1, -1,\n+\t\"event-based-branch\", },\n+\n+\t/*\n+\t * ISAv3.0B Atomic Memory Operations (AMO)\n+\t */\n+\t{ \"atomic-memory-operations\",\n+\tCPU_P9,\n+\tISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_NONE, OS_NONE,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv3.0B Copy-Paste Facility\n+\t */\n+\t{ \"copy-paste\",\n+\tCPU_P9,\n+\tISA_V3_0B, USABLE_HV|USABLE_OS|USABLE_PR,\n+\tHV_NONE, OS_NONE,\n+\t-1, -1, -1,\n+\tNULL, },\n+\n+\t/*\n+\t * ISAv3.0B GSR SPR register\n+\t * POWER9 does not implement it\n+\t */\n+\t{ \"group-start-register\",\n+\t0,\n+\tISA_V3_0B, USABLE_HV|USABLE_OS,\n+\tHV_NONE, OS_NONE,\n+\t-1, -1, -1,\n+\tNULL, },\n+};\n+\n+static void add_cpu_feature_nodeps(struct dt_node *features, const struct cpu_feature *f)\n+{\n+\tstruct dt_node *feature;\n+\n+\tfeature = dt_new(features, f->name);\n+\tassert(feature);\n+\n+\tdt_add_property_cells(feature, \"isa\", f->isa);\n+\tdt_add_property_cells(feature, \"usable-privilege\", f->usable_privilege);\n+\n+\tif (f->usable_privilege & USABLE_HV) {\n+\t\tif (f->hv_support != HV_NONE) {\n+\t\t\tuint32_t s = 0;\n+\t\t\tif (f->hv_support == HV_HFSCR)\n+\t\t\t\ts |= HV_SUPPORT_HFSCR;\n+\n+\t\t\tdt_add_property_cells(feature, \"hv-support\", s);\n+\t\t\tif (f->hfscr_bit_nr != -1)\n+\t\t\t\tdt_add_property_cells(feature, \"hfscr-bit-nr\", f->hfscr_bit_nr);\n+\t\t} else {\n+\t\t\tassert(f->hfscr_bit_nr == -1);\n+\t\t}\n+\t}\n+\n+\tif (f->usable_privilege & USABLE_OS) {\n+\t\tif (f->os_support != OS_NONE) {\n+\t\t\tuint32_t s = 0;\n+\t\t\tif (f->os_support == OS_FSCR)\n+\t\t\t\ts |= OS_SUPPORT_FSCR;\n+\t\t\tdt_add_property_cells(feature, \"os-support\", s);\n+\t\t\tif (f->fscr_bit_nr != -1)\n+\t\t\t\tdt_add_property_cells(feature, \"fscr-bit-nr\", f->fscr_bit_nr);\n+\t\t} else {\n+\t\t\tassert(f->fscr_bit_nr == -1);\n+\t\t}\n+\t}\n+\n+\tif (f->usable_privilege & USABLE_PR) {\n+\t\tif (f->hwcap_bit_nr != -1)\n+\t\t\tdt_add_property_cells(feature, \"hwcap-bit-nr\", f->hwcap_bit_nr);\n+\t}\n+\n+\tif (f->dependencies_names)\n+\t\tdt_add_property(feature, \"dependencies\", NULL, 0);\n+}\n+\n+static void add_cpufeatures_dependencies(struct dt_node *features)\n+{\n+\tstruct dt_node *feature;\n+\n+\tdt_for_each_node(features, feature) {\n+\t\tconst struct cpu_feature *f;\n+\t\tconst char *deps_names;\n+\t\tstruct dt_property *deps;\n+\t\tint nr_deps;\n+\t\tint i;\n+\n+\t\t/* Find features with dependencies */\n+\n+\t\tdeps = __dt_find_property(feature, \"dependencies\");\n+\t\tif (!deps)\n+\t\t\tcontinue;\n+\n+\t\t/* Find the matching cpu table */\n+\t\tfor (i = 0; i < ARRAY_SIZE(cpu_features_table); i++) {\n+\t\t\tf = &cpu_features_table[i];\n+\t\t\tif (!strcmp(f->name, feature->name))\n+\t\t\t\tbreak;\n+\t\t}\n+\t\tassert(f->dependencies_names);\n+\n+\t\t/*\n+\t\t * Count number of depended features and allocate space\n+\t\t * for phandles in the property.\n+\t\t */\n+\t\tdeps_names = f->dependencies_names;\n+\t\tnr_deps = strcount(deps_names, \" \") + 1;\n+\t\tdt_resize_property(&deps, nr_deps * sizeof(u32));\n+\t\tdeps->len = nr_deps * sizeof(u32);\n+\n+\t\tDBG(\"feature %s has %d dependencies (%s)\\n\", f->name, nr_deps, deps_names);\n+\t\t/*\n+\t\t * For each one, find the depended feature then advance to\n+\t\t * next name.\n+\t\t */\n+\t\tfor (i = 0; i < nr_deps; i++) {\n+\t\t\tstruct dt_node *dep;\n+\t\t\tint len;\n+\n+\t\t\tif (nr_deps - i == 1)\n+\t\t\t\tlen = strlen(deps_names);\n+\t\t\telse\n+\t\t\t\tlen = strchr(deps_names, ' ') - deps_names;\n+\n+\t\t\tdt_for_each_node(features, dep) {\n+\t\t\t\tif (!strncmp(deps_names, dep->name, len))\n+\t\t\t\t\tgoto found_dep;\n+\t\t\t}\n+\n+\t\t\tprlog(PR_ERR, \"CPUFT: feature %s dependencies not found\\n\", f->name);\n+\t\t\tbreak;\n+found_dep:\n+\t\t\tDBG(\" %s found dep (%s)\\n\", f->name, dep->name);\n+\t\t\tdt_property_set_cell(deps, i, dep->phandle);\n+\n+\t\t\t/* Advance over the name + delimiter */\n+\t\t\tdeps_names += len + 1;\n+\t\t}\n+\t}\n+}\n+\n+static void add_cpufeatures(struct dt_node *cpus,\n+\t\tuint32_t cpu_feature_isa, uint32_t cpu_feature_cpu)\n+{\n+\tstruct dt_node *features;\n+\tint i;\n+\n+\tDBG(\"creating cpufeatures for cpu:%d isa:%d\\n\", cpu_feature_cpu, cpu_feature_isa);\n+\n+\tfeatures = dt_new(cpus, \"features\");\n+\tassert(features);\n+\n+\tdt_add_property_cells(features, \"isa\", cpu_feature_isa);\n+\n+\tdt_add_property_string(features, \"device_type\", \"ibm,powerpc-cpu-features\");\n+\n+\t/* add without dependencies */\n+\tfor (i = 0; i < ARRAY_SIZE(cpu_features_table); i++) {\n+\t\tconst struct cpu_feature *f = &cpu_features_table[i];\n+\n+\t\tif (f->cpus_supported & cpu_feature_cpu) {\n+\t\t\tDBG(\"  '%s'\\n\", f->name);\n+\t\t\tadd_cpu_feature_nodeps(features, f);\n+\t\t}\n+\t}\n+\n+\t/* dependency construction pass */\n+\tadd_cpufeatures_dependencies(features);\n+}\n+\n+void dt_add_cpufeatures(struct dt_node *root)\n+{\n+\tint version;\n+\tuint32_t cpu_feature_isa = 0;\n+\tuint32_t cpu_feature_cpu = 0;\n+\tstruct dt_node *cpus;\n+\n+\tversion = mfspr(SPR_PVR);\n+\tswitch(PVR_TYPE(version)) {\n+\tcase PVR_TYPE_P8:\n+\tcase PVR_TYPE_P8E:\n+\tcase PVR_TYPE_P8NVL:\n+\t\tcpu_feature_isa = ISA_V2_07B;\n+\t\tif (PVR_VERS_MAJ(version) == 1)\n+\t\t\tcpu_feature_cpu = CPU_P8_DD1;\n+\t\telse\n+\t\t\tcpu_feature_cpu = CPU_P8_DD2;\n+\t\tbreak;\n+\tcase PVR_TYPE_P9:\n+\t\tcpu_feature_isa = ISA_V3_0B;\n+\t\tif (PVR_VERS_MAJ(version) == 1)\n+\t\t\tcpu_feature_cpu = CPU_P9_DD1;\n+\t\telse\n+\t\t\tcpu_feature_cpu = CPU_P9_DD2;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn;\n+\t}\n+\n+\tcpus = dt_new_check(root, \"cpus\");\n+\n+\tadd_cpufeatures(cpus, cpu_feature_isa, cpu_feature_cpu);\n+}\ndiff --git a/core/device.c b/core/device.c\nindex f3ee63fb..38a420eb 100644\n--- a/core/device.c\n+++ b/core/device.c\n@@ -598,6 +598,13 @@ u32 dt_property_get_cell(const struct dt_property *prop, u32 index)\n \treturn fdt32_to_cpu(((const u32 *)prop->prop)[index]);\n }\n \n+void dt_property_set_cell(struct dt_property *prop, u32 index, u32 val)\n+{\n+\tassert(prop->len >= (index+1)*sizeof(u32));\n+\t/* Always aligned, so this works. */\n+\t((u32 *)prop->prop)[index] = cpu_to_fdt32(val);\n+}\n+\n /* First child of this node. */\n struct dt_node *dt_first(const struct dt_node *root)\n {\ndiff --git a/core/init.c b/core/init.c\nindex 6b8137c8..4d4bf651 100644\n--- a/core/init.c\n+++ b/core/init.c\n@@ -790,6 +790,7 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt)\n \t} else {\n \t\tdt_expand(fdt);\n \t}\n+\tdt_add_cpufeatures(dt_root);\n \n \t/* Now that we have a full devicetree, verify that we aren't on fire. */\n \tper_thread_sanity_checks();\ndiff --git a/doc/device-tree/ibm,powerpc-cpu-features/binding.txt b/doc/device-tree/ibm,powerpc-cpu-features/binding.txt\nnew file mode 100644\nindex 00000000..a5270484\n--- /dev/null\n+++ b/doc/device-tree/ibm,powerpc-cpu-features/binding.txt\n@@ -0,0 +1,226 @@\n+ibm,powerpc-cpu-features binding\n+================================\n+\n+This device tree binding describes CPU features available to software, with\n+enablement, privilege, and compatibility metadata.\n+\n+More general description of design and implementation of this binding is\n+found in design.txt, which also points to documentation of specific features.\n+\n+\n+/cpus/ibm,powerpc-cpu-features node binding\n+-------------------------------------------\n+\n+Node: ibm,powerpc-cpu-features\n+\n+Description: Container of CPU feature nodes.\n+\n+The node name must be \"ibm,powerpc-cpu-features\" and it must be a child of the\n+node \"/cpus\".\n+\n+The node is optional but should be provided by new OPAL firmware.\n+\n+Properties:\n+\n+- device_type\n+  Usage: required\n+  Value type: string\n+  Definition: \"cpu-features\"\n+\n+- isa\n+  Usage: required\n+  Value type: <u32>\n+  Definition:\n+\n+  isa that the CPU is currently running in. This provides instruction set\n+  compatibility, less the individual feature nodes. For example, an ISA v3.0\n+  implementation that lacks the \"transactional-memory\" cpufeature node\n+  should not use transactional memory facilities.\n+\n+  Value corresponds to the \"Power ISA Version\" multiplied by 1000.\n+  For example, <3000> corresponds to Version 3.0, <2070> to Version 2.07.\n+  The minor digit is available for revisions.\n+\n+/cpus/ibm,powerpc-cpu-features/example-feature node bindings\n+----------------------------------------------------------------\n+\n+Each child node of cpu-features represents a CPU feature / capability.\n+\n+Node: A string describing an architected CPU feature, e.g., \"floating-point\".\n+\n+Description: A feature or capability supported by the CPUs.\n+\n+The name of the node is a human readable string that forms the interface\n+used to describe features to software. Features are currently documented\n+in the code where they are implemented in skiboot/core/cpufeatures.c\n+\n+Presence of the node indicates the feature is available.\n+\n+Properties:\n+\n+- isa\n+  Usage: required\n+  Value type: <u32>\n+  Definition:\n+\n+  First level of the Power ISA that the feature appears in.\n+  Software should filter out features when constraining the\n+  environment to a particular ISA version.\n+\n+  Value is defined similarly to /cpus/features/isa\n+\n+- usable-privilege\n+  Usage: required\n+  Value type: <u32> bit mask\n+  Definition:\n+              Bit numbers are LSB0\n+              bit 0 - PR (problem state / user mode)\n+              bit 1 - OS (privileged state)\n+              bit 2 - HV (hypervisor state)\n+              All other bits reserved and should be zero.\n+\n+  This property describes the privilege levels and/or software components\n+  that can use the feature.\n+\n+  If bit 0 is set, then the hwcap-bit-nr property will exist.\n+\n+\n+- hv-support\n+  Usage: optional\n+  Value type: <u32> bit mask\n+  Definition:\n+              Bit numbers are LSB0\n+              bit 0 -  HFSCR\n+              All other bits reserved and should be zero.\n+\n+  This property describes the HV privilege support required to enable the\n+  feature to lesser privilege levels. If the property does not exist then no\n+  support is required.\n+\n+  If no bits are set, the hypervisor must have explicit/custom support for\n+  this feature.\n+\n+  If the HFSCR bit is set, then the hfscr-bit-nr property will exist and\n+  the feature may be enabled by setting this bit in the HFSCR register.\n+\n+\n+- os-support\n+  Usage: optional\n+  Value type: <u32> bit mask\n+  Definition:\n+              Bit numbers are LSB0\n+              bit 0 -  FSCR\n+              All other bits reserved and should be zero.\n+\n+  This property describes the OS privilege support required to enable the\n+  feature to lesser privilege levels. If the property does not exist then no\n+  support is required.\n+\n+  If no bits are set, the operating system must have explicit/custom support\n+  for this feature.\n+\n+  If the FSCR bit is set, then the fscr-bit-nr property will exist and\n+  the feature may be enabled by setting this bit in the FSCR register.\n+\n+\n+- hfscr-bit-nr\n+  Usage: optional\n+  Value type: <u32>\n+  Definition: HFSCR bit position (LSB0)\n+\n+  This property exists when the hv-support property HFSCR bit is set. This\n+  property describes the bit number in the HFSCR register that the\n+  hypervisor must set in order to enable this feature.\n+\n+  This property also exists if an HFSCR bit corresponds with this feature.\n+  This makes CPU feature parsing slightly simpler.\n+\n+\n+- fscr-bit-nr\n+  Usage: optional\n+  Value type: <u32>\n+  Definition: FSCR bit position (LSB0)\n+\n+  This property exists when the os-support property FSCR bit is set. This\n+  property describes the bit number in the FSCR register that the\n+  operating system must set in order to enable this feature.\n+\n+  This property also exists if an FSCR bit corresponds with this feature.\n+  This makes CPU feature parsing slightly simpler.\n+\n+\n+- hwcap-bit-nr\n+  Usage: optional\n+  Value type: <u32>\n+  Definition: Linux ELF AUX vector bit position (LSB0)\n+\n+  This property may exist when the usable-privilege property value has PR bit set.\n+  This property describes the bit number that should be set in the ELF AUX\n+  hardware capability vectors in order to advertise this feature to userspace.\n+  Bits 0-31 correspond to bits 0-31 in AT_HWCAP vector. Bits 32-63 correspond\n+  to 0-31 in AT_HWCAP2 vector, and so on.  Missing AT_HWCAPx vectors implies\n+  that the feature is not enabled or can not be advertised. Operating systems\n+  may provide a number of unassigned hardware capability bits to allow for new\n+  features to be advertised.\n+\n+  Some properties representing features created before this binding are\n+  advertised to userspace without a one-to-one hwcap bit number may not specify\n+  this bit. Operating system will handle those bits specifically.  All new\n+  features usable by userspace will have a hwcap-bit-nr property.\n+\n+\n+- dependencies\n+  Usage: optional\n+  Value type: <prop-encoded-array>\n+  Definition:\n+\n+  If this property exists then it is a list of phandles to cpu feature\n+  nodes that must be enabled for this feature to be enabled.\n+\n+\n+Example\n+-------\n+\n+\t/cpus/ibm,powerpc-cpu-features {\n+\t\tdevice_type = \"ibm,powerpc-cpu-features\";\n+\n+\t\tisa = <3020>;\n+\n+\t\tdarn {\n+\t\t\tisa = <3000>;\n+\t\t\tusable-privilege = <1 | 2 | 4>;\n+\t\t\thwcap-bit-nr = <xx>;\n+\t\t};\n+\n+\t\tscv {\n+\t\t\tisa = <3000>;\n+\t\t\tusable-privilege = <1 | 2>;\n+\t\t\tos-support = <0>;\n+\t\t\thwcap-bit-nr = <xx>;\n+\t\t};\n+\n+\t\tstop {\n+\t\t\tisa = <3000>;\n+\t\t\tusable-privilege = <2 | 4>;\n+\t\t\thv-support = <0>;\n+\t\t\tos-support = <0>;\n+\t\t};\n+\n+\t\tvsx2 (hypothetical) {\n+\t\t\tisa = <3010>;\n+\t\t\tusable-privilege = <1 | 2 | 4>;\n+\t\t\thv-support = <0>;\n+\t\t\tos-support = <0>;\n+\t\t\thwcap-bit-nr = <xx>;\n+\t\t};\n+\n+\t\tvsx2-newinsns {\n+\t\t\tisa = <3020>;\n+\t\t\tusable-privilege = <1 | 2 | 4>;\n+\t\t\tos-support = <1>;\n+\t\t\tfscr-bit-nr = <xx>;\n+\t\t\thwcap-bit-nr = <xx>;\n+\t\t\tdependencies = <&vsx2>;\n+\t\t};\n+\n+\t};\ndiff --git a/doc/device-tree/ibm,powerpc-cpu-features/design.txt b/doc/device-tree/ibm,powerpc-cpu-features/design.txt\nnew file mode 100644\nindex 00000000..490e80c5\n--- /dev/null\n+++ b/doc/device-tree/ibm,powerpc-cpu-features/design.txt\n@@ -0,0 +1,157 @@\n+ibm,powerpc-cpu-features binding\n+================================\n+\n+The OPAL / skiboot code is the canonical location for this specification.  All\n+definitions of features, constant, bit positions, etc. must be documented here\n+before being deployed in Linux. This is not presently part of LoPAPR.\n+\n+\n+Interfaces\n+----------\n+This specification describes the /cpus/ibm,powerpc-cpu-features binding (the\n+formal definition of binding can be found in binding.txt in this directory).\n+\n+This specification also involves the Linux ELF AUXV AT_HWCAP and AT_HWCAP2\n+interfaces for PPC_FEATURE* bits. Allocation of new AT_HWCAP bits should be\n+done in coordination with OPAL / skiboot, Linux, and glibc projects.\n+\n+The binding is passed to the hypervisor by firmware. The hypervisor may\n+build a subset with unsupported/disabled features and hypervisor specifics\n+removed, and pass that to a guest OS. The OS may advertise features to\n+userspace.\n+\n+\n+Background\n+----------\n+The cpu-features binding (subsequently \"cpu-features\") aims to provide an\n+extensible metadata and protocol between different levels of system software\n+(firmware, hypervisor, OS/guest, userspace) to advertise the CPU features\n+available on the system. With each level able to shape the features available\n+to the next.\n+\n+The binding specifies features common to all CPUs in the system. Heterogeneous\n+CPU features are not supported at present (such could be added by providing\n+additional cpu-features nodes and linking those to particular CPUs with\n+additional features).\n+\n+There is no strict definition for what a CPU feature must be, but an\n+architectural behaviour or performance characteristic (or group of related\n+behaviours). They must be documented in skiboot/core/cpufeatures.c sufficiently\n+precisely. More guidelines for feature definitions below.\n+\n+cpu-features is intended to provide fine grained control of CPU features at\n+all levels of the stack (firmware, hypervisor, OS, userspace), with the\n+ability for new CPU features to be used by some components without all\n+components being upgraded (e.g., a new floating point instruction could be\n+used by userspace math library without upgrading kernel and hypervisor).\n+\n+\n+Overview\n+--------\n+\n+The cpu-features node is created by firmware and passed to the hypervisor.\n+The hypervisor may create cpu-features node to be passed to guest, based on\n+the features that have been enabled, and policy decisions. Hypervisor specific\n+features, and hypervisor bits and properties should not be advertised to\n+guests. Guest OS may advertise features to userspace using another method\n+(e.g., using AUXV vectors, userspace typically does not parse DT).\n+\n+When the cpu-features node is present, ibm,pa-features and individual feature\n+properties (e.g., \"ibm,vsx\"), and cpu-version under the \"cpu\" compatible nodes\n+can be ignored by the consumer. For compatibility, the provider must continue\n+to provide those older properties and the consumer must not assume cpu-features\n+exists.\n+\n+When this node exists, software may assume a base feature set which is ISA\n+v2.07B (BookS) minus the explicit features listed in core/cpufeatures.c\n+entries in this source tree.\n+\n+Each feature is advertised as a node underneath the cpu-features node, named\n+with a human-readable string name that uniquely identifies specification of\n+that capability.\n+\n+A feature node has a number of metadata properties describing privilege levels\n+a feature may be used (HV, OS, PR/user), and information about how it is to\n+be enabled and advertised to lesser privilege levels. Enabling means to make\n+it available at a lesser privilege level, (how to enable a given feature\n+for this privilege level is implicit: if the software know how to use a\n+feature, it also knows how to enable it).\n+\n+Feature node properties:\n+\n+- \"isa\", the Power ISA version where this feature first became available.\n+  In case of an implementation specific feature\n+\n+- \"usable-privilege\", a bitmask (HV, OS, PR/user) specifying which privilege\n+  levels this feature may be used in.\n+\n+- \"hv-support\", a bitmask. If this exists, the hypervisor must do some work\n+  to enable support for lesser privilege levels. Bits can be set in this mask\n+  to specify prescription/recipes to enable the feature without custom code.\n+  If no bits are set, no recipe exists and custom code must be used. HFSCR\n+  register enable bit is the only such recipe currently.\n+\n+- \"os-support\", similar to hv-support. FSCR recipe.\n+\n+- Features may have additional properties associated, must be documented with\n+  the feature.\n+\n+- Recipes may have additional properties associated. HFSCR recipe has\n+  hfscr-bit-nr, and FSCR recipe has fscr-bit-nr.\n+\n+- \"dependencies\" array of phandles. If this exists, it links to the\n+  features that must be enabled in order for this feature to be enabled.\n+\n+- \"hwcap-bit-nr\" if it exists provides a Linux ELF AUXV HWCAP bit number that\n+  can be used to advertise this feature to userspace.\n+\n+Together, these compatibility, support, and dependencies properties allow\n+unknown features to be enabled and advertised to lesser privilege levels\n+(when possible).\n+\n+All bits not defined in usable, support masks must be 0, and should be ignored\n+by consumers. This allows extensibility to add new privilege levels and new\n+recipes. Unknown properties should also be ignored. This allows extensibility\n+for additional methods and metadata for enablement and advertisement.\n+\n+The policy for seleting and configuring which features to advertise and use\n+is left for implementations.\n+\n+\n+Guidelines for defining features\n+--------------------------------\n+\n+As a rough guide, features should be based on functional groups of changes\n+to the ISA, or related performance characteristics.\n+\n+Grouping should be made by one or a combination of those that:\n+- Share common enablement requirements (e.g., share particular registers or\n+  firmware setup requirements).\n+- Share common usage patterns (e..g, likely to be used together).\n+- Are implemented with a particular new hardware unit.\n+- Are optional in the ISA.\n+\n+Granularity can be debated, but fine grained and encompassing is generally\n+preferable. For example, memory management unit may be considered fundamental,\n+but the MMU in POWER9 is very different and in many ways incompatible from\n+that in POWER8 even in hash mode.\n+\n+For example, \"POWER9\" would be too general, but a new feature for every\n+instruction would be too specific. The \"summary of changes\" preface in Power\n+ISA specification is a good starting point to give a guideline for granularity\n+of the architected features.\n+\n+New features that offer additional or incompatible functionality beyond\n+an existing feature may contain an ISA version postfix.\n+\n+Implementation specific behaviour should contain a CPU type postfix. E.g.,\n+\"machine-check-power9\" gives exact MCE properties. If a future CPU has the same\n+MCE architecture, it should define the same property. If it has a\n+backward-compatible superset, it could additionally define\n+\"machine-check-newcpu\".\n+\n+Features should be \"positive\" as much as possible. That is, the presence of\n+a feature should indicate the presence of an additional CPU feature (e.g., a\n+new instruction or register). This requires some anticipation and foresight\n+for defining CPU features. \"Negative\" features may be unavoidable in some\n+cases.\ndiff --git a/include/device.h b/include/device.h\nindex 5155daad..ca4dd0b0 100644\n--- a/include/device.h\n+++ b/include/device.h\n@@ -125,6 +125,7 @@ void dt_check_del_prop(struct dt_node *node, const char *name);\n /* Warning: moves *prop! */\n void dt_resize_property(struct dt_property **prop, size_t len);\n \n+void dt_property_set_cell(struct dt_property *prop, u32 index, u32 val);\n u32 dt_property_get_cell(const struct dt_property *prop, u32 index);\n \n /* First child of this node. */\ndiff --git a/include/skiboot.h b/include/skiboot.h\nindex 2b1f8a57..764ce8d2 100644\n--- a/include/skiboot.h\n+++ b/include/skiboot.h\n@@ -184,6 +184,11 @@ extern void start_kernel_secondary(uint64_t entry) __noreturn;\n /* Get description of machine from HDAT and create device-tree */\n extern int parse_hdat(bool is_opal);\n \n+struct dt_node;\n+\n+/* Add /cpus/features node for boot environment that passes an fdt */\n+extern void dt_add_cpufeatures(struct dt_node *root);\n+\n /* Root of device tree. */\n extern struct dt_node *dt_root;\n \n","prefixes":["OPAL"]}