{"id":724973,"url":"http://patchwork.ozlabs.org/api/patches/724973/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20170207071657.10071-1-wenyou.yang@atmel.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170207071657.10071-1-wenyou.yang@atmel.com>","list_archive_url":null,"date":"2017-02-07T07:16:57","name":"[U-Boot,v2] ARM: dts: at91: add device tree files for at91sam9x5ek","commit_ref":null,"pull_url":null,"state":"deferred","archived":false,"hash":"58d343c2f707a47bf36ce03181c76708f38f5590","submitter":{"id":16102,"url":"http://patchwork.ozlabs.org/api/people/16102/?format=json","name":"Wenyou Yang","email":"wenyou.yang@atmel.com"},"delegate":{"id":6342,"url":"http://patchwork.ozlabs.org/api/users/6342/?format=json","username":"abiessmann","first_name":"Andreas","last_name":"Bießmann","email":"andreas.biessmann@googlemail.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20170207071657.10071-1-wenyou.yang@atmel.com/mbox/","series":[],"comments":"http://patchwork.ozlabs.org/api/patches/724973/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/724973/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Received":["from theia.denx.de (theia.denx.de [85.214.87.163])\n\tby ozlabs.org (Postfix) with ESMTP id 3vHbWD1FBvz9s2G\n\tfor ;\n\tTue, 7 Feb 2017 18:26:48 +1100 (AEDT)","from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 65AA9B38CB;\n\tTue, 7 Feb 2017 08:23:48 +0100 (CET)","from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id iZnejrdF8KfX; Tue, 7 Feb 2017 08:23:48 +0100 (CET)","from theia.denx.de (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 4E106B38DD;\n\tTue, 7 Feb 2017 08:23:40 +0100 (CET)","from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 7FB89B38DD\n\tfor ; Tue, 7 Feb 2017 08:23:29 +0100 (CET)","from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id LvRZj_XzKRVf for ;\n\tTue, 7 Feb 2017 08:23:29 +0100 (CET)","from ussmtp01.atmel.com (nasmtp01.atmel.com [192.199.1.245])\n\tby theia.denx.de (Postfix) with ESMTPS id 1BBF4B38E4\n\tfor ; Tue, 7 Feb 2017 08:22:09 +0100 (CET)","from apsmtp01.atmel.com (10.168.254.31) by DVREDG01.corp.atmel.com\n\t(10.42.103.30) with Microsoft SMTP Server (TLS) id 14.3.235.1;\n\tTue, 7 Feb 2017 00:22:03 -0700","from shaarm01.corp.atmel.com (10.168.254.13) by apsmtp01.atmel.com\n\t(10.168.254.31) with Microsoft SMTP Server id 14.3.235.1;\n\tTue, 7 Feb 2017 15:26:21 +0800"],"X-policyd-weight":"NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5\n\tNOT_IN_BL_NJABL=-1.5 (only DNSBL check requested)","From":"Wenyou Yang ","To":"U-Boot Mailing List ","Date":"Tue, 7 Feb 2017 15:16:57 +0800","Message-ID":"<20170207071657.10071-1-wenyou.yang@atmel.com>","X-Mailer":"git-send-email 2.11.0","MIME-Version":"1.0","Cc":"Albert Aribaud ","Subject":"[U-Boot] [PATCH v2] ARM: dts: at91: add device tree files for\n\tat91sam9x5ek","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.15","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"The device tree source files of at91sam9x5ek board are copied\nfrom the Linux kernel, do the changes below.\n - Add the reg property for the pinctrl node.\n - Move the gpio (pioA, pioB, pioC ...) nodes as the pinctrl's\n slibling nodes, instead of the child nodes.\n - Change the compatible of the spi flash to \"spi-flash\".\n - Add spi0 aliases.\n - Fix the compile warnings.\n\nSigned-off-by: Wenyou Yang \n---\n\nChanges in v2:\n - Rebase on the patch set:\n [PATCH v3 0/2] ARM: dts: at91: add dts files for the boards of SAMA5D3\n http://lists.denx.de/pipermail/u-boot/2017-February/280475.html\n\n arch/arm/dts/Makefile | 7 +\n arch/arm/dts/at91sam9g15.dtsi | 29 +\n arch/arm/dts/at91sam9g15ek.dts | 41 ++\n arch/arm/dts/at91sam9g25.dtsi | 31 +\n arch/arm/dts/at91sam9g25ek.dts | 69 ++\n arch/arm/dts/at91sam9g35.dtsi | 30 +\n arch/arm/dts/at91sam9g35ek.dts | 46 ++\n arch/arm/dts/at91sam9x25.dtsi | 32 +\n arch/arm/dts/at91sam9x25ek.dts | 30 +\n arch/arm/dts/at91sam9x35.dtsi | 31 +\n arch/arm/dts/at91sam9x35ek.dts | 45 ++\n arch/arm/dts/at91sam9x5.dtsi | 1292 +++++++++++++++++++++++++++++++++++\n arch/arm/dts/at91sam9x5_can.dtsi | 71 ++\n arch/arm/dts/at91sam9x5_isi.dtsi | 72 ++\n arch/arm/dts/at91sam9x5_lcd.dtsi | 165 +++++\n arch/arm/dts/at91sam9x5_macb0.dtsi | 67 ++\n arch/arm/dts/at91sam9x5_macb1.dtsi | 55 ++\n arch/arm/dts/at91sam9x5_usart3.dtsi | 69 ++\n arch/arm/dts/at91sam9x5cm.dtsi | 100 +++\n arch/arm/dts/at91sam9x5dm.dtsi | 101 +++\n arch/arm/dts/at91sam9x5ek.dtsi | 165 +++++\n 21 files changed, 2548 insertions(+)\n create mode 100644 arch/arm/dts/at91sam9g15.dtsi\n create mode 100644 arch/arm/dts/at91sam9g15ek.dts\n create mode 100644 arch/arm/dts/at91sam9g25.dtsi\n create mode 100644 arch/arm/dts/at91sam9g25ek.dts\n create mode 100644 arch/arm/dts/at91sam9g35.dtsi\n create mode 100644 arch/arm/dts/at91sam9g35ek.dts\n create mode 100644 arch/arm/dts/at91sam9x25.dtsi\n create mode 100644 arch/arm/dts/at91sam9x25ek.dts\n create mode 100644 arch/arm/dts/at91sam9x35.dtsi\n create mode 100644 arch/arm/dts/at91sam9x35ek.dts\n create mode 100644 arch/arm/dts/at91sam9x5.dtsi\n create mode 100644 arch/arm/dts/at91sam9x5_can.dtsi\n create mode 100644 arch/arm/dts/at91sam9x5_isi.dtsi\n create mode 100644 arch/arm/dts/at91sam9x5_lcd.dtsi\n create mode 100644 arch/arm/dts/at91sam9x5_macb0.dtsi\n create mode 100644 arch/arm/dts/at91sam9x5_macb1.dtsi\n create mode 100644 arch/arm/dts/at91sam9x5_usart3.dtsi\n create mode 100644 arch/arm/dts/at91sam9x5cm.dtsi\n create mode 100644 arch/arm/dts/at91sam9x5dm.dtsi\n create mode 100644 arch/arm/dts/at91sam9x5ek.dtsi","diff":"diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\nindex 18db8c8f79..fce84b4e12 100644\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -325,6 +325,13 @@ dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \\\n \tk2e-evm.dtb \\\n \tk2g-evm.dtb\n \n+dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \\\n+\tat91sam9g15ek.dtb\t\\\n+\tat91sam9g25ek.dtb\t\\\n+\tat91sam9g35ek.dtb\t\\\n+\tat91sam9x25ek.dtb\t\\\n+\tat91sam9x35ek.dtb\n+\n dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \\\n \tat91-sama5d2_xplained.dtb\n \ndiff --git a/arch/arm/dts/at91sam9g15.dtsi b/arch/arm/dts/at91sam9g15.dtsi\nnew file mode 100644\nindex 0000000000..27de7dc0f0\n--- /dev/null\n+++ b/arch/arm/dts/at91sam9g15.dtsi\n@@ -0,0 +1,29 @@\n+/*\n+ * at91sam9g15.dtsi - Device Tree Include file for AT91SAM9G15 SoC\n+ *\n+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD \n+ *\n+ * Licensed under GPLv2.\n+ */\n+\n+#include \"at91sam9x5.dtsi\"\n+#include \"at91sam9x5_lcd.dtsi\"\n+\n+/ {\n+\tmodel = \"Atmel AT91SAM9G15 SoC\";\n+\tcompatible = \"atmel,at91sam9g15\", \"atmel,at91sam9x5\";\n+\n+\tahb {\n+\t\tapb {\n+\t\t\tpinctrl@fffff400 {\n+\t\t\t\tatmel,mux-mask = <\n+\t\t\t\t /* A B C */\n+\t\t\t\t 0xffffffff 0xffe0399f 0x00000000 /* pioA */\n+\t\t\t\t 0x00040000 0x00047e3f 0x00000000 /* pioB */\n+\t\t\t\t 0xfdffffff 0x00000000 0xb83fffff /* pioC */\n+\t\t\t\t 0x003fffff 0x003f8000 0x00000000 /* pioD */\n+\t\t\t\t >;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/dts/at91sam9g15ek.dts b/arch/arm/dts/at91sam9g15ek.dts\nnew file mode 100644\nindex 0000000000..d1d2b400f1\n--- /dev/null\n+++ b/arch/arm/dts/at91sam9g15ek.dts\n@@ -0,0 +1,41 @@\n+/*\n+ * at91sam9g15ek.dts - Device Tree file for AT91SAM9G15-EK board\n+ *\n+ * Copyright (C) 2012 Atmel,\n+ * 2012 Nicolas Ferre \n+ *\n+ * Licensed under GPLv2 or later.\n+ */\n+/dts-v1/;\n+#include \"at91sam9g15.dtsi\"\n+#include \"at91sam9x5dm.dtsi\"\n+#include \"at91sam9x5ek.dtsi\"\n+\n+/ {\n+\tmodel = \"Atmel AT91SAM9G15-EK\";\n+\tcompatible = \"atmel,at91sam9g15ek\", \"atmel,at91sam9x5ek\", \"atmel,at91sam9x5\", \"atmel,at91sam9\";\n+\n+\tahb {\n+\t\tapb {\n+\t\t\thlcdc: hlcdc@f8038000 {\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tbacklight: backlight {\n+\t\tstatus = \"okay\";\n+\t};\n+\n+\tbl_reg: backlight_regulator {\n+\t\tstatus = \"okay\";\n+\t};\n+\n+\tpanel: panel {\n+\t\tstatus = \"okay\";\n+\t};\n+\n+\tpanel_reg: panel_regulator {\n+\t\tstatus = \"okay\";\n+\t};\n+};\ndiff --git a/arch/arm/dts/at91sam9g25.dtsi b/arch/arm/dts/at91sam9g25.dtsi\nnew file mode 100644\nindex 0000000000..a7da0dd0c9\n--- /dev/null\n+++ b/arch/arm/dts/at91sam9g25.dtsi\n@@ -0,0 +1,31 @@\n+/*\n+ * at91sam9g25.dtsi - Device Tree Include file for AT91SAM9G25 SoC\n+ *\n+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD \n+ *\n+ * Licensed under GPLv2.\n+ */\n+\n+#include \"at91sam9x5.dtsi\"\n+#include \"at91sam9x5_isi.dtsi\"\n+#include \"at91sam9x5_usart3.dtsi\"\n+#include \"at91sam9x5_macb0.dtsi\"\n+\n+/ {\n+\tmodel = \"Atmel AT91SAM9G25 SoC\";\n+\tcompatible = \"atmel,at91sam9g25\", \"atmel,at91sam9x5\";\n+\n+\tahb {\n+\t\tapb {\n+\t\t\tpinctrl@fffff400 {\n+\t\t\t\tatmel,mux-mask = <\n+\t\t\t\t /* A B C */\n+\t\t\t\t 0xffffffff 0xffe0399f 0xc000001c /* pioA */\n+\t\t\t\t 0x0007ffff 0x8000fe3f 0x00000000 /* pioB */\n+\t\t\t\t 0x80000000 0x07c0ffff 0xb83fffff /* pioC */\n+\t\t\t\t 0x003fffff 0x003f8000 0x00000000 /* pioD */\n+\t\t\t\t >;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/dts/at91sam9g25ek.dts b/arch/arm/dts/at91sam9g25ek.dts\nnew file mode 100644\nindex 0000000000..91a7177447\n--- /dev/null\n+++ b/arch/arm/dts/at91sam9g25ek.dts\n@@ -0,0 +1,69 @@\n+/*\n+ * at91sam9g25ek.dts - Device Tree file for AT91SAM9G25-EK board\n+ *\n+ * Copyright (C) 2012 Atmel,\n+ * 2012 Nicolas Ferre \n+ *\n+ * Licensed under GPLv2 or later.\n+ */\n+/dts-v1/;\n+#include \"at91sam9g25.dtsi\"\n+#include \"at91sam9x5ek.dtsi\"\n+\n+/ {\n+\tmodel = \"Atmel AT91SAM9G25-EK\";\n+\tcompatible = \"atmel,at91sam9g25ek\", \"atmel,at91sam9x5ek\", \"atmel,at91sam9x5\", \"atmel,at91sam9\";\n+\n+\tahb {\n+\t\tapb {\n+\t\t\tspi0: spi@f0000000 {\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tmmc1: mmc@f000c000 {\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\ti2c0: i2c@f8010000 {\n+\t\t\t\tov2640: camera@0x30 {\n+\t\t\t\t\tcompatible = \"ovti,ov2640\";\n+\t\t\t\t\treg = <0x30>;\n+\t\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\t\tpinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;\n+\t\t\t\t\tresetb-gpios = <&pioA 7 GPIO_ACTIVE_LOW>;\n+\t\t\t\t\tpwdn-gpios = <&pioA 13 GPIO_ACTIVE_HIGH>;\n+\t\t\t\t\tclocks = <&pck0>;\n+\t\t\t\t\tclock-names = \"xvclk\";\n+\t\t\t\t\tassigned-clocks = <&pck0>;\n+\t\t\t\t\tassigned-clock-rates = <25000000>;\n+\t\t\t\t\tstatus = \"okay\";\n+\n+\t\t\t\t\tport {\n+\t\t\t\t\t\tov2640_0: endpoint {\n+\t\t\t\t\t\t\tremote-endpoint = <&isi_0>;\n+\t\t\t\t\t\t\tbus-width = <8>;\n+\t\t\t\t\t\t};\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tmacb0: ethernet@f802c000 {\n+\t\t\t\tphy-mode = \"rmii\";\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\n+\t\t\tisi: isi@f8048000 {\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\tport {\n+\t\t\t\t\tisi_0: endpoint@0 {\n+\t\t\t\t\t\treg = <0>;\n+\t\t\t\t\t\tremote-endpoint = <&ov2640_0>;\n+\t\t\t\t\t\tbus-width = <8>;\n+\t\t\t\t\t\tvsync-active = <1>;\n+\t\t\t\t\t\thsync-active = <1>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/dts/at91sam9g35.dtsi b/arch/arm/dts/at91sam9g35.dtsi\nnew file mode 100644\nindex 0000000000..ff4115886f\n--- /dev/null\n+++ b/arch/arm/dts/at91sam9g35.dtsi\n@@ -0,0 +1,30 @@\n+/*\n+ * at91sam9g35.dtsi - Device Tree Include file for AT91SAM9G35 SoC\n+ *\n+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD \n+ *\n+ * Licensed under GPLv2.\n+ */\n+\n+#include \"at91sam9x5.dtsi\"\n+#include \"at91sam9x5_lcd.dtsi\"\n+#include \"at91sam9x5_macb0.dtsi\"\n+\n+/ {\n+\tmodel = \"Atmel AT91SAM9G35 SoC\";\n+\tcompatible = \"atmel,at91sam9g35\", \"atmel,at91sam9x5\";\n+\n+\tahb {\n+\t\tapb {\n+\t\t\tpinctrl@fffff400 {\n+\t\t\t\tatmel,mux-mask = <\n+\t\t\t\t /* A B C */\n+\t\t\t\t 0xffffffff 0xffe0399f 0xc000000c /* pioA */\n+\t\t\t\t 0x000406ff 0x00047e3f 0x00000000 /* pioB */\n+\t\t\t\t 0xfdffffff 0x00000000 0xb83fffff /* pioC */\n+\t\t\t\t 0x003fffff 0x003f8000 0x00000000 /* pioD */\n+\t\t\t\t >;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/dts/at91sam9g35ek.dts b/arch/arm/dts/at91sam9g35ek.dts\nnew file mode 100644\nindex 0000000000..23ec8b13f3\n--- /dev/null\n+++ b/arch/arm/dts/at91sam9g35ek.dts\n@@ -0,0 +1,46 @@\n+/*\n+ * at91sam9g35ek.dts - Device Tree file for AT91SAM9G35-EK board\n+ *\n+ * Copyright (C) 2012 Atmel,\n+ * 2012 Nicolas Ferre \n+ *\n+ * Licensed under GPLv2 or later.\n+ */\n+/dts-v1/;\n+#include \"at91sam9g35.dtsi\"\n+#include \"at91sam9x5dm.dtsi\"\n+#include \"at91sam9x5ek.dtsi\"\n+\n+/ {\n+\tmodel = \"Atmel AT91SAM9G35-EK\";\n+\tcompatible = \"atmel,at91sam9g35ek\", \"atmel,at91sam9x5ek\", \"atmel,at91sam9x5\", \"atmel,at91sam9\";\n+\n+\tahb {\n+\t\tapb {\n+\t\t\tmacb0: ethernet@f802c000 {\n+\t\t\t\tphy-mode = \"rmii\";\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\n+\t\t\thlcdc: hlcdc@f8038000 {\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tbacklight: backlight {\n+\t\tstatus = \"okay\";\n+\t};\n+\n+\tbl_reg: backlight_regulator {\n+\t\tstatus = \"okay\";\n+\t};\n+\n+\tpanel: panel {\n+\t\tstatus = \"okay\";\n+\t};\n+\n+\tpanel_reg: panel_regulator {\n+\t\tstatus = \"okay\";\n+\t};\n+};\ndiff --git a/arch/arm/dts/at91sam9x25.dtsi b/arch/arm/dts/at91sam9x25.dtsi\nnew file mode 100644\nindex 0000000000..3c5fa33889\n--- /dev/null\n+++ b/arch/arm/dts/at91sam9x25.dtsi\n@@ -0,0 +1,32 @@\n+/*\n+ * at91sam9x25.dtsi - Device Tree Include file for AT91SAM9X25 SoC\n+ *\n+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD \n+ *\n+ * Licensed under GPLv2.\n+ */\n+\n+#include \"at91sam9x5.dtsi\"\n+#include \"at91sam9x5_usart3.dtsi\"\n+#include \"at91sam9x5_macb0.dtsi\"\n+#include \"at91sam9x5_macb1.dtsi\"\n+#include \"at91sam9x5_can.dtsi\"\n+\n+/ {\n+\tmodel = \"Atmel AT91SAM9X25 SoC\";\n+\tcompatible = \"atmel,at91sam9x25\", \"atmel,at91sam9x5\";\n+\n+\tahb {\n+\t\tapb {\n+\t\t\tpinctrl@fffff400 {\n+\t\t\t\tatmel,mux-mask = <\n+\t\t\t\t /* A B C */\n+\t\t\t\t 0xffffffff 0xffe03fff 0xc000001c /* pioA */\n+\t\t\t\t 0x0007ffff 0x00047e3f 0x00000000 /* pioB */\n+\t\t\t\t 0x80000000 0xfffd0000 0xb83fffff /* pioC */\n+\t\t\t\t 0x003fffff 0x003f8000 0x00000000 /* pioD */\n+\t\t\t\t >;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/dts/at91sam9x25ek.dts b/arch/arm/dts/at91sam9x25ek.dts\nnew file mode 100644\nindex 0000000000..494864836e\n--- /dev/null\n+++ b/arch/arm/dts/at91sam9x25ek.dts\n@@ -0,0 +1,30 @@\n+/*\n+ * at91sam9x25ek.dts - Device Tree file for AT91SAM9X25-EK board\n+ *\n+ * Copyright (C) 2012 Atmel,\n+ * 2012 Nicolas Ferre \n+ *\n+ * Licensed under GPLv2 or later.\n+ */\n+/dts-v1/;\n+#include \"at91sam9x25.dtsi\"\n+#include \"at91sam9x5ek.dtsi\"\n+\n+/ {\n+\tmodel = \"Atmel AT91SAM9X25-EK\";\n+\tcompatible = \"atmel,at91sam9x25ek\", \"atmel,at91sam9x5ek\", \"atmel,at91sam9x5\", \"atmel,at91sam9\";\n+\n+\tahb {\n+\t\tapb {\n+\t\t\tmacb0: ethernet@f802c000 {\n+\t\t\t\tphy-mode = \"rmii\";\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\n+\t\t\tmacb1: ethernet@f8030000 {\n+\t\t\t\tphy-mode = \"rmii\";\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/dts/at91sam9x35.dtsi b/arch/arm/dts/at91sam9x35.dtsi\nnew file mode 100644\nindex 0000000000..d9054e8167\n--- /dev/null\n+++ b/arch/arm/dts/at91sam9x35.dtsi\n@@ -0,0 +1,31 @@\n+/*\n+ * at91sam9x35.dtsi - Device Tree Include file for AT91SAM9X35 SoC\n+ *\n+ * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD \n+ *\n+ * Licensed under GPLv2.\n+ */\n+\n+#include \"at91sam9x5.dtsi\"\n+#include \"at91sam9x5_lcd.dtsi\"\n+#include \"at91sam9x5_macb0.dtsi\"\n+#include \"at91sam9x5_can.dtsi\"\n+\n+/ {\n+\tmodel = \"Atmel AT91SAM9X35 SoC\";\n+\tcompatible = \"atmel,at91sam9x35\", \"atmel,at91sam9x5\";\n+\n+\tahb {\n+\t\tapb {\n+\t\t\tpinctrl@fffff400 {\n+\t\t\t\tatmel,mux-mask = <\n+\t\t\t\t /* A B C */\n+\t\t\t\t 0xffffffff 0xffe03fff 0xc000000c /* pioA */\n+\t\t\t\t 0x000406ff 0x00047e3f 0x00000000 /* pioB */\n+\t\t\t\t 0xfdffffff 0x00000000 0xb83fffff /* pioC */\n+\t\t\t\t 0x003fffff 0x003f8000 0x00000000 /* pioD */\n+\t\t\t\t >;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/dts/at91sam9x35ek.dts b/arch/arm/dts/at91sam9x35ek.dts\nnew file mode 100644\nindex 0000000000..fcb67180ea\n--- /dev/null\n+++ b/arch/arm/dts/at91sam9x35ek.dts\n@@ -0,0 +1,45 @@\n+/*\n+ * at91sam9x35ek.dts - Device Tree file for AT91SAM9X35-EK board\n+ *\n+ * Copyright (C) 2012 Atmel,\n+ * 2012 Nicolas Ferre \n+ *\n+ * Licensed under GPLv2 or later.\n+ */\n+/dts-v1/;\n+#include \"at91sam9x35.dtsi\"\n+#include \"at91sam9x5dm.dtsi\"\n+#include \"at91sam9x5ek.dtsi\"\n+\n+/ {\n+\tmodel = \"Atmel AT91SAM9X35-EK\";\n+\tcompatible = \"atmel,at91sam9x35ek\", \"atmel,at91sam9x5ek\", \"atmel,at91sam9x5\", \"atmel,at91sam9\";\n+\n+\tahb {\n+\t\tapb {\n+\t\t\tmacb0: ethernet@f802c000 {\n+\t\t\t\tphy-mode = \"rmii\";\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t\thlcdc: hlcdc@f8038000 {\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tbacklight: backlight {\n+\t\tstatus = \"okay\";\n+\t};\n+\n+\tbl_reg: backlight_regulator {\n+\t\tstatus = \"okay\";\n+\t};\n+\n+\tpanel: panel {\n+\t\tstatus = \"okay\";\n+\t};\n+\n+\tpanel_reg: panel_regulator {\n+\t\tstatus = \"okay\";\n+\t};\n+};\ndiff --git a/arch/arm/dts/at91sam9x5.dtsi b/arch/arm/dts/at91sam9x5.dtsi\nnew file mode 100644\nindex 0000000000..a5f836a5ac\n--- /dev/null\n+++ b/arch/arm/dts/at91sam9x5.dtsi\n@@ -0,0 +1,1292 @@\n+/*\n+ * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC\n+ * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,\n+ * AT91SAM9X25, AT91SAM9X35 SoC\n+ *\n+ * Copyright (C) 2012 Atmel,\n+ * 2012 Nicolas Ferre \n+ *\n+ * Licensed under GPLv2 or later.\n+ */\n+\n+#include \"skeleton.dtsi\"\n+#include \n+#include \n+#include \n+#include \n+#include \n+\n+/ {\n+\tmodel = \"Atmel AT91SAM9x5 family SoC\";\n+\tcompatible = \"atmel,at91sam9x5\";\n+\tinterrupt-parent = <&aic>;\n+\n+\taliases {\n+\t\tserial0 = &dbgu;\n+\t\tserial1 = &usart0;\n+\t\tserial2 = &usart1;\n+\t\tserial3 = &usart2;\n+\t\tgpio0 = &pioA;\n+\t\tgpio1 = &pioB;\n+\t\tgpio2 = &pioC;\n+\t\tgpio3 = &pioD;\n+\t\ttcb0 = &tcb0;\n+\t\ttcb1 = &tcb1;\n+\t\ti2c0 = &i2c0;\n+\t\ti2c1 = &i2c1;\n+\t\ti2c2 = &i2c2;\n+\t\tssc0 = &ssc0;\n+\t\tpwm0 = &pwm0;\n+\t\tspi0 = &spi0;\n+\t};\n+\n+\tcpus {\n+\t\t#address-cells = <0>;\n+\t\t#size-cells = <0>;\n+\n+\t\tcpu {\n+\t\t\tcompatible = \"arm,arm926ej-s\";\n+\t\t\tdevice_type = \"cpu\";\n+\t\t};\n+\t};\n+\n+\tmemory {\n+\t\treg = <0x20000000 0x10000000>;\n+\t};\n+\n+\tclocks {\n+\t\tslow_xtal: slow_xtal {\n+\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t#clock-cells = <0>;\n+\t\t\tclock-frequency = <0>;\n+\t\t};\n+\n+\t\tmain_xtal: main_xtal {\n+\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t#clock-cells = <0>;\n+\t\t\tclock-frequency = <0>;\n+\t\t};\n+\n+\t\tadc_op_clk: adc_op_clk{\n+\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t#clock-cells = <0>;\n+\t\t\tclock-frequency = <1000000>;\n+\t\t};\n+\t};\n+\n+\tsram: sram@00300000 {\n+\t\tcompatible = \"mmio-sram\";\n+\t\treg = <0x00300000 0x8000>;\n+\t};\n+\n+\tahb {\n+\t\tcompatible = \"simple-bus\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tranges;\n+\n+\t\tapb {\n+\t\t\tcompatible = \"simple-bus\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tranges;\n+\n+\t\t\taic: interrupt-controller@fffff000 {\n+\t\t\t\t#interrupt-cells = <3>;\n+\t\t\t\tcompatible = \"atmel,at91rm9200-aic\";\n+\t\t\t\tinterrupt-controller;\n+\t\t\t\treg = <0xfffff000 0x200>;\n+\t\t\t\tatmel,external-irqs = <31>;\n+\t\t\t};\n+\n+\t\t\tramc0: ramc@ffffe800 {\n+\t\t\t\tcompatible = \"atmel,at91sam9g45-ddramc\";\n+\t\t\t\treg = <0xffffe800 0x200>;\n+\t\t\t\tclocks = <&ddrck>;\n+\t\t\t\tclock-names = \"ddrck\";\n+\t\t\t};\n+\n+\t\t\tpmc: pmc@fffffc00 {\n+\t\t\t\tcompatible = \"atmel,at91sam9x5-pmc\", \"syscon\";\n+\t\t\t\treg = <0xfffffc00 0x200>;\n+\t\t\t\tinterrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;\n+\t\t\t\tinterrupt-controller;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\t#interrupt-cells = <1>;\n+\n+\t\t\t\tmain_rc_osc: main_rc_osc {\n+\t\t\t\t\tcompatible = \"atmel,at91sam9x5-clk-main-rc-osc\";\n+\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\tinterrupts-extended = <&pmc AT91_PMC_MOSCRCS>;\n+\t\t\t\t\tclock-frequency = <12000000>;\n+\t\t\t\t\tclock-accuracy = <50000000>;\n+\t\t\t\t};\n+\n+\t\t\t\tmain_osc: main_osc {\n+\t\t\t\t\tcompatible = \"atmel,at91rm9200-clk-main-osc\";\n+\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\tinterrupts-extended = <&pmc AT91_PMC_MOSCS>;\n+\t\t\t\t\tclocks = <&main_xtal>;\n+\t\t\t\t};\n+\n+\t\t\t\tmain: mainck {\n+\t\t\t\t\tcompatible = \"atmel,at91sam9x5-clk-main\";\n+\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\tinterrupts-extended = <&pmc AT91_PMC_MOSCSELS>;\n+\t\t\t\t\tclocks = <&main_rc_osc>, <&main_osc>;\n+\t\t\t\t};\n+\n+\t\t\t\tplla: pllack@0 {\n+\t\t\t\t\tcompatible = \"atmel,at91rm9200-clk-pll\";\n+\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\tinterrupts-extended = <&pmc AT91_PMC_LOCKA>;\n+\t\t\t\t\tclocks = <&main>;\n+\t\t\t\t\treg = <0>;\n+\t\t\t\t\tatmel,clk-input-range = <2000000 32000000>;\n+\t\t\t\t\t#atmel,pll-clk-output-range-cells = <4>;\n+\t\t\t\t\tatmel,pll-clk-output-ranges = <745000000 800000000 0 0\n+\t\t\t\t\t\t\t\t 695000000 750000000 1 0\n+\t\t\t\t\t\t\t\t 645000000 700000000 2 0\n+\t\t\t\t\t\t\t\t 595000000 650000000 3 0\n+\t\t\t\t\t\t\t\t 545000000 600000000 0 1\n+\t\t\t\t\t\t\t\t 495000000 555000000 1 1\n+\t\t\t\t\t\t\t\t 445000000 500000000 2 1\n+\t\t\t\t\t\t\t\t 400000000 450000000 3 1>;\n+\t\t\t\t};\n+\n+\t\t\t\tplladiv: plladivck {\n+\t\t\t\t\tcompatible = \"atmel,at91sam9x5-clk-plldiv\";\n+\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\tclocks = <&plla>;\n+\t\t\t\t};\n+\n+\t\t\t\tutmi: utmick {\n+\t\t\t\t\tcompatible = \"atmel,at91sam9x5-clk-utmi\";\n+\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\tinterrupts-extended = <&pmc AT91_PMC_LOCKU>;\n+\t\t\t\t\tclocks = <&main>;\n+\t\t\t\t};\n+\n+\t\t\t\tmck: masterck {\n+\t\t\t\t\tcompatible = \"atmel,at91sam9x5-clk-master\";\n+\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\tinterrupts-extended = <&pmc AT91_PMC_MCKRDY>;\n+\t\t\t\t\tclocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;\n+\t\t\t\t\tatmel,clk-output-range = <0 133333333>;\n+\t\t\t\t\tatmel,clk-divisors = <1 2 4 3>;\n+\t\t\t\t\tatmel,master-clk-have-div3-pres;\n+\t\t\t\t};\n+\n+\t\t\t\tusb: usbck {\n+\t\t\t\t\tcompatible = \"atmel,at91sam9x5-clk-usb\";\n+\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\tclocks = <&plladiv>, <&utmi>;\n+\t\t\t\t};\n+\n+\t\t\t\tprog: progck {\n+\t\t\t\t\tcompatible = \"atmel,at91sam9x5-clk-programmable\";\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\tinterrupt-parent = <&pmc>;\n+\t\t\t\t\tclocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;\n+\n+\t\t\t\t\tprog0: prog@0 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <0>;\n+\t\t\t\t\t\tinterrupts = ;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tprog1: prog@1 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <1>;\n+\t\t\t\t\t\tinterrupts = ;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tsmd: smdclk {\n+\t\t\t\t\tcompatible = \"atmel,at91sam9x5-clk-smd\";\n+\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\tclocks = <&plladiv>, <&utmi>;\n+\t\t\t\t};\n+\n+\t\t\t\tsystemck {\n+\t\t\t\t\tcompatible = \"atmel,at91rm9200-clk-system\";\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\n+\t\t\t\t\tddrck: ddrck@2 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <2>;\n+\t\t\t\t\t\tclocks = <&mck>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tsmdck: smdck@4 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <4>;\n+\t\t\t\t\t\tclocks = <&smd>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tuhpck: uhpck@6 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <6>;\n+\t\t\t\t\t\tclocks = <&usb>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tudpck: udpck@7 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <7>;\n+\t\t\t\t\t\tclocks = <&usb>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpck0: pck0@8 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <8>;\n+\t\t\t\t\t\tclocks = <&prog0>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpck1: pck1@9 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <9>;\n+\t\t\t\t\t\tclocks = <&prog1>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tperiphck {\n+\t\t\t\t\tcompatible = \"atmel,at91sam9x5-clk-peripheral\";\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\tclocks = <&mck>;\n+\n+\t\t\t\t\tpioAB_clk: pioAB_clk@2 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <2>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpioCD_clk: pioCD_clk@3 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <3>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tsmd_clk: smd_clk@4 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <4>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tusart0_clk: usart0_clk@5 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <5>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tusart1_clk: usart1_clk@6 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <6>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tusart2_clk: usart2_clk@7 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <7>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\ttwi0_clk: twi0_clk@9 {\n+\t\t\t\t\t\treg = <9>;\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\ttwi1_clk: twi1_clk@10 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <10>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\ttwi2_clk: twi2_clk@11 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <11>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tmci0_clk: mci0_clk@12 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <12>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tspi0_clk: spi0_clk@13 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <13>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tspi1_clk: spi1_clk@14 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <14>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tuart0_clk: uart0_clk@15 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <15>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tuart1_clk: uart1_clk@16 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <16>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\ttcb0_clk: tcb0_clk@17 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <17>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpwm_clk: pwm_clk@18 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <18>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tadc_clk: adc_clk@19 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <19>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tdma0_clk: dma0_clk@20 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <20>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tdma1_clk: dma1_clk@21 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <21>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tuhphs_clk: uhphs_clk@22 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <22>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tudphs_clk: udphs_clk@23 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <23>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tmci1_clk: mci1_clk@26 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <26>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tssc0_clk: ssc0_clk@28 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <28>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\trstc@fffffe00 {\n+\t\t\t\tcompatible = \"atmel,at91sam9g45-rstc\";\n+\t\t\t\treg = <0xfffffe00 0x10>;\n+\t\t\t\tclocks = <&clk32k>;\n+\t\t\t};\n+\n+\t\t\tshdwc@fffffe10 {\n+\t\t\t\tcompatible = \"atmel,at91sam9x5-shdwc\";\n+\t\t\t\treg = <0xfffffe10 0x10>;\n+\t\t\t\tclocks = <&clk32k>;\n+\t\t\t};\n+\n+\t\t\tpit: timer@fffffe30 {\n+\t\t\t\tcompatible = \"atmel,at91sam9260-pit\";\n+\t\t\t\treg = <0xfffffe30 0xf>;\n+\t\t\t\tinterrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;\n+\t\t\t\tclocks = <&mck>;\n+\t\t\t};\n+\n+\t\t\tsckc@fffffe50 {\n+\t\t\t\tcompatible = \"atmel,at91sam9x5-sckc\";\n+\t\t\t\treg = <0xfffffe50 0x4>;\n+\n+\t\t\t\tslow_osc: slow_osc {\n+\t\t\t\t\tcompatible = \"atmel,at91sam9x5-clk-slow-osc\";\n+\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\tclocks = <&slow_xtal>;\n+\t\t\t\t};\n+\n+\t\t\t\tslow_rc_osc: slow_rc_osc {\n+\t\t\t\t\tcompatible = \"atmel,at91sam9x5-clk-slow-rc-osc\";\n+\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\tclock-frequency = <32768>;\n+\t\t\t\t\tclock-accuracy = <50000000>;\n+\t\t\t\t};\n+\n+\t\t\t\tclk32k: slck {\n+\t\t\t\t\tcompatible = \"atmel,at91sam9x5-clk-slow\";\n+\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\tclocks = <&slow_rc_osc>, <&slow_osc>;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\ttcb0: timer@f8008000 {\n+\t\t\t\tcompatible = \"atmel,at91sam9x5-tcb\";\n+\t\t\t\treg = <0xf8008000 0x100>;\n+\t\t\t\tinterrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\t\tclocks = <&tcb0_clk>, <&clk32k>;\n+\t\t\t\tclock-names = \"t0_clk\", \"slow_clk\";\n+\t\t\t};\n+\n+\t\t\ttcb1: timer@f800c000 {\n+\t\t\t\tcompatible = \"atmel,at91sam9x5-tcb\";\n+\t\t\t\treg = <0xf800c000 0x100>;\n+\t\t\t\tinterrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\t\tclocks = <&tcb0_clk>, <&clk32k>;\n+\t\t\t\tclock-names = \"t0_clk\", \"slow_clk\";\n+\t\t\t};\n+\n+\t\t\tdma0: dma-controller@ffffec00 {\n+\t\t\t\tcompatible = \"atmel,at91sam9g45-dma\";\n+\t\t\t\treg = <0xffffec00 0x200>;\n+\t\t\t\tinterrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\t\t#dma-cells = <2>;\n+\t\t\t\tclocks = <&dma0_clk>;\n+\t\t\t\tclock-names = \"dma_clk\";\n+\t\t\t};\n+\n+\t\t\tdma1: dma-controller@ffffee00 {\n+\t\t\t\tcompatible = \"atmel,at91sam9g45-dma\";\n+\t\t\t\treg = <0xffffee00 0x200>;\n+\t\t\t\tinterrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\t\t#dma-cells = <2>;\n+\t\t\t\tclocks = <&dma1_clk>;\n+\t\t\t\tclock-names = \"dma_clk\";\n+\t\t\t};\n+\n+\t\t\tpinctrl@fffff400 {\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <1>;\n+\t\t\t\tcompatible = \"atmel,at91sam9x5-pinctrl\", \"atmel,at91rm9200-pinctrl\", \"simple-bus\";\n+\t\t\t\tranges = <0xfffff400 0xfffff400 0x800>;\n+\t\t\t\treg = <0xfffff400 0x200\t\t/* pioA */\n+\t\t\t\t 0xfffff600 0x200\t\t/* pioB */\n+\t\t\t\t 0xfffff800 0x200\t\t/* pioC */\n+\t\t\t\t 0xfffffa00 0x200\t\t/* pioD */\n+\t\t\t\t >;\n+\n+\t\t\t\t/* shared pinctrl settings */\n+\t\t\t\tdbgu {\n+\t\t\t\t\tpinctrl_dbgu: dbgu-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tusart0 {\n+\t\t\t\t\tpinctrl_usart0: usart0-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PA1 periph A */\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_usart0_rts: usart0_rts-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PA2 periph A */\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_usart0_cts: usart0_cts-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PA3 periph A */\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_usart0_sck: usart0_sck-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PA4 periph A */\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tusart1 {\n+\t\t\t\t\tpinctrl_usart1: usart1-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PA6 periph A */\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_usart1_rts: usart1_rts-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PC27 periph C */\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_usart1_cts: usart1_cts-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PC28 periph C */\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_usart1_sck: usart1_sck-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PC29 periph C */\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tusart2 {\n+\t\t\t\t\tpinctrl_usart2: usart2-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PA8 periph A */\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_usart2_rts: usart2_rts-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PB0 periph B */\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_usart2_cts: usart2_cts-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PB1 periph B */\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_usart2_sck: usart2_sck-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PB2 periph B */\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tuart0 {\n+\t\t\t\t\tpinctrl_uart0: uart0-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PC9 periph C with pullup */\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tuart1 {\n+\t\t\t\t\tpinctrl_uart1: uart1-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PC17 periph C with pullup */\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tnand {\n+\t\t\t\t\tpinctrl_nand: nand-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PD13 periph A Data bit 7 */\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_nand_16bits: nand_16bits-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PD21 periph A Data bit 15 */\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tmmc0 {\n+\t\t\t\t\tpinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PA15 periph A with pullup */\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PA20 periph A with pullup */\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tmmc1 {\n+\t\t\t\t\tpinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PA11 periph B with pullup */\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PA4 periph B with pullup */\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tssc0 {\n+\t\t\t\t\tpinctrl_ssc0_tx: ssc0_tx-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PA26 periph B */\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_ssc0_rx: ssc0_rx-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PA29 periph B */\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tspi0 {\n+\t\t\t\t\tpinctrl_spi0: spi0-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PA13 periph A SPI0_SPCK pin */\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tspi1 {\n+\t\t\t\t\tpinctrl_spi1: spi1-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PA23 periph B SPI1_SPCK pin */\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\ti2c0 {\n+\t\t\t\t\tpinctrl_i2c0: i2c0-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PA31 periph A I2C0 clock */\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\ti2c1 {\n+\t\t\t\t\tpinctrl_i2c1: i2c1-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PC1 periph C I2C1 clock */\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\ti2c2 {\n+\t\t\t\t\tpinctrl_i2c2: i2c2-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PB5 periph B I2C2 clock */\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\ti2c_gpio0 {\n+\t\t\t\t\tpinctrl_i2c_gpio0: i2c_gpio0-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PA31 gpio multidrive I2C0 clock */\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\ti2c_gpio1 {\n+\t\t\t\t\tpinctrl_i2c_gpio1: i2c_gpio1-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PC1 gpio multidrive I2C1 clock */\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\ti2c_gpio2 {\n+\t\t\t\t\tpinctrl_i2c_gpio2: i2c_gpio2-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PB5 gpio multidrive I2C2 clock */\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tpwm0 {\n+\t\t\t\t\tpinctrl_pwm0_pwm0_0: pwm0_pwm0-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\n+\t\t\t\t\t};\n+\t\t\t\t\tpinctrl_pwm0_pwm0_1: pwm0_pwm0-1 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\n+\t\t\t\t\t};\n+\t\t\t\t\tpinctrl_pwm0_pwm0_2: pwm0_pwm0-2 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_pwm0_pwm1_0: pwm0_pwm1-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\n+\t\t\t\t\t};\n+\t\t\t\t\tpinctrl_pwm0_pwm1_1: pwm0_pwm1-1 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\n+\t\t\t\t\t};\n+\t\t\t\t\tpinctrl_pwm0_pwm1_2: pwm0_pwm1-2 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_pwm0_pwm2_0: pwm0_pwm2-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\n+\t\t\t\t\t};\n+\t\t\t\t\tpinctrl_pwm0_pwm2_1: pwm0_pwm2-1 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_pwm0_pwm3_0: pwm0_pwm3-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\n+\t\t\t\t\t};\n+\t\t\t\t\tpinctrl_pwm0_pwm3_1: pwm0_pwm3-1 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\ttcb0 {\n+\t\t\t\t\tpinctrl_tcb0_tclk0: tcb0_tclk0-0 {\n+\t\t\t\t\t\tatmel,pins = ;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_tcb0_tclk1: tcb0_tclk1-0 {\n+\t\t\t\t\t\tatmel,pins = ;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_tcb0_tclk2: tcb0_tclk2-0 {\n+\t\t\t\t\t\tatmel,pins = ;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_tcb0_tioa0: tcb0_tioa0-0 {\n+\t\t\t\t\t\tatmel,pins = ;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_tcb0_tioa1: tcb0_tioa1-0 {\n+\t\t\t\t\t\tatmel,pins = ;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_tcb0_tioa2: tcb0_tioa2-0 {\n+\t\t\t\t\t\tatmel,pins = ;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_tcb0_tiob0: tcb0_tiob0-0 {\n+\t\t\t\t\t\tatmel,pins = ;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_tcb0_tiob1: tcb0_tiob1-0 {\n+\t\t\t\t\t\tatmel,pins = ;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_tcb0_tiob2: tcb0_tiob2-0 {\n+\t\t\t\t\t\tatmel,pins = ;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\ttcb1 {\n+\t\t\t\t\tpinctrl_tcb1_tclk0: tcb1_tclk0-0 {\n+\t\t\t\t\t\tatmel,pins = ;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_tcb1_tclk1: tcb1_tclk1-0 {\n+\t\t\t\t\t\tatmel,pins = ;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_tcb1_tclk2: tcb1_tclk2-0 {\n+\t\t\t\t\t\tatmel,pins = ;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_tcb1_tioa0: tcb1_tioa0-0 {\n+\t\t\t\t\t\tatmel,pins = ;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_tcb1_tioa1: tcb1_tioa1-0 {\n+\t\t\t\t\t\tatmel,pins = ;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_tcb1_tioa2: tcb1_tioa2-0 {\n+\t\t\t\t\t\tatmel,pins = ;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_tcb1_tiob0: tcb1_tiob0-0 {\n+\t\t\t\t\t\tatmel,pins = ;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_tcb1_tiob1: tcb1_tiob1-0 {\n+\t\t\t\t\t\tatmel,pins = ;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_tcb1_tiob2: tcb1_tiob2-0 {\n+\t\t\t\t\t\tatmel,pins = ;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tpioA: gpio@fffff400 {\n+\t\t\t\tcompatible = \"atmel,at91sam9x5-gpio\", \"atmel,at91rm9200-gpio\";\n+\t\t\t\treg = <0xfffff400 0x200>;\n+\t\t\t\tinterrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\tinterrupt-controller;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tclocks = <&pioAB_clk>;\n+\t\t\t};\n+\n+\t\t\tpioB: gpio@fffff600 {\n+\t\t\t\tcompatible = \"atmel,at91sam9x5-gpio\", \"atmel,at91rm9200-gpio\";\n+\t\t\t\treg = <0xfffff600 0x200>;\n+\t\t\t\tinterrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-lines = <19>;\n+\t\t\t\tinterrupt-controller;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tclocks = <&pioAB_clk>;\n+\t\t\t};\n+\n+\t\t\tpioC: gpio@fffff800 {\n+\t\t\t\tcompatible = \"atmel,at91sam9x5-gpio\", \"atmel,at91rm9200-gpio\";\n+\t\t\t\treg = <0xfffff800 0x200>;\n+\t\t\t\tinterrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\tinterrupt-controller;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tclocks = <&pioCD_clk>;\n+\t\t\t};\n+\n+\t\t\tpioD: gpio@fffffa00 {\n+\t\t\t\tcompatible = \"atmel,at91sam9x5-gpio\", \"atmel,at91rm9200-gpio\";\n+\t\t\t\treg = <0xfffffa00 0x200>;\n+\t\t\t\tinterrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;\n+\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-lines = <22>;\n+\t\t\t\tinterrupt-controller;\n+\t\t\t\t#interrupt-cells = <2>;\n+\t\t\t\tclocks = <&pioCD_clk>;\n+\t\t\t};\n+\n+\t\t\tssc0: ssc@f0010000 {\n+\t\t\t\tcompatible = \"atmel,at91sam9g45-ssc\";\n+\t\t\t\treg = <0xf0010000 0x4000>;\n+\t\t\t\tinterrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;\n+\t\t\t\tdmas = <&dma0 1 AT91_DMA_CFG_PER_ID(13)>,\n+\t\t\t\t <&dma0 1 AT91_DMA_CFG_PER_ID(14)>;\n+\t\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;\n+\t\t\t\tclocks = <&ssc0_clk>;\n+\t\t\t\tclock-names = \"pclk\";\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tmmc0: mmc@f0008000 {\n+\t\t\t\tcompatible = \"atmel,hsmci\";\n+\t\t\t\treg = <0xf0008000 0x600>;\n+\t\t\t\tinterrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\t\tdmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>;\n+\t\t\t\tdma-names = \"rxtx\";\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tclocks = <&mci0_clk>;\n+\t\t\t\tclock-names = \"mci_clk\";\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tmmc1: mmc@f000c000 {\n+\t\t\t\tcompatible = \"atmel,hsmci\";\n+\t\t\t\treg = <0xf000c000 0x600>;\n+\t\t\t\tinterrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\t\tdmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>;\n+\t\t\t\tdma-names = \"rxtx\";\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tclocks = <&mci1_clk>;\n+\t\t\t\tclock-names = \"mci_clk\";\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tdbgu: serial@fffff200 {\n+\t\t\t\tcompatible = \"atmel,at91sam9260-dbgu\", \"atmel,at91sam9260-usart\";\n+\t\t\t\treg = <0xfffff200 0x200>;\n+\t\t\t\tinterrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&pinctrl_dbgu>;\n+\t\t\t\tdmas = <&dma1 1 AT91_DMA_CFG_PER_ID(8)>,\n+\t\t\t\t <&dma1 1 (AT91_DMA_CFG_PER_ID(9) | AT91_DMA_CFG_FIFOCFG_ASAP)>;\n+\t\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\t\tclocks = <&mck>;\n+\t\t\t\tclock-names = \"usart\";\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tusart0: serial@f801c000 {\n+\t\t\t\tcompatible = \"atmel,at91sam9260-usart\";\n+\t\t\t\treg = <0xf801c000 0x200>;\n+\t\t\t\tinterrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&pinctrl_usart0>;\n+\t\t\t\tdmas = <&dma0 1 AT91_DMA_CFG_PER_ID(3)>,\n+\t\t\t\t <&dma0 1 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;\n+\t\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\t\tclocks = <&usart0_clk>;\n+\t\t\t\tclock-names = \"usart\";\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tusart1: serial@f8020000 {\n+\t\t\t\tcompatible = \"atmel,at91sam9260-usart\";\n+\t\t\t\treg = <0xf8020000 0x200>;\n+\t\t\t\tinterrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&pinctrl_usart1>;\n+\t\t\t\tdmas = <&dma0 1 AT91_DMA_CFG_PER_ID(5)>,\n+\t\t\t\t <&dma0 1 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>;\n+\t\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\t\tclocks = <&usart1_clk>;\n+\t\t\t\tclock-names = \"usart\";\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tusart2: serial@f8024000 {\n+\t\t\t\tcompatible = \"atmel,at91sam9260-usart\";\n+\t\t\t\treg = <0xf8024000 0x200>;\n+\t\t\t\tinterrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&pinctrl_usart2>;\n+\t\t\t\tdmas = <&dma1 1 AT91_DMA_CFG_PER_ID(12)>,\n+\t\t\t\t <&dma1 1 (AT91_DMA_CFG_PER_ID(13) | AT91_DMA_CFG_FIFOCFG_ASAP)>;\n+\t\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\t\tclocks = <&usart2_clk>;\n+\t\t\t\tclock-names = \"usart\";\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\ti2c0: i2c@f8010000 {\n+\t\t\t\tcompatible = \"atmel,at91sam9x5-i2c\";\n+\t\t\t\treg = <0xf8010000 0x100>;\n+\t\t\t\tinterrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;\n+\t\t\t\tdmas = <&dma0 1 AT91_DMA_CFG_PER_ID(7)>,\n+\t\t\t\t <&dma0 1 AT91_DMA_CFG_PER_ID(8)>;\n+\t\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&pinctrl_i2c0>;\n+\t\t\t\tclocks = <&twi0_clk>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\ti2c1: i2c@f8014000 {\n+\t\t\t\tcompatible = \"atmel,at91sam9x5-i2c\";\n+\t\t\t\treg = <0xf8014000 0x100>;\n+\t\t\t\tinterrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;\n+\t\t\t\tdmas = <&dma1 1 AT91_DMA_CFG_PER_ID(5)>,\n+\t\t\t\t <&dma1 1 AT91_DMA_CFG_PER_ID(6)>;\n+\t\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&pinctrl_i2c1>;\n+\t\t\t\tclocks = <&twi1_clk>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\ti2c2: i2c@f8018000 {\n+\t\t\t\tcompatible = \"atmel,at91sam9x5-i2c\";\n+\t\t\t\treg = <0xf8018000 0x100>;\n+\t\t\t\tinterrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;\n+\t\t\t\tdmas = <&dma0 1 AT91_DMA_CFG_PER_ID(9)>,\n+\t\t\t\t <&dma0 1 AT91_DMA_CFG_PER_ID(10)>;\n+\t\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&pinctrl_i2c2>;\n+\t\t\t\tclocks = <&twi2_clk>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tuart0: serial@f8040000 {\n+\t\t\t\tcompatible = \"atmel,at91sam9260-usart\";\n+\t\t\t\treg = <0xf8040000 0x200>;\n+\t\t\t\tinterrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&pinctrl_uart0>;\n+\t\t\t\tclocks = <&uart0_clk>;\n+\t\t\t\tclock-names = \"usart\";\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tuart1: serial@f8044000 {\n+\t\t\t\tcompatible = \"atmel,at91sam9260-usart\";\n+\t\t\t\treg = <0xf8044000 0x200>;\n+\t\t\t\tinterrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&pinctrl_uart1>;\n+\t\t\t\tclocks = <&uart1_clk>;\n+\t\t\t\tclock-names = \"usart\";\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tadc0: adc@f804c000 {\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tcompatible = \"atmel,at91sam9x5-adc\";\n+\t\t\t\treg = <0xf804c000 0x100>;\n+\t\t\t\tinterrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\t\tclocks = <&adc_clk>,\n+\t\t\t\t\t <&adc_op_clk>;\n+\t\t\t\tclock-names = \"adc_clk\", \"adc_op_clk\";\n+\t\t\t\tatmel,adc-use-external-triggers;\n+\t\t\t\tatmel,adc-channels-used = <0xffff>;\n+\t\t\t\tatmel,adc-vref = <3300>;\n+\t\t\t\tatmel,adc-startup-time = <40>;\n+\t\t\t\tatmel,adc-sample-hold-time = <11>;\n+\t\t\t\tatmel,adc-res = <8 10>;\n+\t\t\t\tatmel,adc-res-names = \"lowres\", \"highres\";\n+\t\t\t\tatmel,adc-use-res = \"highres\";\n+\n+\t\t\t\ttrigger0 {\n+\t\t\t\t\ttrigger-name = \"external-rising\";\n+\t\t\t\t\ttrigger-value = <0x1>;\n+\t\t\t\t\ttrigger-external;\n+\t\t\t\t};\n+\n+\t\t\t\ttrigger1 {\n+\t\t\t\t\ttrigger-name = \"external-falling\";\n+\t\t\t\t\ttrigger-value = <0x2>;\n+\t\t\t\t\ttrigger-external;\n+\t\t\t\t};\n+\n+\t\t\t\ttrigger2 {\n+\t\t\t\t\ttrigger-name = \"external-any\";\n+\t\t\t\t\ttrigger-value = <0x3>;\n+\t\t\t\t\ttrigger-external;\n+\t\t\t\t};\n+\n+\t\t\t\ttrigger3 {\n+\t\t\t\t\ttrigger-name = \"continuous\";\n+\t\t\t\t\ttrigger-value = <0x6>;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tspi0: spi@f0000000 {\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tcompatible = \"atmel,at91rm9200-spi\";\n+\t\t\t\treg = <0xf0000000 0x100>;\n+\t\t\t\tinterrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;\n+\t\t\t\tdmas = <&dma0 1 AT91_DMA_CFG_PER_ID(1)>,\n+\t\t\t\t <&dma0 1 AT91_DMA_CFG_PER_ID(2)>;\n+\t\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&pinctrl_spi0>;\n+\t\t\t\tclocks = <&spi0_clk>;\n+\t\t\t\tclock-names = \"spi_clk\";\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tspi1: spi@f0004000 {\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tcompatible = \"atmel,at91rm9200-spi\";\n+\t\t\t\treg = <0xf0004000 0x100>;\n+\t\t\t\tinterrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;\n+\t\t\t\tdmas = <&dma1 1 AT91_DMA_CFG_PER_ID(1)>,\n+\t\t\t\t <&dma1 1 AT91_DMA_CFG_PER_ID(2)>;\n+\t\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&pinctrl_spi1>;\n+\t\t\t\tclocks = <&spi1_clk>;\n+\t\t\t\tclock-names = \"spi_clk\";\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tusb2: gadget@f803c000 {\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tcompatible = \"atmel,at91sam9g45-udc\";\n+\t\t\t\treg = <0x00500000 0x80000\n+\t\t\t\t 0xf803c000 0x400>;\n+\t\t\t\tinterrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\t\tclocks = <&utmi>, <&udphs_clk>;\n+\t\t\t\tclock-names = \"hclk\", \"pclk\";\n+\t\t\t\tstatus = \"disabled\";\n+\n+\t\t\t\tep@0 {\n+\t\t\t\t\treg = <0>;\n+\t\t\t\t\tatmel,fifo-size = <64>;\n+\t\t\t\t\tatmel,nb-banks = <1>;\n+\t\t\t\t};\n+\n+\t\t\t\tep@1 {\n+\t\t\t\t\treg = <1>;\n+\t\t\t\t\tatmel,fifo-size = <1024>;\n+\t\t\t\t\tatmel,nb-banks = <2>;\n+\t\t\t\t\tatmel,can-dma;\n+\t\t\t\t\tatmel,can-isoc;\n+\t\t\t\t};\n+\n+\t\t\t\tep@2 {\n+\t\t\t\t\treg = <2>;\n+\t\t\t\t\tatmel,fifo-size = <1024>;\n+\t\t\t\t\tatmel,nb-banks = <2>;\n+\t\t\t\t\tatmel,can-dma;\n+\t\t\t\t\tatmel,can-isoc;\n+\t\t\t\t};\n+\n+\t\t\t\tep@3 {\n+\t\t\t\t\treg = <3>;\n+\t\t\t\t\tatmel,fifo-size = <1024>;\n+\t\t\t\t\tatmel,nb-banks = <3>;\n+\t\t\t\t\tatmel,can-dma;\n+\t\t\t\t};\n+\n+\t\t\t\tep@4 {\n+\t\t\t\t\treg = <4>;\n+\t\t\t\t\tatmel,fifo-size = <1024>;\n+\t\t\t\t\tatmel,nb-banks = <3>;\n+\t\t\t\t\tatmel,can-dma;\n+\t\t\t\t};\n+\n+\t\t\t\tep@5 {\n+\t\t\t\t\treg = <5>;\n+\t\t\t\t\tatmel,fifo-size = <1024>;\n+\t\t\t\t\tatmel,nb-banks = <3>;\n+\t\t\t\t\tatmel,can-dma;\n+\t\t\t\t\tatmel,can-isoc;\n+\t\t\t\t};\n+\n+\t\t\t\tep@6 {\n+\t\t\t\t\treg = <6>;\n+\t\t\t\t\tatmel,fifo-size = <1024>;\n+\t\t\t\t\tatmel,nb-banks = <3>;\n+\t\t\t\t\tatmel,can-dma;\n+\t\t\t\t\tatmel,can-isoc;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\twatchdog@fffffe40 {\n+\t\t\t\tcompatible = \"atmel,at91sam9260-wdt\";\n+\t\t\t\treg = <0xfffffe40 0x10>;\n+\t\t\t\tinterrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;\n+\t\t\t\tclocks = <&clk32k>;\n+\t\t\t\tatmel,watchdog-type = \"hardware\";\n+\t\t\t\tatmel,reset-type = \"all\";\n+\t\t\t\tatmel,dbg-halt;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\trtc@fffffeb0 {\n+\t\t\t\tcompatible = \"atmel,at91sam9x5-rtc\";\n+\t\t\t\treg = <0xfffffeb0 0x40>;\n+\t\t\t\tinterrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;\n+\t\t\t\tclocks = <&clk32k>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tpwm0: pwm@f8034000 {\n+\t\t\t\tcompatible = \"atmel,at91sam9rl-pwm\";\n+\t\t\t\treg = <0xf8034000 0x300>;\n+\t\t\t\tinterrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;\n+\t\t\t\tclocks = <&pwm_clk>;\n+\t\t\t\t#pwm-cells = <3>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\t\t};\n+\n+\t\tnand0: nand@40000000 {\n+\t\t\tcompatible = \"atmel,at91rm9200-nand\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\treg = <0x40000000 0x10000000\n+\t\t\t 0xffffe000 0x600\t\t/* PMECC Registers */\n+\t\t\t 0xffffe600 0x200\t\t/* PMECC Error Location Registers */\n+\t\t\t 0x00108000 0x18000\t/* PMECC looup table in ROM code */\n+\t\t\t >;\n+\t\t\tatmel,pmecc-lookup-table-offset = <0x0 0x8000>;\n+\t\t\tatmel,nand-addr-offset = <21>;\n+\t\t\tatmel,nand-cmd-offset = <22>;\n+\t\t\tatmel,nand-has-dma;\n+\t\t\tpinctrl-names = \"default\";\n+\t\t\tpinctrl-0 = <&pinctrl_nand>;\n+\t\t\tgpios = <&pioD 5 GPIO_ACTIVE_HIGH\n+\t\t\t\t &pioD 4 GPIO_ACTIVE_HIGH\n+\t\t\t\t 0\n+\t\t\t\t>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tusb0: ohci@00600000 {\n+\t\t\tcompatible = \"atmel,at91rm9200-ohci\", \"usb-ohci\";\n+\t\t\treg = <0x00600000 0x100000>;\n+\t\t\tinterrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;\n+\t\t\tclocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;\n+\t\t\tclock-names = \"ohci_clk\", \"hclk\", \"uhpck\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tusb1: ehci@00700000 {\n+\t\t\tcompatible = \"atmel,at91sam9g45-ehci\", \"usb-ehci\";\n+\t\t\treg = <0x00700000 0x100000>;\n+\t\t\tinterrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;\n+\t\t\tclocks = <&utmi>, <&uhphs_clk>;\n+\t\t\tclock-names = \"usb_clk\", \"ehci_clk\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+\n+\ti2c-gpio-0 {\n+\t\tcompatible = \"i2c-gpio\";\n+\t\tgpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */\n+\t\t\t &pioA 31 GPIO_ACTIVE_HIGH /* scl */\n+\t\t\t>;\n+\t\ti2c-gpio,sda-open-drain;\n+\t\ti2c-gpio,scl-open-drain;\n+\t\ti2c-gpio,delay-us = <2>;\t/* ~100 kHz */\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pinctrl_i2c_gpio0>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\ti2c-gpio-1 {\n+\t\tcompatible = \"i2c-gpio\";\n+\t\tgpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */\n+\t\t\t &pioC 1 GPIO_ACTIVE_HIGH /* scl */\n+\t\t\t>;\n+\t\ti2c-gpio,sda-open-drain;\n+\t\ti2c-gpio,scl-open-drain;\n+\t\ti2c-gpio,delay-us = <2>;\t/* ~100 kHz */\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pinctrl_i2c_gpio1>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\ti2c-gpio-2 {\n+\t\tcompatible = \"i2c-gpio\";\n+\t\tgpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */\n+\t\t\t &pioB 5 GPIO_ACTIVE_HIGH /* scl */\n+\t\t\t>;\n+\t\ti2c-gpio,sda-open-drain;\n+\t\ti2c-gpio,scl-open-drain;\n+\t\ti2c-gpio,delay-us = <2>;\t/* ~100 kHz */\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pinctrl_i2c_gpio2>;\n+\t\tstatus = \"disabled\";\n+\t};\n+};\ndiff --git a/arch/arm/dts/at91sam9x5_can.dtsi b/arch/arm/dts/at91sam9x5_can.dtsi\nnew file mode 100644\nindex 0000000000..9727b771d1\n--- /dev/null\n+++ b/arch/arm/dts/at91sam9x5_can.dtsi\n@@ -0,0 +1,71 @@\n+/*\n+ * at91sam9x5_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1\n+ * Ethernet interface.\n+ *\n+ * Copyright (C) 2013 Boris BREZILLON \n+ *\n+ * Licensed under GPLv2.\n+ */\n+\n+#include \n+#include \n+\n+/ {\n+\tahb {\n+\t\tapb {\n+\t\t\tpmc: pmc@fffffc00 {\n+\t\t\t\tperiphck {\n+\t\t\t\t\tcan0_clk: can0_clk@29 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <29>;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tcan1_clk: can1_clk@30 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <30>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tcan0: can@f8000000 {\n+\t\t\t\tcompatible = \"atmel,at91sam9x5-can\";\n+\t\t\t\treg = <0xf8000000 0x300>;\n+\t\t\t\tinterrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&pinctrl_can0_rx_tx>;\n+\t\t\t\tclocks = <&can0_clk>;\n+\t\t\t\tclock-names = \"can_clk\";\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tcan1: can@f8004000 {\n+\t\t\t\tcompatible = \"atmel,at91sam9x5-can\";\n+\t\t\t\treg = <0xf8004000 0x300>;\n+\t\t\t\tinterrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&pinctrl_can1_rx_tx>;\n+\t\t\t\tclocks = <&can1_clk>;\n+\t\t\t\tclock-names = \"can_clk\";\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tpinctrl@fffff400 {\n+\t\t\t\tcan0 {\n+\t\t\t\t\tpinctrl_can0_rx_tx: can0_rx_tx {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* CANTX0, conflicts with DTXD */\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tcan1 {\n+\t\t\t\t\tpinctrl_can1_rx_tx: can1_rx_tx {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* CANTX1, conflicts with TXD1 */\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/dts/at91sam9x5_isi.dtsi b/arch/arm/dts/at91sam9x5_isi.dtsi\nnew file mode 100644\nindex 0000000000..2c5075f8c3\n--- /dev/null\n+++ b/arch/arm/dts/at91sam9x5_isi.dtsi\n@@ -0,0 +1,72 @@\n+/*\n+ * at91sam9x5_isi.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an\n+ * Image Sensor Interface.\n+ *\n+ * Copyright (C) 2013 Boris BREZILLON \n+ *\n+ * Licensed under GPLv2.\n+ */\n+\n+#include \n+#include \n+\n+/ {\n+\tahb {\n+\t\tapb {\n+\t\t\tpinctrl@fffff400 {\n+\t\t\t\tisi {\n+\t\t\t\t\tpinctrl_isi_data_0_7: isi-0-data-0-7 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* ISI_VSYNC, conflicts with LCDDAT13 */\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_isi_data_8_9: isi-0-data-8-9 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* ISI_D9, conflicts with LCDDAT9 */\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_isi_data_10_11: isi-0-data-10-11 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* ISI_D11, conflicts with LCDDAT11 */\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tpmc: pmc@fffffc00 {\n+\t\t\t\tperiphck {\n+\t\t\t\t\tisi_clk: isi_clk@25 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <25>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tisi: isi@f8048000 {\n+\t\t\t\tcompatible = \"atmel,at91sam9g45-isi\";\n+\t\t\t\treg = <0xf8048000 0x4000>;\n+\t\t\t\tinterrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&pinctrl_isi_data_0_7>;\n+\t\t\t\tclocks = <&isi_clk>;\n+\t\t\t\tclock-names = \"isi_clk\";\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t\tport {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/dts/at91sam9x5_lcd.dtsi b/arch/arm/dts/at91sam9x5_lcd.dtsi\nnew file mode 100644\nindex 0000000000..41e87589fb\n--- /dev/null\n+++ b/arch/arm/dts/at91sam9x5_lcd.dtsi\n@@ -0,0 +1,165 @@\n+/*\n+ * at91sam9x5_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an\n+ * LCD controller.\n+ *\n+ * Copyright (C) 2013 Boris BREZILLON \n+ *\n+ * Licensed under GPLv2.\n+ */\n+\n+#include \n+#include \n+\n+/ {\n+\tahb {\n+\t\tapb {\n+\t\t\thlcdc: hlcdc@f8038000 {\n+\t\t\t\tcompatible = \"atmel,at91sam9x5-hlcdc\";\n+\t\t\t\treg = <0xf8038000 0x4000>;\n+\t\t\t\tinterrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;\n+\t\t\t\tclocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;\n+\t\t\t\tclock-names = \"periph_clk\",\"sys_clk\", \"slow_clk\";\n+\t\t\t\tstatus = \"disabled\";\n+\n+\t\t\t\thlcdc-display-controller {\n+\t\t\t\t\tcompatible = \"atmel,hlcdc-display-controller\";\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\n+\t\t\t\t\tport@0 {\n+\t\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t\t#size-cells = <0>;\n+\t\t\t\t\t\treg = <0>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\thlcdc_pwm: hlcdc-pwm {\n+\t\t\t\t\tcompatible = \"atmel,hlcdc-pwm\";\n+\t\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\t\tpinctrl-0 = <&pinctrl_lcd_pwm>;\n+\t\t\t\t\t#pwm-cells = <3>;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tpinctrl@fffff400 {\n+\t\t\t\tlcd {\n+\t\t\t\t\tpinctrl_lcd_base: lcd-base-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* LCDPCK */\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_lcd_pwm: lcd-pwm-0 {\n+\t\t\t\t\t\tatmel,pins = ;\t/* LCDPWM */\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_lcd_rgb444: lcd-rgb-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* LCDD11 pin */\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_lcd_rgb565: lcd-rgb-1 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* LCDD15 pin */\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_lcd_rgb666: lcd-rgb-2 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* LCDD17 pin */\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_lcd_rgb888: lcd-rgb-3 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* LCDD23 pin */\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tpmc: pmc@fffffc00 {\n+\t\t\t\tperiphck {\n+\t\t\t\t\tlcdc_clk: lcdc_clk@25 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <25>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tsystemck {\n+\t\t\t\t\tlcdck: lcdck@3 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <3>;\n+\t\t\t\t\t\tclocks = <&mck>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/dts/at91sam9x5_macb0.dtsi b/arch/arm/dts/at91sam9x5_macb0.dtsi\nnew file mode 100644\nindex 0000000000..1540e60232\n--- /dev/null\n+++ b/arch/arm/dts/at91sam9x5_macb0.dtsi\n@@ -0,0 +1,67 @@\n+/*\n+ * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1\n+ * Ethernet interface.\n+ *\n+ * Copyright (C) 2013 Boris BREZILLON \n+ *\n+ * Licensed under GPLv2.\n+ */\n+\n+#include \n+#include \n+\n+/ {\n+\tahb {\n+\t\tapb {\n+\t\t\tpinctrl@fffff400 {\n+\t\t\t\tmacb0 {\n+\t\t\t\t\tpinctrl_macb0_rmii: macb0_rmii-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PB10 periph A */\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PB17 periph A */\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tpmc: pmc@fffffc00 {\n+\t\t\t\tperiphck {\n+\t\t\t\t\tmacb0_clk: macb0_clk@24 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <24>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tmacb0: ethernet@f802c000 {\n+\t\t\t\tcompatible = \"cdns,at91sam9260-macb\", \"cdns,macb\";\n+\t\t\t\treg = <0xf802c000 0x100>;\n+\t\t\t\tinterrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&pinctrl_macb0_rmii>;\n+\t\t\t\tclocks = <&macb0_clk>, <&macb0_clk>;\n+\t\t\t\tclock-names = \"hclk\", \"pclk\";\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/dts/at91sam9x5_macb1.dtsi b/arch/arm/dts/at91sam9x5_macb1.dtsi\nnew file mode 100644\nindex 0000000000..be2eab4b9c\n--- /dev/null\n+++ b/arch/arm/dts/at91sam9x5_macb1.dtsi\n@@ -0,0 +1,55 @@\n+/*\n+ * at91sam9x5_macb1.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 2\n+ * Ethernet interfaces.\n+ *\n+ * Copyright (C) 2013 Boris BREZILLON \n+ *\n+ * Licensed under GPLv2.\n+ */\n+\n+#include \n+#include \n+\n+/ {\n+\tahb {\n+\t\tapb {\n+\t\t\tpinctrl@fffff400 {\n+\t\t\t\tmacb1 {\n+\t\t\t\t\tpinctrl_macb1_rmii: macb1_rmii-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PC31 periph B */\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tpmc: pmc@fffffc00 {\n+\t\t\t\tperiphck {\n+\t\t\t\t\tmacb1_clk: macb1_clk@27 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <27>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tmacb1: ethernet@f8030000 {\n+\t\t\t\tcompatible = \"cdns,at91sam9260-macb\", \"cdns,macb\";\n+\t\t\t\treg = <0xf8030000 0x100>;\n+\t\t\t\tinterrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&pinctrl_macb1_rmii>;\n+\t\t\t\tclocks = <&macb1_clk>, <&macb1_clk>;\n+\t\t\t\tclock-names = \"hclk\", \"pclk\";\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/dts/at91sam9x5_usart3.dtsi b/arch/arm/dts/at91sam9x5_usart3.dtsi\nnew file mode 100644\nindex 0000000000..5259219077\n--- /dev/null\n+++ b/arch/arm/dts/at91sam9x5_usart3.dtsi\n@@ -0,0 +1,69 @@\n+/*\n+ * at91sam9x5_usart3.dtsi - Device Tree Include file for AT91SAM9x5 SoC with\n+ * 4 USART.\n+ *\n+ * Copyright (C) 2013 Boris BREZILLON \n+ *\n+ * Licensed under GPLv2.\n+ */\n+\n+#include \n+#include \n+\n+/ {\n+\taliases {\n+\t\tserial4 = &usart3;\n+\t};\n+\n+\tahb {\n+\t\tapb {\n+\t\t\tpinctrl@fffff400 {\n+\t\t\t\tusart3 {\n+\t\t\t\t\tpinctrl_usart3: usart3-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t\t/* PC23 periph B */\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_usart3_rts: usart3_rts-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t\t/* PC24 periph B */\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_usart3_cts: usart3_cts-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t\t/* PC25 periph B */\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_usart3_sck: usart3_sck-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t\t/* PC26 periph B */\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tpmc: pmc@fffffc00 {\n+\t\t\t\tperiphck {\n+\t\t\t\t\tusart3_clk: usart3_clk@8 {\n+\t\t\t\t\t\t#clock-cells = <0>;\n+\t\t\t\t\t\treg = <8>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tusart3: serial@f8028000 {\n+\t\t\t\tcompatible = \"atmel,at91sam9260-usart\";\n+\t\t\t\treg = <0xf8028000 0x200>;\n+\t\t\t\tinterrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&pinctrl_usart3>;\n+\t\t\t\tdmas = <&dma1 1 AT91_DMA_CFG_PER_ID(14)>,\n+\t\t\t\t <&dma1 1 (AT91_DMA_CFG_PER_ID(15) | AT91_DMA_CFG_FIFOCFG_ASAP)>;\n+\t\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\t\tclocks = <&usart3_clk>;\n+\t\t\t\tclock-names = \"usart\";\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/dts/at91sam9x5cm.dtsi b/arch/arm/dts/at91sam9x5cm.dtsi\nnew file mode 100644\nindex 0000000000..b098ad8cd9\n--- /dev/null\n+++ b/arch/arm/dts/at91sam9x5cm.dtsi\n@@ -0,0 +1,100 @@\n+/*\n+ * at91sam9x5cm.dtsi - Device Tree Include file for AT91SAM9x5 CPU Module\n+ *\n+ * Copyright (C) 2012 Atmel,\n+ * 2012 Nicolas Ferre \n+ *\n+ * Licensed under GPLv2 or later.\n+ */\n+\n+/ {\n+\tmemory {\n+\t\treg = <0x20000000 0x8000000>;\n+\t};\n+\n+\tclocks {\n+\t\tslow_xtal {\n+\t\t\tclock-frequency = <32768>;\n+\t\t};\n+\n+\t\tmain_xtal {\n+\t\t\tclock-frequency = <12000000>;\n+\t\t};\n+\t};\n+\n+\tahb {\n+\t\tapb {\n+\t\t\tpinctrl@fffff400 {\n+\t\t\t\t1wire_cm {\n+\t\t\t\t\tpinctrl_1wire_cm: 1wire_cm-0 {\n+\t\t\t\t\t\tatmel,pins = ; /* PB18 multidrive, conflicts with led */\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\trtc@fffffeb0 {\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\n+\t\tnand0: nand@40000000 {\n+\t\t\tnand-bus-width = <8>;\n+\t\t\tnand-ecc-mode = \"hw\";\n+\t\t\tatmel,has-pmecc;\t/* Enable PMECC */\n+\t\t\tatmel,pmecc-cap = <2>;\n+\t\t\tatmel,pmecc-sector-size = <512>;\n+\t\t\tnand-on-flash-bbt;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tat91bootstrap@0 {\n+\t\t\t\tlabel = \"at91bootstrap\";\n+\t\t\t\treg = <0x0 0x40000>;\n+\t\t\t};\n+\n+\t\t\tuboot@40000 {\n+\t\t\t\tlabel = \"u-boot\";\n+\t\t\t\treg = <0x40000 0x80000>;\n+\t\t\t};\n+\n+\t\t\tubootenv@c0000 {\n+\t\t\t\tlabel = \"U-Boot Env\";\n+\t\t\t\treg = <0xc0000 0x140000>;\n+\t\t\t};\n+\n+\t\t\tkernel@200000 {\n+\t\t\t\tlabel = \"kernel\";\n+\t\t\t\treg = <0x200000 0x600000>;\n+\t\t\t};\n+\n+\t\t\trootfs@800000 {\n+\t\t\t\tlabel = \"rootfs\";\n+\t\t\t\treg = <0x800000 0x1f800000>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tleds {\n+\t\tcompatible = \"gpio-leds\";\n+\n+\t\tpb18 {\n+\t\t\tlabel = \"pb18\";\n+\t\t\tgpios = <&pioB 18 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,default-trigger = \"heartbeat\";\n+\t\t};\n+\n+\t\tpd21 {\n+\t\t\tlabel = \"pd21\";\n+\t\t\tgpios = <&pioD 21 GPIO_ACTIVE_HIGH>;\n+\t\t};\n+\t};\n+\n+\t1wire_cm {\n+\t\tcompatible = \"w1-gpio\";\n+\t\tgpios = <&pioB 18 GPIO_ACTIVE_HIGH>;\n+\t\tlinux,open-drain;\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pinctrl_1wire_cm>;\n+\t\tstatus = \"okay\";\n+\t};\n+\n+};\ndiff --git a/arch/arm/dts/at91sam9x5dm.dtsi b/arch/arm/dts/at91sam9x5dm.dtsi\nnew file mode 100644\nindex 0000000000..34c089fe0b\n--- /dev/null\n+++ b/arch/arm/dts/at91sam9x5dm.dtsi\n@@ -0,0 +1,101 @@\n+/*\n+ * at91sam9x5dm.dtsi - Device Tree file for SAM9x5 display module\n+ *\n+ * Copyright (C) 2014 Atmel,\n+ * 2014 Free Electrons\n+ *\n+ * Author: Boris Brezillon \n+ *\n+ * Licensed under GPLv2 or later.\n+ */\n+\n+/ {\n+\tahb {\n+\t\tapb {\n+\t\t\ti2c0: i2c@f8010000 {\n+\t\t\t\tqt1070: keyboard@1b {\n+\t\t\t\t\tcompatible = \"qt1070\";\n+\t\t\t\t\treg = <0x1b>;\n+\t\t\t\t\tinterrupt-parent = <&pioA>;\n+\t\t\t\t\tinterrupts = <7 0x0>;\n+\t\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\t\tpinctrl-0 = <&pinctrl_qt1070_irq>;\n+\t\t\t\t\twakeup-source;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\thlcdc: hlcdc@f8038000 {\n+\t\t\t\thlcdc-display-controller {\n+\t\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\t\tpinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;\n+\n+\t\t\t\t\tport@0 {\n+\t\t\t\t\t\thlcdc_panel_output: endpoint@0 {\n+\t\t\t\t\t\t\treg = <0>;\n+\t\t\t\t\t\t\tremote-endpoint = <&panel_input>;\n+\t\t\t\t\t\t};\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tadc0: adc@f804c000 {\n+\t\t\t\tatmel,adc-ts-wires = <4>;\n+\t\t\t\tatmel,adc-ts-pressure-threshold = <10000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\n+\t\t\tpinctrl@fffff400 {\n+\t\t\t\tboard {\n+\t\t\t\t\tpinctrl_qt1070_irq: qt1070_irq {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tbacklight: backlight {\n+\t\tcompatible = \"pwm-backlight\";\n+\t\tpwms = <&hlcdc_pwm 0 50000 0>;\n+\t\tbrightness-levels = <0 4 8 16 32 64 128 255>;\n+\t\tdefault-brightness-level = <6>;\n+\t\tpower-supply = <&bl_reg>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\tbl_reg: backlight_regulator {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"backlight-power-supply\";\n+\t\tregulator-min-microvolt = <5000000>;\n+\t\tregulator-max-microvolt = <5000000>;\n+\t\tstatus = \"disabled\";\n+\t};\n+\n+\tpanel: panel {\n+\t\tcompatible = \"foxlink,fl500wvr00-a0t\", \"simple-panel\";\n+\t\tbacklight = <&backlight>;\n+\t\tpower-supply = <&panel_reg>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tstatus = \"disabled\";\n+\n+\t\tport@0 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tpanel_input: endpoint@0 {\n+\t\t\t\treg = <0>;\n+\t\t\t\tremote-endpoint = <&hlcdc_panel_output>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tpanel_reg: panel_regulator {\n+\t\tcompatible = \"regulator-fixed\";\n+\t\tregulator-name = \"panel-power-supply\";\n+\t\tregulator-min-microvolt = <3300000>;\n+\t\tregulator-max-microvolt = <3300000>;\n+\t\tstatus = \"disabled\";\n+\t};\n+};\ndiff --git a/arch/arm/dts/at91sam9x5ek.dtsi b/arch/arm/dts/at91sam9x5ek.dtsi\nnew file mode 100644\nindex 0000000000..0f1fcd9c28\n--- /dev/null\n+++ b/arch/arm/dts/at91sam9x5ek.dtsi\n@@ -0,0 +1,165 @@\n+/*\n+ * at91sam9x5ek.dtsi - Device Tree file for AT91SAM9x5CM Base board\n+ *\n+ * Copyright (C) 2012 Atmel,\n+ * 2012 Nicolas Ferre \n+ *\n+ * Licensed under GPLv2 or later.\n+ */\n+#include \"at91sam9x5cm.dtsi\"\n+\n+/ {\n+\tmodel = \"Atmel AT91SAM9X5-EK\";\n+\tcompatible = \"atmel,at91sam9x5ek\", \"atmel,at91sam9x5\", \"atmel,at91sam9\";\n+\n+\tchosen {\n+\t\tbootargs = \"root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs\";\n+\t\tstdout-path = \"serial0:115200n8\";\n+\t};\n+\n+\tahb {\n+\t\tapb {\n+\t\t\tmmc0: mmc@f0008000 {\n+\t\t\t\tpinctrl-0 = <\n+\t\t\t\t\t&pinctrl_board_mmc0\n+\t\t\t\t\t&pinctrl_mmc0_slot0_clk_cmd_dat0\n+\t\t\t\t\t&pinctrl_mmc0_slot0_dat1_3>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\tslot@0 {\n+\t\t\t\t\treg = <0>;\n+\t\t\t\t\tbus-width = <4>;\n+\t\t\t\t\tcd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tmmc1: mmc@f000c000 {\n+\t\t\t\tpinctrl-0 = <\n+\t\t\t\t\t&pinctrl_board_mmc1\n+\t\t\t\t\t&pinctrl_mmc1_slot0_clk_cmd_dat0\n+\t\t\t\t\t&pinctrl_mmc1_slot0_dat1_3>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\tslot@0 {\n+\t\t\t\t\treg = <0>;\n+\t\t\t\t\tbus-width = <4>;\n+\t\t\t\t\tcd-gpios = <&pioD 14 GPIO_ACTIVE_HIGH>;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tdbgu: serial@fffff200 {\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\n+\t\t\tusart0: serial@f801c000 {\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\n+\t\t\tusb2: gadget@f803c000 {\n+\t\t\t\tpinctrl-names = \"default\";\n+\t\t\t\tpinctrl-0 = <&pinctrl_board_usb2>;\n+\t\t\t\tatmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\n+\t\t\ti2c0: i2c@f8010000 {\n+\t\t\t\tstatus = \"okay\";\n+\n+\t\t\t\twm8731: wm8731@1a {\n+\t\t\t\t\tcompatible = \"wm8731\";\n+\t\t\t\t\treg = <0x1a>;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tadc0: adc@f804c000 {\n+\t\t\t\tatmel,adc-ts-wires = <4>;\n+\t\t\t\tatmel,adc-ts-pressure-threshold = <10000>;\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\n+\t\t\tpinctrl@fffff400 {\n+\t\t\t\tcamera_sensor {\n+\t\t\t\t\tpinctrl_pck0_as_isi_mck: pck0_as_isi_mck-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* ISI_MCK */\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_sensor_power: sensor_power-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\n+\t\t\t\t\t};\n+\n+\t\t\t\t\tpinctrl_sensor_reset: sensor_reset-0 {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tmmc0 {\n+\t\t\t\t\tpinctrl_board_mmc0: mmc0-board {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PD15 gpio CD pin pull up and deglitch */\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tmmc1 {\n+\t\t\t\t\tpinctrl_board_mmc1: mmc1-board {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t/* PD14 gpio CD pin pull up and deglitch */\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\n+\t\t\t\tusb2 {\n+\t\t\t\t\tpinctrl_board_usb2: usb2-board {\n+\t\t\t\t\t\tatmel,pins =\n+\t\t\t\t\t\t\t;\t\t/* PB16 gpio vbus sense, deglitch */\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tspi0: spi@f0000000 {\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t\tcs-gpios = <&pioA 14 0>, <0>, <0>, <0>;\n+\t\t\t\tspi_flash@0 {\n+\t\t\t\t\tcompatible = \"spi-flash\";\n+\t\t\t\t\tspi-max-frequency = <50000000>;\n+\t\t\t\t\treg = <0>;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\twatchdog@fffffe40 {\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\n+\t\t\tssc0: ssc@f0010000 {\n+\t\t\t\tstatus = \"okay\";\n+\t\t\t};\n+\t\t};\n+\n+\t\tusb0: ohci@00600000 {\n+\t\t\tstatus = \"okay\";\n+\t\t\tnum-ports = <3>;\n+\t\t\tatmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW *//* Activate to have access to port A */\n+\t\t\t\t\t &pioD 19 GPIO_ACTIVE_LOW\n+\t\t\t\t\t &pioD 20 GPIO_ACTIVE_LOW\n+\t\t\t\t\t >;\n+\t\t};\n+\n+\t\tusb1: ehci@00700000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+\n+\tsound {\n+\t\tcompatible = \"atmel,sam9x5-wm8731-audio\";\n+\n+\t\tatmel,model = \"wm8731 @ AT91SAM9X5EK\";\n+\n+\t\tatmel,audio-routing =\n+\t\t\t\"Headphone Jack\", \"RHPOUT\",\n+\t\t\t\"Headphone Jack\", \"LHPOUT\",\n+\t\t\t\"LLINEIN\", \"Line In Jack\",\n+\t\t\t\"RLINEIN\", \"Line In Jack\";\n+\n+\t\tatmel,ssc-controller = <&ssc0>;\n+\t\tatmel,audio-codec = <&wm8731>;\n+\t};\n+};\n","prefixes":["U-Boot","v2"]}