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helo=mx0b-002c1b01.pphosted.com","X-Spam_score_int":"-31","X-Spam_score":"-3.2","X-Spam_bar":"---","X-Spam_report":"(-3.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Writeback modified cpu->isar.idregs[] to KVM after the model is realized.\nWarn if modified bits are not writable by KVM. To facilitate this,\nadd writable_mask to ArmIdReg struct and populate it from\nKVM_ARM_GET_REG_WRITABLE_MASKS during scratch VM creation.\n\nCo-authored-by: Khushit Shah \nSigned-off-by: Shaju Abraham \n---\n target/arm/cpu-idregs.c | 1 +\n target/arm/cpu-idregs.h | 1 +\n target/arm/kvm.c | 160 +++++++++++++++++++++++++++++++++++++++-\n target/arm/trace-events | 1 +\n 4 files changed, 162 insertions(+), 1 deletion(-)","diff":"diff --git a/target/arm/cpu-idregs.c b/target/arm/cpu-idregs.c\nindex 5ffdeb5f21..e8988b7392 100644\n--- a/target/arm/cpu-idregs.c\n+++ b/target/arm/cpu-idregs.c\n@@ -68,6 +68,7 @@\n .name = #reg, \\\n .fields = reg##_fields, \\\n .fields_count = ARRAY_SIZE(reg##_fields), \\\n+ .writable_mask = 0, \\\n },\n \n ArmIdReg arm_idregs[NUM_ID_IDX] = {\ndiff --git a/target/arm/cpu-idregs.h b/target/arm/cpu-idregs.h\nindex 0127bc0a95..eb0d8a1280 100644\n--- a/target/arm/cpu-idregs.h\n+++ b/target/arm/cpu-idregs.h\n@@ -37,6 +37,7 @@ typedef struct ArmIdReg {\n const char *name;\n struct ArmIdRegField *fields;\n uint32_t fields_count;\n+ uint64_t writable_mask;\n } ArmIdReg;\n \n /* Map short register names to canonical _EL1/_EL0 IDX values */\ndiff --git a/target/arm/kvm.c b/target/arm/kvm.c\nindex 7d194ea112..dc64cfbeb6 100644\n--- a/target/arm/kvm.c\n+++ b/target/arm/kvm.c\n@@ -28,6 +28,7 @@\n #include \"kvm_arm.h\"\n #include \"cpu.h\"\n #include \"cpu-sysregs.h\"\n+#include \"cpu-idregs.h\"\n #include \"trace.h\"\n #include \"internals.h\"\n #include \"hw/pci/pci.h\"\n@@ -66,6 +67,12 @@ typedef struct ARMHostCPUFeatures {\n \n static ARMHostCPUFeatures arm_host_cpu_features;\n \n+#define DEF(NAME, OP0, OP1, CRN, CRM, OP2) [NAME##_IDX] = #NAME,\n+const char * const sysreg_names[NUM_ID_IDX] = {\n+#include \"cpu-sysregs.h.inc\"\n+};\n+#undef DEF\n+\n /**\n * kvm_arm_vcpu_init:\n * @cpu: ARMCPU\n@@ -244,6 +251,63 @@ static int get_host_cpu_reg(int fd, ARMHostCPUFeatures *ahcf,\n return ret;\n }\n \n+static int get_host_cpu_idregs_all(int fd, ARMHostCPUFeatures *ahcf)\n+{\n+ int err = 0, i;\n+ for (i = 0; i < NUM_ID_IDX; i++) {\n+ /* Skip registers whose plumbing is not yet added. */\n+ if (!arm_idregs[i].name) {\n+ continue;\n+ }\n+\n+ err |= get_host_cpu_reg(fd, ahcf, i);\n+ }\n+ return err;\n+}\n+\n+static int idregs_idx_to_kvm_idx(ARMIDRegisterIdx idx)\n+{\n+ ARMSysRegs sysreg = id_register_sysreg[idx];\n+\n+ return KVM_ARM_FEATURE_ID_RANGE_IDX(\n+ (sysreg >> CP_REG_ARM64_SYSREG_OP0_SHIFT) & 0x3,\n+ (sysreg >> CP_REG_ARM64_SYSREG_OP1_SHIFT) & 0x7,\n+ (sysreg >> CP_REG_ARM64_SYSREG_CRN_SHIFT) & 0xf,\n+ (sysreg >> CP_REG_ARM64_SYSREG_CRM_SHIFT) & 0xf,\n+ (sysreg >> CP_REG_ARM64_SYSREG_OP2_SHIFT) & 0x7);\n+}\n+\n+static int get_writable_id_regs(int vmfd)\n+{\n+ int cap, ret, i;\n+ uint64_t regs[KVM_ARM_FEATURE_ID_RANGE_SIZE] = { 0 };\n+ struct reg_mask_range range = {\n+ .addr = (uint64_t)(uintptr_t)regs,\n+ .range = KVM_ARM_FEATURE_ID_RANGE,\n+ };\n+\n+ cap = ioctl(vmfd, KVM_CHECK_EXTENSION,\n+ KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES);\n+ if (cap <= 0 || !(cap & (1 << KVM_ARM_FEATURE_ID_RANGE))) {\n+ return -ENOSYS;\n+ }\n+\n+ ret = ioctl(vmfd, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);\n+ if (ret) {\n+ return -errno;\n+ }\n+\n+ for (i = 0; i < NUM_ID_IDX; i++) {\n+ int kidx = idregs_idx_to_kvm_idx(i);\n+\n+ if (kidx < 0 || kidx >= KVM_ARM_FEATURE_ID_RANGE_SIZE) {\n+ continue;\n+ }\n+ arm_idregs[i].writable_mask = regs[kidx];\n+ }\n+ return 0;\n+}\n+\n static uint32_t kvm_arm_sve_get_vls(int fd)\n {\n uint64_t vls[KVM_ARM64_SVE_VLS_WORDS];\n@@ -455,6 +519,22 @@ static void kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)\n arm_host_cpu_features.sve_vq_supported = kvm_arm_sve_get_vls(fd);\n }\n }\n+ /*\n+ * Try to read all the ID registers. KVM does not yet support it\n+ * for all registers, hence ignore the errors.\n+ */\n+ get_host_cpu_idregs_all(fd, ahcf);\n+\n+ {\n+ int wret = get_writable_id_regs(fdarray[1]);\n+ if (wret) {\n+ warn_report(\"KVM_ARM_GET_REG_WRITABLE_MASKS\"\n+ \"%s: %s\",\n+ wret == -ENOSYS ? \" unsupported\"\n+ : \" failed\",\n+ strerror(-wret));\n+ }\n+ }\n \n kvm_arm_destroy_scratch_host_vcpu(fdarray);\n \n@@ -1080,6 +1160,71 @@ void kvm_arm_cpu_pre_save(ARMCPU *cpu)\n }\n }\n \n+/* same as kvm_arm_get_cpreg_ptr() but can return NULL. */\n+static uint64_t *kvm_arm_find_cpreg_ptr(ARMCPU *cpu, uint64_t regidx)\n+{\n+ uint64_t *res;\n+\n+ res = bsearch(®idx, cpu->cpreg_indexes, cpu->cpreg_array_len,\n+ sizeof(uint64_t), compare_u64);\n+ if (!res) {\n+ return NULL;\n+ }\n+ return &cpu->cpreg_values[res - cpu->cpreg_indexes];\n+}\n+\n+static void kvm_arm_writeback_idregs(ARMCPU *cpu)\n+{\n+ for (int i = 0; i < NUM_ID_IDX; i++) {\n+ uint64_t kvm_reg = idregs_sysreg_to_kvm_reg(id_register_sysreg[i]);\n+ uint64_t *cpreg = kvm_arm_find_cpreg_ptr(cpu, kvm_reg);\n+ const char *name = arm_idregs[i].name;\n+ uint64_t writable_mask, previous, desired, diff;\n+\n+ if (!cpreg) {\n+ warn_report(\"KVM does not expose ID register slot %d \"\n+ \"(kvm_reg=0x%\" PRIx64 \"), %s; skipping writeback\",\n+ i, kvm_reg, sysreg_names[i]);\n+ continue;\n+ }\n+\n+ if (!name) {\n+ /* No field table, don't push back. */\n+ warn_report(\"ID register slot %d \"\n+ \"(kvm_reg=0x%\" PRIx64 \"), %s: \"\n+ \"no field table in cpu-idregs.inc.h\",\n+ i, kvm_reg, sysreg_names[i]);\n+ continue;\n+ }\n+\n+ writable_mask = arm_idregs[i].writable_mask;\n+ previous = *cpreg;\n+ desired = cpu->isar.idregs[i];\n+ diff = previous ^ desired;\n+\n+ if (!diff) {\n+ continue;\n+ }\n+\n+ if (diff & ~writable_mask) {\n+ warn_report(\"%s: non-writable bits differ: \"\n+ \"kvm=0x%016\" PRIx64\n+ \" desired=0x%016\" PRIx64\n+ \" diff=0x%016\" PRIx64\n+ \" writable=0x%016\" PRIx64,\n+ name, previous, desired,\n+ diff & ~writable_mask,\n+ writable_mask);\n+ }\n+\n+ if (diff & writable_mask) {\n+ *cpreg = (previous & ~writable_mask) |\n+ (desired & writable_mask);\n+ trace_kvm_arm_writeback_idreg(name, previous, *cpreg);\n+ }\n+ }\n+}\n+\n bool kvm_arm_cpu_post_load(ARMCPU *cpu)\n {\n if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) {\n@@ -1116,6 +1261,10 @@ void kvm_arm_reset_vcpu(ARMCPU *cpu)\n fprintf(stderr, \"write_kvmstate_to_list failed\\n\");\n abort();\n }\n+\n+ /* Re-apply named-model ID register overrides after KVM_ARM_VCPU_INIT. */\n+ kvm_arm_writeback_idregs(cpu);\n+\n /*\n * Sync the reset values also into the CPUState. This is necessary\n * because the next thing we do will be a kvm_arch_put_registers()\n@@ -2051,7 +2200,16 @@ int kvm_arch_init_vcpu(CPUState *cs)\n }\n cpu->mp_affinity = mpidr & ARM64_AFFINITY_MASK;\n \n- return kvm_arm_init_cpreg_list(cpu);\n+ ret = kvm_arm_init_cpreg_list(cpu);\n+ if (ret) {\n+ return ret;\n+ }\n+\n+ /* Apply named-model ID register overrides on top of KVM's defaults. */\n+ kvm_arm_writeback_idregs(cpu);\n+ write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE);\n+\n+ return 0;\n }\n \n int kvm_arch_destroy_vcpu(CPUState *cs)\ndiff --git a/target/arm/trace-events b/target/arm/trace-events\nindex 8502fb3265..975236b24f 100644\n--- a/target/arm/trace-events\n+++ b/target/arm/trace-events\n@@ -13,6 +13,7 @@ arm_gt_update_irq(int timer, int irqstate) \"gt_update_irq: timer %d irqstate %d\"\n \n # kvm.c\n kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) \"MSI iova = 0x%\"PRIx64\" is translated into 0x%\"PRIx64\n+kvm_arm_writeback_idreg(const char *name, uint64_t previous, uint64_t desired) \"%s overwrite 0x%\"PRIx64\" with 0x%\"PRIx64\n \n # cpu.c\n arm_cpu_reset(uint64_t mp_aff) \"cpu %\" PRIu64\n","prefixes":["RFC","v1","12/13"]}