{"id":2232297,"url":"http://patchwork.ozlabs.org/api/patches/2232297/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/7a4d125075572c0a9a87eb34b25628263c0a3cc1.1777886786.git.michal.simek@amd.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<7a4d125075572c0a9a87eb34b25628263c0a3cc1.1777886786.git.michal.simek@amd.com>","list_archive_url":null,"date":"2026-05-04T09:26:29","name":"[v2,2/2] riscv: Exclude ACLINT for TARGET_XILINX_MBV","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"e94e30dd54ed504552504f2bdd22ceca028ad2bd","submitter":{"id":84271,"url":"http://patchwork.ozlabs.org/api/people/84271/?format=json","name":"Michal Simek","email":"michal.simek@amd.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/7a4d125075572c0a9a87eb34b25628263c0a3cc1.1777886786.git.michal.simek@amd.com/mbox/","series":[{"id":502631,"url":"http://patchwork.ozlabs.org/api/series/502631/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=502631","date":"2026-05-04T09:26:28","name":"[v2,1/2] riscv: Make RISCV_ACLINT visible","version":2,"mbox":"http://patchwork.ozlabs.org/series/502631/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2232297/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2232297/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=amd.com header.i=@amd.com header.a=rsa-sha256\n header.s=selector1 header.b=22GhBSVK;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=3Gvju8K2y1lVrasNR0vuse2gp7XAE7leNNv3nzhxl3I=;\n b=22GhBSVKISjcRaR1ru0/nkA/ZSSN+Jnm1HOGjx+tgqPAdUqInRw05NpYLc5DcS2UdLPfnrojl+wLwKBHx7N/qzod9gSvLPu5G41aWPAdKAGKxV9eTXWpJC395FgTEaU6Uaf2xCXOF87i1NdV1uSz0rBKk3FGmIHvj356aeS+788=","X-MS-Exchange-Authentication-Results":"spf=pass (sender IP is 165.204.84.17)\n smtp.mailfrom=amd.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=amd.com;","Received-SPF":"Pass (protection.outlook.com: domain of amd.com designates\n 165.204.84.17 as permitted sender) receiver=protection.outlook.com;\n client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C","From":"Michal Simek ","To":", ","CC":"Heinrich Schuchardt , Leo Yu-Chi Liang\n , Marek Vasut ,\n Martin Herren , Padmarao Begari\n , Sam Protsenko , \"Tom\n Rini\" ","Subject":"[PATCH v2 2/2] riscv: Exclude ACLINT for TARGET_XILINX_MBV","Date":"Mon, 4 May 2026 11:26:29 +0200","Message-ID":"\n <7a4d125075572c0a9a87eb34b25628263c0a3cc1.1777886786.git.michal.simek@amd.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"\n <7e80b87009b327aa618117baf223973e10c5b611.1777886786.git.michal.simek@amd.com>","References":"\n <7e80b87009b327aa618117baf223973e10c5b611.1777886786.git.michal.simek@amd.com>","MIME-Version":"1.0","X-Developer-Signature":"v=1; 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Ip=[165.204.84.17];\n Helo=[satlexmb08.amd.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n SJ5PEPF00000203.namprd05.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"MW3PR12MB4476","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"The Xilinx MicroBlaze V platform does not have an ACLINT (Advanced\nCore Local Interruptor) hardware block. The timer functionality is\nprovided through a different mechanism.\n\nExclude both RISCV_ACLINT and SPL_RISCV_ACLINT from being implied\nfor TARGET_XILINX_MBV while keeping the default behavior for other\ngeneric RISC-V targets that do have ACLINT hardware.\n\n spl/u-boot-spl: all -1382 data -360 rodata -200 text -822\n\nSigned-off-by: Michal Simek \n---\n\nChanges in v2:\n- Separate platform defconfig from core Kconfig\n\n configs/xilinx_mbv32_defconfig | 2 ++\n 1 file changed, 2 insertions(+)","diff":"diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig\nindex 4ff3bd6b6875..bcfd7cd92353 100644\n--- a/configs/xilinx_mbv32_defconfig\n+++ b/configs/xilinx_mbv32_defconfig\n@@ -17,6 +17,8 @@ CONFIG_SYS_CLK_FREQ=100000000\n CONFIG_BOOT_SCRIPT_OFFSET=0x0\n CONFIG_TARGET_XILINX_MBV=y\n # CONFIG_RISCV_ISA_F is not set\n+# CONFIG_RISCV_ACLINT is not set\n+# CONFIG_SPL_RISCV_ACLINT is not set\n # CONFIG_SPL_SMP is not set\n CONFIG_REMAKE_ELF=y\n # CONFIG_EFI_LOADER is not set\n","prefixes":["v2","2/2"]}