{"id":2232296,"url":"http://patchwork.ozlabs.org/api/patches/2232296/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/7e80b87009b327aa618117baf223973e10c5b611.1777886786.git.michal.simek@amd.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<7e80b87009b327aa618117baf223973e10c5b611.1777886786.git.michal.simek@amd.com>","list_archive_url":null,"date":"2026-05-04T09:26:28","name":"[v2,1/2] riscv: Make RISCV_ACLINT visible","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"f0a5e10d1dc8194bc579bb479ee344a4b0270efa","submitter":{"id":84271,"url":"http://patchwork.ozlabs.org/api/people/84271/?format=json","name":"Michal Simek","email":"michal.simek@amd.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/7e80b87009b327aa618117baf223973e10c5b611.1777886786.git.michal.simek@amd.com/mbox/","series":[{"id":502631,"url":"http://patchwork.ozlabs.org/api/series/502631/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=502631","date":"2026-05-04T09:26:28","name":"[v2,1/2] riscv: Make RISCV_ACLINT visible","version":2,"mbox":"http://patchwork.ozlabs.org/series/502631/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2232296/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2232296/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=amd.com header.i=@amd.com header.a=rsa-sha256\n header.s=selector1 header.b=Lg58GN4a;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=saG/huuci6hkAHzaMySW/dceN5E5ykSjYZ/y/5tStYg=;\n b=Lg58GN4ahZFzhkJ031ezqUHJagGivH0v9jrV87FOpZiXvedxPhtQ36GoDdUjDAveuYhn2CdgGMDBLumFyX6ZBARg4IGbAG9Iw0+hr9JGqseD+XB+YGHmBYf+3/KNOmFFvA1wGjYDxLbsgCXzGedJGcH0ZGAVtO1emxGqP7l3F4g=","X-MS-Exchange-Authentication-Results":"spf=pass (sender IP is 165.204.84.17)\n smtp.mailfrom=amd.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=amd.com;","Received-SPF":"Pass (protection.outlook.com: domain of amd.com designates\n 165.204.84.17 as permitted sender) receiver=protection.outlook.com;\n client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C","From":"Michal Simek ","To":", ","CC":"Conor Dooley , Jamie Gibbons\n , Leo , Randolph\n Sheng-Kai Lin , Rick Chen , Tom\n Rini , Yao Zi ","Subject":"[PATCH v2 1/2] riscv: Make RISCV_ACLINT visible","Date":"Mon, 4 May 2026 11:26:28 +0200","Message-ID":"\n <7e80b87009b327aa618117baf223973e10c5b611.1777886786.git.michal.simek@amd.com>","X-Mailer":"git-send-email 2.43.0","MIME-Version":"1.0","X-Developer-Signature":"v=1; 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Ip=[165.204.84.17];\n Helo=[satlexmb07.amd.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n BN2PEPF000044A4.namprd02.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"LV2PR12MB5848","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"A platform (like Xilinx Microblaze V) does not have an ACLINT (Advanced\nCore Local Interruptor) hardware block.\n\nMake RISCV_ACLINT and SPL_RISCV_ACLINT Kconfig symbols visible with\nprompts and enable them by default\n\nSigned-off-by: Michal Simek \n---\n\nChanges in v2:\n- Make symbols visible and disable them per platform basis\n\n arch/riscv/Kconfig | 6 ++++--\n 1 file changed, 4 insertions(+), 2 deletions(-)","diff":"diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig\nindex ad7589123c6c..d14086e9f4dc 100644\n--- a/arch/riscv/Kconfig\n+++ b/arch/riscv/Kconfig\n@@ -378,8 +378,9 @@ config DMA_ADDR_T_64BIT\n \tdefault y if 64BIT\n \n config RISCV_ACLINT\n-\tbool\n+\tbool \"RISC-V ACLINT support\"\n \tdepends on RISCV_MMODE\n+\tdefault y\n \tselect REGMAP\n \tselect SYSCON\n \thelp\n@@ -387,8 +388,9 @@ config RISCV_ACLINT\n \t associated with software and timer interrupts.\n \n config SPL_RISCV_ACLINT\n-\tbool\n+\tbool \"RISC-V ACLINT support in SPL\"\n \tdepends on SPL_RISCV_MMODE\n+\tdefault y\n \tselect SPL_REGMAP\n \tselect SPL_SYSCON\n \thelp\n","prefixes":["v2","1/2"]}