{"id":2232242,"url":"http://patchwork.ozlabs.org/api/patches/2232242/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260504025342.1452605-10-jamin_lin@aspeedtech.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260504025342.1452605-10-jamin_lin@aspeedtech.com>","list_archive_url":null,"date":"2026-05-04T02:53:53","name":"[v6,09/11] hw/arm/aspeed_ast27x0: Set EHCI ctrldssegment-default","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"88f3d1074bb8e7de9073a14338553ca291de9e9b","submitter":{"id":81768,"url":"http://patchwork.ozlabs.org/api/people/81768/?format=json","name":"Jamin Lin","email":"jamin_lin@aspeedtech.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260504025342.1452605-10-jamin_lin@aspeedtech.com/mbox/","series":[{"id":502603,"url":"http://patchwork.ozlabs.org/api/series/502603/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502603","date":"2026-05-04T02:53:55","name":"hw/usb/ehci: Add 64-bit descriptor addressing support","version":6,"mbox":"http://patchwork.ozlabs.org/series/502603/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2232242/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2232242/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com\n header.a=rsa-sha256 header.s=selector1 header.b=AXmRz1M8;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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As a result, descriptor addresses\nderived from the EHCI registers do not include the DRAM base\naddress.\n\nDescriptor memory is allocated through the DMA API with a 64-bit\nDMA mask, allowing descriptors to reside in DRAM above 4GB. On\nAST2700, EHCI queue heads (QH) and queue element transfer\ndescriptors (qTD) are therefore placed at addresses starting from\n0x400000000.\n\nSet the ctrldssegment-default property to \"sc->memmap[ASPEED_DEV_SDRAM] >> 32\"\nso the upper 32 bits of descriptor addresses are adjusted accordingly. This\nallows the emulated EHCI controller to construct correct system\naddresses when accessing descriptors in DRAM above 4GB.\n\nSigned-off-by: Jamin Lin \nReviewed-by: Cédric Le Goater \n---\n hw/arm/aspeed_ast27x0.c | 3 +++\n 1 file changed, 3 insertions(+)","diff":"diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c\nindex 87dcb82e1b..ea527479e6 100644\n--- a/hw/arm/aspeed_ast27x0.c\n+++ b/hw/arm/aspeed_ast27x0.c\n@@ -856,6 +856,9 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)\n \n /* EHCI */\n for (i = 0; i < sc->ehcis_num; i++) {\n+ object_property_set_int(OBJECT(&s->ehci[i]), \"ctrldssegment-default\",\n+ sc->memmap[ASPEED_DEV_SDRAM] >> 32,\n+ &error_abort);\n if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {\n return;\n }\n","prefixes":["v6","09/11"]}