{"id":2232195,"url":"http://patchwork.ozlabs.org/api/patches/2232195/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260503161913.77878-1-18255117159@163.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260503161913.77878-1-18255117159@163.com>","list_archive_url":null,"date":"2026-05-03T16:19:13","name":"PCI: cadence: Use cdns_pcie_find_capability() to get PCIe Cap offset in host driver","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"f3aaecb712bd71c06b6f571f73164ef51b03ad80","submitter":{"id":89937,"url":"http://patchwork.ozlabs.org/api/people/89937/?format=json","name":"Hans Zhang","email":"18255117159@163.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260503161913.77878-1-18255117159@163.com/mbox/","series":[{"id":502580,"url":"http://patchwork.ozlabs.org/api/series/502580/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=502580","date":"2026-05-03T16:19:13","name":"PCI: cadence: Use cdns_pcie_find_capability() to get PCIe Cap offset in host driver","version":1,"mbox":"http://patchwork.ozlabs.org/series/502580/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2232195/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2232195/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=163.com header.i=@163.com header.a=rsa-sha256\n header.s=s110527 header.b=d74FHb1q;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-53642-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (1024-bit key) header.d=163.com header.i=@163.com\n header.b=\"d74FHb1q\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=117.135.210.3","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=163.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=163.com"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g7qk81sxtz1xvV\n\tfor ; Mon, 04 May 2026 02:20:00 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id EFE393008756\n\tfor ; Sun, 3 May 2026 16:19:57 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 7B7CE372ECA;\n\tSun, 3 May 2026 16:19:57 +0000 (UTC)","from m16.mail.163.com (m16.mail.163.com [117.135.210.3])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id D23512D061C;\n\tSun, 3 May 2026 16:19:51 +0000 (UTC)","from zhb.. (unknown [])\n\tby gzsmtp2 (Coremail) with SMTP id PSgvCgBH_x2Cdfdp3fqmCw--.44160S2;\n\tMon, 04 May 2026 00:19:15 +0800 (CST)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1777825197; cv=none;\n b=PD2KX4TyW0v+lCBFqsQUFQUJZA4ynZx0nb9fdqmIOdQG0VRA+qTjupwSTC3h5j2pUblybK3p66SLRw4XZ5yLMxdUoXFs//iHSPksZNCvnn5r68c6mcl3HmewmmUIOq3nU64EK3QCT6Fw+ZSM04+qrc2CZ/IBFItLLYdQi2qjOgw=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1777825197; c=relaxed/simple;\n\tbh=yAvWr3Kprz6m9sHl1Wb0mk7IQ8OXqE+bT9c893UKmeE=;\n\th=From:To:Cc:Subject:Date:Message-Id:MIME-Version;\n b=lOMb1vV1EwbeV/H9mXL+vnAyiRESCo45IDOwGJINQ2InVukQmEVYXCNzkA4ndVdYAWZlDjhS3SUzpndeyXeBdqlWL1ED3Be72+lx7d3AJPU1VtCWIbGfUpc0onG5W5LVv3jl80RtdoB8bCE1twZOMb0uvH182I3W5RfzUJab4z0=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=163.com;\n spf=pass smtp.mailfrom=163.com;\n dkim=pass (1024-bit key) header.d=163.com header.i=@163.com\n header.b=d74FHb1q; arc=none smtp.client-ip=117.135.210.3","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com;\n\ts=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=b4\n\t1JjN3SH5XxvevjFooIwDYxxQeYW3QDlKT3BlDY/5I=; b=d74FHb1qiNQSooxygD\n\thXeiY8r70ELfArPMNtHvmFZZqa/+FcsxgUZaGW3TYjr1vCULRsC8m5Mg2gBOA6yT\n\tyjKBloKqIZX798YOhyF7SWtlvFoOT3rSkOePKcvTXGP+Fw4fRlhfEQ2lqfyLmLLR\n\tY9J3xWX5cg8CMctEVONvVM9rs=","From":"Hans Zhang <18255117159@163.com>","To":"bhelgaas@google.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org","Cc":"robh@kernel.org,\n\tlinux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tHans Zhang <18255117159@163.com>","Subject":"[PATCH] PCI: cadence: Use cdns_pcie_find_capability() to get PCIe Cap\n offset in host driver","Date":"Mon, 4 May 2026 00:19:13 +0800","Message-Id":"<20260503161913.77878-1-18255117159@163.com>","X-Mailer":"git-send-email 2.34.1","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-CM-TRANSID":"PSgvCgBH_x2Cdfdp3fqmCw--.44160S2","X-Coremail-Antispam":"1Uf129KBjvJXoWxtrW5tFW8CryfJFy5Zw4kCrg_yoW7Aw1fpF\n\tZxW3WSkF1Iqr4Y9a1kC3Z8XF13JF9Iya47Jan2kw13XF17CFyUGFy2kFy3KFW7GrZrXry7\n\tX3yDtrZxJa1avFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2\n\t9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pE6pBsUUUUU=","X-CM-SenderInfo":"rpryjkyvrrlimvzbiqqrwthudrp/xtbCwwTWemn3dYTVjQAA3c"},"content":"The PCI Express capability structure may not always reside at offset 0xC0\nin the configuration space of the Cadence PCIe controller. Different SoC\nintegrations can place the capability at a different offset, making the\nhardcoded CDNS_PCIE_RP_CAP_OFFSET unreliable.\n\nReplace the fixed offset with a dynamic lookup using\ncdns_pcie_find_capability() in all host-related functions that need\nto access the PCIe Capability registers. This ensures correct operation\nacross various SoC designs.\n\nSigned-off-by: Hans Zhang <18255117159@163.com>\n---\nWhen I was dealing with Siddharth Vadapalli's review comments on my patch,\nI also discovered that there was hardware coding for the capability. So, \ncontinued to handle it according to the previous submission.\nhttps://lore.kernel.org/all/20250813144529.303548-1-18255117159@163.com/\n\nThis patch is based on the submissions of the following series:\nhttps://patchwork.kernel.org/project/linux-pci/cover/20260501153553.66382-1-18255117159@163.com/\n---\n .../cadence/pcie-cadence-host-common.c | 17 ++++++++---------\n .../pci/controller/cadence/pcie-cadence-host.c | 5 +++--\n .../controller/cadence/pcie-cadence-lga-regs.h | 1 -\n 3 files changed, 11 insertions(+), 12 deletions(-)","diff":"diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.c b/drivers/pci/controller/cadence/pcie-cadence-host-common.c\nindex d4ae762f423f..b217e3717851 100644\n--- a/drivers/pci/controller/cadence/pcie-cadence-host-common.c\n+++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.c\n@@ -27,14 +27,14 @@ EXPORT_SYMBOL_GPL(bar_max_size);\n \n int cdns_pcie_host_training_complete(struct cdns_pcie *pcie)\n {\n-\tu32 pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET;\n \tunsigned long end_jiffies;\n \tu16 lnk_stat;\n+\tu8 cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_EXP);\n \n \t/* Wait for link training to complete. Exit after timeout. */\n \tend_jiffies = jiffies + LINK_RETRAIN_TIMEOUT;\n \tdo {\n-\t\tlnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA);\n+\t\tlnk_stat = cdns_pcie_rp_readw(pcie, cap + PCI_EXP_LNKSTA);\n \t\tif (!(lnk_stat & PCI_EXP_LNKSTA_LT))\n \t\t\tbreak;\n \t\tusleep_range(0, 1000);\n@@ -77,27 +77,26 @@ EXPORT_SYMBOL_GPL(cdns_pcie_host_wait_for_link);\n int cdns_pcie_retrain(struct cdns_pcie *pcie,\n \t\t cdns_pcie_linkup_func pcie_link_up)\n {\n-\tu32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET;\n+\tu32 lnk_cap_sls;\n \tu16 lnk_stat, lnk_ctl;\n \tint ret = 0;\n+\tu8 cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_EXP);\n \n \t/*\n \t * Set retrain bit if current speed is 2.5 GB/s,\n \t * but the PCIe root port support is > 2.5 GB/s.\n \t */\n \n-\tlnk_cap_sls = cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off +\n+\tlnk_cap_sls = cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + cap +\n \t\t\t\t\t PCI_EXP_LNKCAP));\n \tif ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)\n \t\treturn ret;\n \n-\tlnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA);\n+\tlnk_stat = cdns_pcie_rp_readw(pcie, cap + PCI_EXP_LNKSTA);\n \tif ((lnk_stat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {\n-\t\tlnk_ctl = cdns_pcie_rp_readw(pcie,\n-\t\t\t\t\t pcie_cap_off + PCI_EXP_LNKCTL);\n+\t\tlnk_ctl = cdns_pcie_rp_readw(pcie, cap + PCI_EXP_LNKCTL);\n \t\tlnk_ctl |= PCI_EXP_LNKCTL_RL;\n-\t\tcdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL,\n-\t\t\t\t lnk_ctl);\n+\t\tcdns_pcie_rp_writew(pcie, cap + PCI_EXP_LNKCTL, lnk_ctl);\n \n \t\tret = cdns_pcie_host_training_complete(pcie);\n \t\tif (ret)\ndiff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c\nindex 0bc9e6e90e0e..2a3fd41c1cf4 100644\n--- a/drivers/pci/controller/cadence/pcie-cadence-host.c\n+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c\n@@ -115,6 +115,7 @@ static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc)\n \tstruct cdns_pcie *pcie = &rc->pcie;\n \tu32 value, ctrl;\n \tu32 id;\n+\tu8 cap = cdns_pcie_find_capability(pcie, PCI_CAP_ID_EXP);\n \n \t/*\n \t * Set the root complex BAR configuration register:\n@@ -147,12 +148,12 @@ static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc)\n \tcdns_pcie_rp_writeb(pcie, PCI_CLASS_PROG, 0);\n \tcdns_pcie_rp_writew(pcie, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI);\n \n-\tvalue = cdns_pcie_rp_readl(pcie, CDNS_PCIE_RP_CAP_OFFSET + PCI_EXP_LNKCAP);\n+\tvalue = cdns_pcie_rp_readl(pcie, cap + PCI_EXP_LNKCAP);\n \tif (rc->quirk_broken_aspm_l0s)\n \t\tvalue &= ~PCI_EXP_LNKCAP_ASPM_L0S;\n \tif (rc->quirk_broken_aspm_l1)\n \t\tvalue &= ~PCI_EXP_LNKCAP_ASPM_L1;\n-\tcdns_pcie_rp_writel(pcie, CDNS_PCIE_RP_CAP_OFFSET + PCI_EXP_LNKCAP, value);\n+\tcdns_pcie_rp_writel(pcie, cap + PCI_EXP_LNKCAP, value);\n \n \treturn 0;\n }\ndiff --git a/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h b/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h\nindex 857b2140c5d2..7b92812ed120 100644\n--- a/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h\n+++ b/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h\n@@ -133,7 +133,6 @@\n \n /* Root Port Registers (PCI configuration space for the root port function) */\n #define CDNS_PCIE_RP_BASE\t0x00200000\n-#define CDNS_PCIE_RP_CAP_OFFSET 0xC0\n \n /* Address Translation Registers */\n #define CDNS_PCIE_AT_BASE\t0x00400000\n","prefixes":[]}