{"id":2232189,"url":"http://patchwork.ozlabs.org/api/patches/2232189/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/57d65cb4-e71b-41c6-a038-41ac3d993cd3@oss.qualcomm.com/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<57d65cb4-e71b-41c6-a038-41ac3d993cd3@oss.qualcomm.com>","list_archive_url":null,"date":"2026-05-03T14:01:42","name":"[to-be-committed,RISC-V,PR,rtl-optimization/124766] Simplify x + y == y into x == 0","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"db11fcf924806ea415e41ab15a2a8ffc90be1fdb","submitter":{"id":92310,"url":"http://patchwork.ozlabs.org/api/people/92310/?format=json","name":"Jeffrey Law","email":"jeffrey.law@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/57d65cb4-e71b-41c6-a038-41ac3d993cd3@oss.qualcomm.com/mbox/","series":[{"id":502578,"url":"http://patchwork.ozlabs.org/api/series/502578/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=502578","date":"2026-05-03T14:01:42","name":"[to-be-committed,RISC-V,PR,rtl-optimization/124766] Simplify x + y == y into x == 0","version":1,"mbox":"http://patchwork.ozlabs.org/series/502578/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2232189/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2232189/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=BRzYZmDg;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=WPKBjWFD;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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boundary=\"------------0PDWW76wLohunRCLKL1yPNV0\"","Message-ID":"<57d65cb4-e71b-41c6-a038-41ac3d993cd3@oss.qualcomm.com>","Date":"Sun, 3 May 2026 08:01:42 -0600","MIME-Version":"1.0","User-Agent":"Mozilla Thunderbird","Content-Language":"en-US","From":"Jeffrey Law ","To":"'GCC Patches' ","Subject":"[to-be-committed][RISC-V][PR rtl-optimization/124766] Simplify x + y\n == y into x == 0","X-Authority-Analysis":"v=2.4 cv=H6rrBeYi c=1 sm=1 tr=0 ts=69f7554a cx=c_pps\n a=bS7HVuBVfinNPG3f6cIo3Q==:117 a=asGLMfRmzhnGNxaIYohjRg==:17\n a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=r77TgQKjGQsHNAKrUKIA:9\n a=9OD_id-UUDYYNeElRygA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10\n a=ortcI1PrsbfvGZA5pR4A:9 a=B2y7HmGcmWMA:10 a=vBUdepa8ALXHeOFLBtFW:22","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNTAzMDE1NyBTYWx0ZWRfX/HCwx1+NkNsD\n +AFUluw5ekGu/Sm/1uZ8LLiVG3Dcvv8sqP0wNbNzC8kpyvr+ch6MPzDBlb1PT8eHLAFUPnkpyT/\n kio2+/Rz9aMUqG3lnEB0Kpc1XGgZbEmlRfyiYiYX/uUqifmcfmUquHrFbeGpbKrcjOzCQa/gAxc\n wMpCcvLk4ZVDMb+k9mqAUcTEwO/0GcePiel7xMycYnMJIZE9/ejjj/0Xz9DDDF+p7oT3GDwGX0h\n iVk0kM55sMgkoZeAGvwsKRzYIwSVBm62x6HBxtyywDJEOv0tXZoysbQEJvRnQ3EVRWzdNQfMfEb\n p0NlEbujmVbvI1a6tKP3kO8+RF4tKH+FpXve8j8AvGRUtWQCLNpAggfX4gkZSeX5KhYdB0zdgL7\n qKxcQQ1//zk1txs1r5pIPupmaRbnHiVq6tPt02G/71TpxCIaeN2VQnPnSxFhJfu4pJIX829y+1R\n eDzQrbILMEKlS0jEn4w==","X-Proofpoint-GUID":"vbfZFgt9_Xu4YrpOEbR_w5Uq11LWuGuP","X-Proofpoint-ORIG-GUID":"vbfZFgt9_Xu4YrpOEbR_w5Uq11LWuGuP","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-05-03_04,2026-04-30_02,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n lowpriorityscore=0 clxscore=1015 phishscore=0 malwarescore=0\n priorityscore=1501 suspectscore=0 bulkscore=0 impostorscore=0 adultscore=0\n spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound\n adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000\n definitions=main-2605030157","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"So this is derived from S_regmatch in spec2017, so fairly hot.\n\n\n\nlong\nfrob (unsigned short *y, long z)\n{\n   long ret = (*y << 2) + z;\n   if (ret != z)\n     return 0;\n   return ret;\n}\n\nIt generates this code on riscv:\n\n\n         lhu     a5,0(a0)\n         sh2add  a5,a5,a1\n         sub     a1,a1,a5\n         czero.nez       a0,a5,a1\n         ret\n\nThat's not bad, but the sh2add and sub are not actually needed. This may \nlook familiar to a case Daniel was recently discussing, the major \ndifference are the types of the function args which I got wrong the \nfirst time I reduced this case.\n\nczero instructions check their condition for zero/nonzero status. So we \njust need to know if a1 has a zero/nonzero value at the czero \ninstruction.  So working backwards\n\na1 = a1 - a5                // sub instruction\na1 = a1 - ((a5 << 2) + a1)  // substitute from sh2add\na1 = a5 << 2                // a1 terms cancel out\n\nSo we just need the nonzero state of a5 << 2.  Now since a5 was set by \nthe lhu instruction, the upper 48 bits are already known zero, so \ncritically we know the upper 2 bits are zero. Meaning that we can just \ntest a5 as set by the lhu instruction for zero/nonzero.  The net is we \ncan generate this code instead:\n\n         lhu     a0,0(a0)\n         czero.nez       a0,a1,a0\n         ret\n\n\nIt's a small, but visible instruction count savings and likely a small \nperformance improvement on most designs.\n\nSo the trick to get there is a small simplify-rtx improvement. We just \nneed to simplify\n(eq/ne (plus (x) (y)) (y)) ->  (eq/ne (x) (0))\n\nAnd all the right things just happen.  Bootstrapped and regression \ntested on a variety of native platforms including x86, aarch64, riscv \nand tested across the various embedded targets in my tester.  I'll wait \nfor the RISC-V pre-commit CI tester to render a verdict before going \nforward.\n\n\nJeff","diff":"diff --git a/gcc/testsuite/gcc.target/riscv/pr124766.c b/gcc/testsuite/gcc.target/riscv/pr124766.c\nnew file mode 100644\nindex 000000000000..b16c31e8a9bd\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/pr124766.c\n@@ -0,0 +1,17 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-march=rv64gcbv_zicond -mabi=lp64d\" { target rv64 } } */\n+/* { dg-options \"-march=rv32gcbv_zicond -mabi=ilp32\" { target rv32 } } */\n+/* { dg-skip-if \"\" { *-*-* } { \"-O0\" \"-Og\" } } */\n+\n+long\n+frob (unsigned short *y, long z)\n+{\n+ long ret = (*y << 2) + z;\n+ if (ret != z)\n+ return 0;\n+ return ret;\n+}\n+\n+/* { dg-final { scan-assembler-not \"sh2add\" } } */\n+/* { dg-final { scan-assembler-not \"sub\" } } */\n+\ndiff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc\nindex 50fc51152cab..23de16800065 100644\n--- a/gcc/simplify-rtx.cc\n+++ b/gcc/simplify-rtx.cc\n@@ -6649,6 +6649,14 @@ simplify_context::simplify_relational_operation_1 (rtx_code code,\n return simplify_gen_relational (code, mode, cmp_mode, x, tem);\n }\n \n+ /* (eq/ne (plus (x) (y)) y) simplifies to (eq/ne x 0). */\n+ if ((code == EQ || code == NE)\n+ && op0code == PLUS\n+ && XEXP (op0, 1) == op1\n+ && (INTEGRAL_MODE_P (cmp_mode) || flag_unsafe_math_optimizations))\n+ return simplify_gen_relational (code, mode, cmp_mode,\n+\t\t\t\t XEXP (op0, 0), const0_rtx);\n+\n /* (ne:SI (zero_extract:SI FOO (const_int 1) BAR) (const_int 0))) is\n the same as (zero_extract:SI FOO (const_int 1) BAR). */\n scalar_int_mode int_mode, int_cmp_mode;\n","prefixes":["to-be-committed","RISC-V","PR","rtl-optimization/124766"]}