{"id":2232164,"url":"http://patchwork.ozlabs.org/api/patches/2232164/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260503073541.790215-10-eric.auger@redhat.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260503073541.790215-10-eric.auger@redhat.com>","list_archive_url":null,"date":"2026-05-03T07:33:29","name":"[v4,09/17] arm/cpu: accessors for writable id registers","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"b23ae8d102d4743d8e480532cf8c181d5d9520e2","submitter":{"id":69187,"url":"http://patchwork.ozlabs.org/api/people/69187/?format=json","name":"Eric Auger","email":"eric.auger@redhat.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260503073541.790215-10-eric.auger@redhat.com/mbox/","series":[{"id":502569,"url":"http://patchwork.ozlabs.org/api/series/502569/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502569","date":"2026-05-03T07:33:20","name":"kvm/arm: Introduce a customizable aarch64 KVM host model","version":4,"mbox":"http://patchwork.ozlabs.org/series/502569/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2232164/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2232164/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256\n header.s=mimecast20190719 header.b=iruJI14m;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com;\n s=mimecast20190719; t=1777793809;\n h=from:from:reply-to:subject:subject:date:date:message-id:message-id:\n to:to:cc:cc:mime-version:mime-version:\n content-transfer-encoding:content-transfer-encoding:\n in-reply-to:in-reply-to:references:references;\n bh=557ybO8Fo2cuy3bEAfcP6Q/Qbo00s1S/okkhzC4QXa4=;\n b=iruJI14mqRdN19Y+r1G5fks5yEx3AEde7iU9BeaTJ8/jxLCio6uwZpgC4T87eB4siab3sc\n ce5GLsvyKCWsVfH7NXRvtFj0SF5SO7aVZD6X8V2IR8eGKdEMNVKqdO45zkCW2aUx2wxh/u\n Z17TECHIEt4vhtORaVK+jRGgRyC7m7Q=","X-MC-Unique":"ljsCbmcJOf-NUPTUsfrLfA-1","X-Mimecast-MFC-AGG-ID":"ljsCbmcJOf-NUPTUsfrLfA_1777793805","From":"Eric Auger ","To":"eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org,\n qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org,\n richard.henderson@linaro.org, cohuck@redhat.com, sebott@redhat.com,\n skolothumtho@nvidia.com, philmd@linaro.org","Cc":"maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com,\n armbru@redhat.com, berrange@redhat.com, abologna@redhat.com,\n jdenemar@redhat.com","Subject":"[PATCH v4 09/17] arm/cpu: accessors for writable id registers","Date":"Sun, 3 May 2026 09:33:29 +0200","Message-ID":"<20260503073541.790215-10-eric.auger@redhat.com>","In-Reply-To":"<20260503073541.790215-1-eric.auger@redhat.com>","References":"<20260503073541.790215-1-eric.auger@redhat.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Scanned-By":"MIMEDefang 3.4.1 on 10.30.177.93","Received-SPF":"pass client-ip=170.10.133.124;\n envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com","X-Spam_score_int":"12","X-Spam_score":"1.2","X-Spam_bar":"+","X-Spam_report":"(1.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001,\n RCVD_IN_SBL_CSS=3.335, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Cornelia Huck \n\nIntroduce ARM_FEATURE_ID_RANGE_IDX macro that converts opcodes\ninto the index used to access the 3 * 8 * 8 feature id array.\n\nKVM_ARM_GET_REG_WRITABLE_MASKS populates writable masks with\nthat indexing.\n\nSigned-off-by: Cornelia Huck \nSigned-off-by: Eric Auger \n---\n target/arm/cpu.h | 7 +++++++\n 1 file changed, 7 insertions(+)","diff":"diff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex 2aa22360d2..0ac0fd13cf 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -886,6 +886,13 @@ typedef struct IdRegMap {\n uint64_t regs[NR_ID_REG_MASKS]; /* writable masks for registers */\n } IdRegMap;\n \n+#define ARM_FEATURE_ID_RANGE_IDX(op0, op1, crn, crm, op2) \\\n+ ({ \\\n+ __u64 __op1 = (op1) & 3; \\\n+ __op1 -= (__op1 == 3); \\\n+ (__op1 << 6 | ((crm) & 7) << 3 | (op2)); \\\n+ })\n+\n /* REG is ID_XXX */\n #define FIELD_DP64_IDREG(ISAR, REG, FIELD, VALUE) \\\n ({ \\\n","prefixes":["v4","09/17"]}