{"id":2232161,"url":"http://patchwork.ozlabs.org/api/patches/2232161/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260503073541.790215-2-eric.auger@redhat.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260503073541.790215-2-eric.auger@redhat.com>","list_archive_url":null,"date":"2026-05-03T07:33:21","name":"[v4,01/17] scripts: introduce scripts/update-aarch64-cpu-sysregs-header.py","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"d0564df917621fd31f419f8cc065a5e30c9b574f","submitter":{"id":69187,"url":"http://patchwork.ozlabs.org/api/people/69187/?format=json","name":"Eric Auger","email":"eric.auger@redhat.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260503073541.790215-2-eric.auger@redhat.com/mbox/","series":[{"id":502569,"url":"http://patchwork.ozlabs.org/api/series/502569/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502569","date":"2026-05-03T07:33:20","name":"kvm/arm: Introduce a customizable aarch64 KVM host model","version":4,"mbox":"http://patchwork.ozlabs.org/series/502569/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2232161/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2232161/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256\n header.s=mimecast20190719 header.b=It8ztmtI;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com;\n s=mimecast20190719; t=1777793762;\n h=from:from:reply-to:subject:subject:date:date:message-id:message-id:\n to:to:cc:cc:mime-version:mime-version:\n content-transfer-encoding:content-transfer-encoding:\n in-reply-to:in-reply-to:references:references;\n bh=F71HBHl1W+M/uo5lCzlKVd+GPVdXLXIc1bRDPajNYkk=;\n b=It8ztmtIYkFFuy1Fu0yR0CxJC0pp8EyIxcSNs0DXmO2/btJHGp2igHeXNnjLDbjR7kikka\n 4X67x4/IKJvqe3I7E5GRGmBhhupT7krfgUrOf0A3dPcZfJPQ9gCoHG7nU+hp3zhLVrcy1U\n EzxTYiexQR11pAbWzqQQi8iUH1K3/IE=","X-MC-Unique":"hNzsxw6-OZiAz4lXVnajhw-1","X-Mimecast-MFC-AGG-ID":"hNzsxw6-OZiAz4lXVnajhw_1777793759","From":"Eric Auger ","To":"eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org,\n qemu-arm@nongnu.org, kvmarm@lists.linux.dev, peter.maydell@linaro.org,\n richard.henderson@linaro.org, cohuck@redhat.com, sebott@redhat.com,\n skolothumtho@nvidia.com, philmd@linaro.org","Cc":"maz@kernel.org, oliver.upton@linux.dev, pbonzini@redhat.com,\n armbru@redhat.com, berrange@redhat.com, abologna@redhat.com,\n jdenemar@redhat.com","Subject":"[PATCH v4 01/17] scripts: introduce\n scripts/update-aarch64-cpu-sysregs-header.py","Date":"Sun, 3 May 2026 09:33:21 +0200","Message-ID":"<20260503073541.790215-2-eric.auger@redhat.com>","In-Reply-To":"<20260503073541.790215-1-eric.auger@redhat.com>","References":"<20260503073541.790215-1-eric.auger@redhat.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Scanned-By":"MIMEDefang 3.4.1 on 10.30.177.93","Received-SPF":"pass client-ip=170.10.133.124;\n envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001,\n SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Introduce a script that takes as input the Registers.json file\ndelivered in the AARCHMRS Features Model downloadable from the\nArm Developer A-Profile Architecture Exploration Tools page:\nhttps://developer.arm.com/Architectures/A-Profile%20Architecture#Downloads\nand outputs the list of ID regs in target/arm/cpu-sysregs.h.inc\nunder the form of DEF(, , , , , ).\n\nWe only care about IDregs with opcodes satisfying:\nop0 = 3, op1 = {0,1,3}, crn = 0, crm within [0, 7], op2 within [0, 7]\n\nSigned-off-by: Eric Auger \n[CH: note correct op1 range, don't skip CCSIDR]\nSigned-off-by: Cornelia Huck \nMessage-ID: <20251208163751.611186-2-eric.auger@redhat.com>\n---\n scripts/update-aarch64-cpu-sysregs-header.py | 134 +++++++++++++++++++\n 1 file changed, 134 insertions(+)\n create mode 100755 scripts/update-aarch64-cpu-sysregs-header.py","diff":"diff --git a/scripts/update-aarch64-cpu-sysregs-header.py b/scripts/update-aarch64-cpu-sysregs-header.py\nnew file mode 100755\nindex 0000000000..8c337147dd\n--- /dev/null\n+++ b/scripts/update-aarch64-cpu-sysregs-header.py\n@@ -0,0 +1,134 @@\n+#!/usr/bin/env python3\n+\n+# This script takes as input the Registers.json file delivered in\n+# the AARCHMRS Features Model downloadable from the Arm Developer\n+# A-Profile Architecture Exploration Tools page:\n+# https://developer.arm.com/Architectures/A-Profile%20Architecture#Downloads\n+# and outputs the list of ID regs in target/arm/cpu-sysregs.h.inc\n+# under the form of DEF(, , , , , )\n+#\n+# Copyright (C) 2026 Red Hat, Inc.\n+#\n+# Authors: Eric Auger \n+#\n+# SPDX-License-Identifier: GPL-2.0-or-later\n+\n+\n+import json\n+import os\n+import sys\n+\n+# Some regs have op code values like 000x, 001x. Anyway we don't need\n+# them. Besides some regs are undesired in the generated file such as\n+# VMPIDR_EL2 and VPIDR_EL2 which are outside of the IDreg scope we\n+# are interested in and are tricky to decode as their system accessor\n+# refer to MPIDR_EL1/MIDR_EL1 respectively\n+\n+skiplist = ['ALLINT', 'PM', 'S1_', 'S3_', 'SVCR', \\\n+ 'VMPIDR_EL2', 'VPIDR_EL2']\n+\n+# returns the int value of a given @opcode for a reg @encoding\n+def get_opcode(encoding, opcode):\n+ fvalue = encoding.get(opcode)\n+ if fvalue:\n+ value = fvalue.get('value')\n+ if isinstance(value, str):\n+ value = value.strip(\"'\")\n+ value = int(value, 2)\n+ return value\n+ return -1\n+\n+def extract_idregs_from_registers_json(filename):\n+ \"\"\"\n+ Load a Registers.json file and extract all ID registers, decode their\n+ opcode and dump the information in target/arm/cpu-sysregs.h.inc\n+\n+ Args:\n+ filename (str): The path to the Registers.json\n+ returns:\n+ idregs: list of ID regs and their encoding\n+ \"\"\"\n+ if not os.path.exists(filename):\n+ print(f\"Error: {filename} could not be found!\")\n+ return {}\n+\n+ try:\n+ with open(filename, 'r') as f:\n+ register_data = json.load(f)\n+\n+ except json.JSONDecodeError:\n+ print(f\"Could not decode json from '{filename}'!\")\n+ return {}\n+ except Exception as e:\n+ print(f\"Unexpected error while reading {filename}: {e}\")\n+ return {}\n+\n+ registers = [r for r in register_data if isinstance(r, dict) and \\\n+ r.get('_type') == 'Register']\n+\n+ idregs = {}\n+\n+ for register in registers:\n+ reg_name = register.get('name')\n+\n+ is_skipped = any(term in (reg_name or \"\").upper() for term in skiplist)\n+\n+ if reg_name and not is_skipped:\n+ accessors = register.get('accessors', [])\n+\n+ for accessor in accessors:\n+ type = accessor.get('_type')\n+ if type in ['Accessors.SystemAccessor']:\n+ encoding_list = accessor.get('encoding')\n+\n+ if isinstance(encoding_list, list) and encoding_list and \\\n+ isinstance(encoding_list[0], dict):\n+ encoding_wrapper = encoding_list[0]\n+ encoding_source = encoding_wrapper.get('encodings', \\\n+ encoding_wrapper)\n+\n+ if isinstance(encoding_source, dict):\n+ op0 = get_opcode(encoding_source, 'op0')\n+ op1 = get_opcode(encoding_source, 'op1')\n+ op2 = get_opcode(encoding_source, 'op2')\n+ crn = get_opcode(encoding_source, 'CRn')\n+ crm = get_opcode(encoding_source, 'CRm')\n+ encoding_str=f\"{op0} {op1} {crn} {crm} {op2}\"\n+\n+ # ID regs are assumed within this scope\n+ if op0 == 3 and (op1 == 0 or op1 == 1 or op1 == 3) and \\\n+ crn == 0 and (crm >= 0 and crm <= 7) and (op2 >= 0 and op2 <= 7):\n+ idregs[reg_name] = encoding_str\n+\n+ return idregs\n+\n+if __name__ == \"__main__\":\n+ # Single arg expected: the path to the Registers.json file\n+ if len(sys.argv) < 2:\n+ print(\"Usage: python scripts/update-aarch64-cpu-sysregs-header.py \"\n+ \"\")\n+ sys.exit(1)\n+ else:\n+ json_file_path = sys.argv[1]\n+\n+ extracted_registers = extract_idregs_from_registers_json(json_file_path)\n+\n+ if extracted_registers:\n+ output_list = extracted_registers.items()\n+\n+ # Sort by register name\n+ sorted_output = sorted(output_list, key=lambda item: item[0])\n+\n+ # format lines as DEF(, , , , , )\n+ final_output = \"\"\n+ for reg_name, encoding in sorted_output:\n+ reformatted_encoding = encoding.replace(\" \", \", \")\n+ final_output += f\"DEF({reg_name}, {reformatted_encoding})\\n\"\n+\n+ with open(\"target/arm/cpu-sysregs.h.inc\", 'w') as f:\n+ f.write(\"/* SPDX-License-Identifier: GPL-2.0-or-later */\\n\\n\")\n+ f.write(\"/* This file is autogenerated by \")\n+ f.write(\"scripts/update-aarch64-cpu-sysregs-header.py */\\n\")\n+ f.write(\"/* DEF(, , , , , ) */\\n\\n\")\n+ f.write(final_output)\n+ print(\"updated target/arm/cpu-sysregs.h.inc\")\n","prefixes":["v4","01/17"]}