{"id":2232140,"url":"http://patchwork.ozlabs.org/api/patches/2232140/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260503015756.99176-3-54weasels@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260503015756.99176-3-54weasels@gmail.com>","list_archive_url":null,"date":"2026-05-03T01:57:51","name":"[2/7] hw/net/lance: Add Sun-3 Native DMA byte-swapping support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"70acaca5d0ace045e9dd5eb1505d4448ce38a625","submitter":{"id":93309,"url":"http://patchwork.ozlabs.org/api/people/93309/?format=json","name":"54weasels","email":"54weasels@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260503015756.99176-3-54weasels@gmail.com/mbox/","series":[{"id":502564,"url":"http://patchwork.ozlabs.org/api/series/502564/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502564","date":"2026-05-03T01:57:51","name":"m68k: Add Sun-3 Machine Emulation","version":1,"mbox":"http://patchwork.ozlabs.org/series/502564/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2232140/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2232140/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=AW0f4Bw5;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-dy1-x132a.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-Mailman-Approved-At":"Sun, 03 May 2026 01:58:52 -0400","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"The Sun-3 hardware physically byte-swaps the D0-D7 and D8-D15 DMA lanes between the Little-Endian LANCE controller and the Big-Endian Sun-3 memory. This commit intercepts the LANCE DMA reads/writes by injecting a phys_mem override in pcnet.c specifically for the Sun-3 instance, dynamically neutralizing the hardcoded internal initblk swap and properly mapping the payload payloads.\n\nSigned-off-by: 54weasels <54weasels@gmail.com>\n---\n hw/net/lance.c | 111 ++++++++++++++++++++++++++++++++++++++---\n hw/net/meson.build | 3 +-\n include/hw/net/lance.h | 3 ++\n 3 files changed, 109 insertions(+), 8 deletions(-)","diff":"diff --git a/hw/net/lance.c b/hw/net/lance.c\nindex 5d5bf9b961..93944fb35d 100644\n--- a/hw/net/lance.c\n+++ b/hw/net/lance.c\n@@ -1,3 +1,4 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n /*\n * QEMU AMD PC-Net II (Am79C970A) emulation\n *\n@@ -22,7 +23,8 @@\n * THE SOFTWARE.\n */\n \n-/* This software was written to be compatible with the specification:\n+/*\n+ * This software was written to be compatible with the specification:\n * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet\n * AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000\n */\n@@ -44,8 +46,73 @@\n #include \"hw/core/qdev-properties.h\"\n #include \"trace.h\"\n #include \"system/system.h\"\n+#include \"system/address-spaces.h\"\n+#include \"system/dma.h\"\n+\n+/*\n+ * LANCE Native DMA Read Hook\n+ *\n+ * Sun-3 Hardware intrinsically byte-swaps the D0-D7 and D8-D15 DMA lanes\n+ * between the Little-Endian LANCE controller and the Big-Endian Sun-3 memory.\n+ * We MUST model this manually. pcnet.c passes CSR_BSWP(s) for payloads\n+ * (correctly bypassing the swap if LANCE internally neutralizes it).\n+ * However, pcnet.c hardcodes do_bswap=1 for the `initblk` structure\n+ * (len 24/28).\n+ * We dynamically intercept the `initblk` fetch by cross-referencing CSR_IADR to\n+ * enforce the hardware swap reliably. Because this branch is only taken when\n+ * `dma_mr` is explicitly provided by the machine, this quirk is safely isolated\n+ * to the Sun-3 and does not impact SPARC (which uses `ledma`).\n+ */\n+static void lance_dma_read(void *dma_opaque, hwaddr addr,\n+ uint8_t *buf, int len, int do_bswap)\n+{\n+ SysBusPCNetState *d = SYSBUS_PCNET(dma_opaque);\n+ PCNetState *s = &d->state;\n+\n+ dma_memory_read(&d->dma_as, addr, buf, len, MEMTXATTRS_UNSPECIFIED);\n+\n+ uint32_t bcr_ssize32 = (s->bcr[20] & 0x0100);\n+ hwaddr iadr = (s->csr[1] | ((uint32_t)s->csr[2] << 16));\n+ if (!bcr_ssize32) {\n+ iadr |= ((0xff00 & (uint32_t)s->csr[2]) << 16);\n+ }\n \n+ int internal_bswap = do_bswap;\n+ if (addr == iadr && (len == 24 || len == 28)) {\n+ internal_bswap = 0; /* Force hardware swap natively for initblk */\n+ }\n \n+ if (!internal_bswap) {\n+ for (int i = 0; i < (len & ~1); i += 2) {\n+ uint8_t tmp = buf[i];\n+ buf[i] = buf[i + 1];\n+ buf[i + 1] = tmp;\n+ }\n+ }\n+}\n+\n+/* LANCE Native DMA Write Hook */\n+static void lance_dma_write(void *dma_opaque, hwaddr addr,\n+ uint8_t *buf, int len, int do_bswap)\n+{\n+ SysBusPCNetState *s = SYSBUS_PCNET(dma_opaque);\n+\n+ if (!do_bswap) {\n+ uint8_t *swapped_buf = g_malloc(len);\n+ for (int i = 0; i < (len & ~1); i += 2) {\n+ swapped_buf[i] = buf[i + 1];\n+ swapped_buf[i + 1] = buf[i];\n+ }\n+ if (len & 1) {\n+ swapped_buf[len - 1] = buf[len - 1];\n+ }\n+ dma_memory_write(&s->dma_as, addr, swapped_buf, len,\n+ MEMTXATTRS_UNSPECIFIED);\n+ g_free(swapped_buf);\n+ } else {\n+ dma_memory_write(&s->dma_as, addr, buf, len, MEMTXATTRS_UNSPECIFIED);\n+ }\n+}\n static void parent_lance_reset(void *opaque, int irq, int level)\n {\n SysBusPCNetState *d = opaque;\n@@ -59,7 +126,15 @@ static void lance_mem_write(void *opaque, hwaddr addr,\n SysBusPCNetState *d = opaque;\n \n trace_lance_mem_writew(addr, val & 0xffff);\n- pcnet_ioport_writew(&d->state, addr, val & 0xffff);\n+ if (size == 1) {\n+ uint16_t orig = pcnet_ioport_readw(&d->state, addr & ~1);\n+ if (addr & 1) { /* LSB in Big Endian */\n+ val = (orig & 0xff00) | (val & 0xff);\n+ } else { /* MSB in Big Endian */\n+ val = (orig & 0x00ff) | ((val & 0xff) << 8);\n+ }\n+ }\n+ pcnet_ioport_writew(&d->state, addr & ~1, val & 0xffff);\n }\n \n static uint64_t lance_mem_read(void *opaque, hwaddr addr,\n@@ -68,18 +143,28 @@ static uint64_t lance_mem_read(void *opaque, hwaddr addr,\n SysBusPCNetState *d = opaque;\n uint32_t val;\n \n- val = pcnet_ioport_readw(&d->state, addr);\n- trace_lance_mem_readw(addr, val & 0xffff);\n+ val = pcnet_ioport_readw(&d->state, addr & ~1);\n+ if (size == 1) {\n+ if (addr & 1) {\n+ val = val & 0xff;\n+ } else {\n+ val = (val >> 8) & 0xff;\n+ }\n+ }\n return val & 0xffff;\n }\n \n static const MemoryRegionOps lance_mem_ops = {\n .read = lance_mem_read,\n .write = lance_mem_write,\n- .endianness = DEVICE_NATIVE_ENDIAN,\n+ .endianness = DEVICE_BIG_ENDIAN,\n .valid = {\n- .min_access_size = 2,\n- .max_access_size = 2,\n+ .min_access_size = 1,\n+ .max_access_size = 4,\n+ },\n+ .impl = {\n+ .min_access_size = 1,\n+ .max_access_size = 4,\n },\n };\n \n@@ -115,8 +200,18 @@ static void lance_realize(DeviceState *dev, Error **errp)\n \n sysbus_init_irq(sbd, &s->irq);\n \n+ if (d->dma_mr) {\n+ address_space_init(&d->dma_as, d->dma_mr, \"lance-dma\");\n+ s->phys_mem_read = lance_dma_read;\n+ s->phys_mem_write = lance_dma_write;\n+ s->dma_opaque = DEVICE(d);\n+ } else {\n+#if defined(TARGET_SPARC)\n s->phys_mem_read = ledma_memory_read;\n s->phys_mem_write = ledma_memory_write;\n+#endif\n+ }\n+\n pcnet_common_init(dev, s, &net_lance_info);\n }\n \n@@ -140,6 +235,8 @@ static void lance_instance_init(Object *obj)\n static const Property lance_properties[] = {\n DEFINE_PROP_LINK(\"dma\", SysBusPCNetState, state.dma_opaque,\n TYPE_DEVICE, DeviceState *),\n+ DEFINE_PROP_LINK(\"dma_mr\", SysBusPCNetState, dma_mr,\n+ TYPE_MEMORY_REGION, MemoryRegion *),\n DEFINE_NIC_PROPERTIES(SysBusPCNetState, state.conf),\n };\n \ndiff --git a/hw/net/meson.build b/hw/net/meson.build\nindex 3102587469..e653a9bc73 100644\n--- a/hw/net/meson.build\n+++ b/hw/net/meson.build\n@@ -31,7 +31,8 @@ system_ss.add(when: 'CONFIG_MARVELL_88W8618', if_true: files('mv88w8618_eth.c'))\n \n system_ss.add(when: 'CONFIG_CADENCE', if_true: files('cadence_gem.c'))\n system_ss.add(when: 'CONFIG_STELLARIS_ENET', if_true: files('stellaris_enet.c'))\n-system_ss.add(when: 'CONFIG_LANCE', if_true: files('lance.c'))\n+# LANCE uses target-specific memory types (e.g., target_ulong) and must be compiled per-target.\n+specific_ss.add(when: 'CONFIG_LANCE', if_true: files('lance.c'))\n system_ss.add(when: 'CONFIG_LASI_82596', if_true: files('lasi_i82596.c'))\n system_ss.add(when: 'CONFIG_I82596_COMMON', if_true: files('i82596.c'))\n system_ss.add(when: 'CONFIG_SUNHME', if_true: files('sunhme.c'))\ndiff --git a/include/hw/net/lance.h b/include/hw/net/lance.h\nindex be473e2eed..706160d7eb 100644\n--- a/include/hw/net/lance.h\n+++ b/include/hw/net/lance.h\n@@ -31,6 +31,7 @@\n \n #include \"net/net.h\"\n #include \"hw/net/pcnet.h\"\n+#include \"system/memory.h\"\n #include \"hw/core/sysbus.h\"\n #include \"qom/object.h\"\n \n@@ -43,6 +44,8 @@ struct SysBusPCNetState {\n SysBusDevice parent_obj;\n \n PCNetState state;\n+ MemoryRegion *dma_mr;\n+ AddressSpace dma_as;\n };\n \n #endif\n","prefixes":["2/7"]}