{"id":2232120,"url":"http://patchwork.ozlabs.org/api/patches/2232120/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/088f06e9-1c12-4829-96cf-ab25c169e033@yahoo.co.jp/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<088f06e9-1c12-4829-96cf-ab25c169e033@yahoo.co.jp>","list_archive_url":null,"date":"2026-05-02T18:16:03","name":"[v2,4/4] doc: Document several \"force_l32\" features for Xtensa","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"0617916fc77cc1e78ea4fa54290b294895c869e6","submitter":{"id":83997,"url":"http://patchwork.ozlabs.org/api/people/83997/?format=json","name":"Takayuki 'January June' Suwa","email":"jjsuwa_sys3175@yahoo.co.jp"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/088f06e9-1c12-4829-96cf-ab25c169e033@yahoo.co.jp/mbox/","series":[{"id":502546,"url":"http://patchwork.ozlabs.org/api/series/502546/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=502546","date":"2026-05-02T18:14:43","name":"[v2,1/4] xtensa: Implement \"__force_l32\" named address space","version":2,"mbox":"http://patchwork.ozlabs.org/series/502546/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2232120/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2232120/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=yahoo.co.jp header.i=@yahoo.co.jp header.a=rsa-sha256\n header.s=yahoocojp-202506 header.b=Tpg8deBd;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1777745763;\n s=yahoocojp-202506; d=yahoo.co.jp;\n h=References:Content-Transfer-Encoding:Content-Type:Subject:From:Cc:To:MIME-Version:Date:Message-ID;\n bh=7NHV23DDnfDbCLsjnQnRE8Djy4gEixuUL1Vi2DqyX1o=;\n b=Tpg8deBdHYMMOB/js9feZ0LuAj9VHVY+J7KyM5OcHen6wZJNVVf5IGk+kvo9DPyD\n +7d6ZE/RxiWQtxLt/UPxn3BlggEilZ2vnrdHcTx9dDldyvEyJEq4tOL+v7febx1CokA\n 7fMjGrrJLPmwq6gtD/ZosLmMDNInwvunzP1nUyha95oqj46ipjswY1a7em0oF7wbZF/\n f0gcTDR5J6lZXp/mAP+oVHqvx3Fb9/5HKYn6rzNnPQ8GlSQQ+CX1HTTP7RaUkPiqRPE\n lSwzDZte9OpVotNofawV1N0hkeq6afpe1QCpBgHcmmd1KNbvkpXoVpN8PqEvEJM4faR\n DG2Q3YCT7w==","Message-ID":"<088f06e9-1c12-4829-96cf-ab25c169e033@yahoo.co.jp>","Date":"Sun, 3 May 2026 03:16:03 +0900","MIME-Version":"1.0","User-Agent":"Mozilla Thunderbird","Content-Language":"en-US","To":"gcc-patches@gcc.gnu.org","Cc":"Max Filippov ","From":"Takayuki 'January June' Suwa ","Subject":"[PATCH v2 4/4] doc: Document several \"force_l32\" features for Xtensa","Content-Type":"text/plain; charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit","References":"<088f06e9-1c12-4829-96cf-ab25c169e033.ref@yahoo.co.jp>","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"This patch adds documentation for the \"force_l32\" features of the Xtensa\ntarget that were added in recent patches.\n\ngcc/ChangeLog:\n\n\t* doc/extend.texi (Xtensa Named Address Spaces):\n\tDocument '__force_l32'.\n\t(Xtensa Attributes): Document 'force_l32'.\n\t* doc/invoke.texi (Xtensa Options):\n\tDocument '-m[no-]force-l32'.\n---\n gcc/doc/extend.texi | 73 ++++++++++++++++++++++++++++++++++++++++++++-\n gcc/doc/invoke.texi | 15 +++++++++-\n 2 files changed, 86 insertions(+), 2 deletions(-)","diff":"diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi\nindex 0faa5323ce1..8dd0b3137bc 100644\n--- a/gcc/doc/extend.texi\n+++ b/gcc/doc/extend.texi\n@@ -1379,7 +1379,7 @@ As an extension, GNU C supports named address spaces as\n defined in the N1275 draft of ISO/IEC DTR 18037. Support for named\n address spaces in GCC will evolve as the draft technical report\n changes. Calling conventions for any target might also change. At\n-present, only the AVR, M32C, PRU, RL78, and x86 targets support\n+present, only the AVR, M32C, PRU, RL78, x86 and Xtensa targets support\n address spaces other than the generic address space.\n \n Address space identifiers may be used exactly like any other C type\n@@ -1618,6 +1618,55 @@ The preprocessor symbols @code{__SEG_FS} and @code{__SEG_GS} are\n defined when these address spaces are supported.\n @end table\n \n+@anchor{Xtensa Named Address Spaces}\n+@subsection Xtensa Named Address Spaces\n+@cindex @code{__force_l32} Xtensa Named Address Spaces\n+\n+On the Xtensa target, when a variable qualified with @code{__force_l32}\n+is loaded from memory, it is always read aligned to a 4-byte width\n+regardless of whether its width is 1 or 2 bytes, and a bit-extraction\n+instruction is applied to the read to obtain the desired result; writing\n+with a width of 1 or 2 bytes is not supported (see also @code{force_l32}\n+attribute described in @ref{Xtensa Attributes}, and command-line option\n+@option{-mforce-l32} described in @ref{Xtensa Options}).\n+\n+@smallexample\n+char *strcpy_irom (char *dst, __force_l32 const char *src)\n+@{\n+ char *p = dst;\n+ /* \"*src\" is always read as an aligned 4-byte width, and then\n+ the desired one byte is extracted using bitwise operations. */\n+ while (*p = *src)\n+ ++p, ++src;\n+ return dst;\n+@}\n+@end smallexample\n+\n+Qualifying a variable with @code{__force_l32} affects how that variable\n+is read as mentioned above, but it does not affect the memory section in\n+which the variable is placed (this can be specified separately using the\n+@code{section} attribute).\n+\n+@smallexample\n+/* Instruction ROM reading requires aligned 4-byte width access. */\n+__force_l32 const char IROM_message[] __attribute__((section(\".irom.text\")))\n+ = \"placed within the instruction ROM area.\";\n+@end smallexample\n+\n+A pointer qualified with @code{__force_l32} can read memory regions in\n+the generic address space (though not very efficiently), but not vice\n+versa. Therefore, the conversion from a pointer for the generic address\n+space to a pointer qualified with @code{__force_l32} is implicit, but not\n+the other way around.\n+\n+@smallexample\n+extern char *strcpy_irom (char *, __force_l32 const char *);\n+char buf[80], alt_buf[80];\n+\n+strcpy_irom (buf, IROM_message);\n+strcpy_irom (alt_buf, \"placed within read-only RAM area.\");\n+@end smallexample\n+\n @anchor{Function Attributes}\n @anchor{Variable Attributes}\n @anchor{Type Attributes}\n@@ -5729,6 +5778,7 @@ The default for the attribute is controlled by @option{-fzero-call-used-regs}.\n * Visium Attributes::\n * x86 Attributes::\n * Xstormy16 Attributes::\n+* Xtensa Attributes::\n @end menu\n \n @anchor{AArch64 Function Attributes}\n@@ -9810,6 +9860,27 @@ placed in either the @code{.bss_below100} section or the\n @code{.data_below100} section.\n @end table\n \n+@node Xtensa Attributes\n+@subsubsection Xtensa Attributes\n+\n+These attributes are supported by the Xtensa back end:\n+\n+@table @code\n+@atindex @code{force_l32}, Xtensa\n+@item force_l32\n+This attribute can be applied to variables, function parameters and\n+types.\n+\n+When this attribute is specified in a declaration, any memory loads of 1-\n+or 2-byte width objects for the type (in the declaration) itself and all\n+the underlying types contained within it are performed by a combination\n+of aligned 4-byte load and bit-extraction instructions, rather than by\n+instructions dedicated to those objects; storing memory with a width of 1\n+or 2 bytes is not supported (see also @code{__force_l32} address spaces\n+described in @ref{Xtensa Named Address Spaces}, and command-line option\n+@option{-mforce-l32} described in @ref{Xtensa Options}).\n+\n+@end table\n \n @node Attribute Syntax\n @subsection GNU Attribute Syntax\ndiff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi\nindex 756af474310..fb69dc5fb80 100644\n--- a/gcc/doc/invoke.texi\n+++ b/gcc/doc/invoke.texi\n@@ -1593,7 +1593,7 @@ See Cygwin and MinGW Options.\n @gccoptlist{-mconst16 -mforce-no-pic -mno-serialize-volatile\n -mtext-section-literals -mauto-litpools -mno-target-align\n -mlongcalls -mabi=@var{abi-type}\n--mextra-l32r-costs=@var{cycles} -mstrict-align}\n+-mextra-l32r-costs=@var{cycles} -mstrict-align -mforce-l32}\n \n @emph{zSeries Options}\n See S/390 and zSeries Options.\n@@ -37518,6 +37518,19 @@ The default is @option{-mno-strict-align} for cores that support both\n unaligned loads and stores in hardware and @option{-mstrict-align} for all\n other cores.\n \n+@opindex mforce-l32\n+@opindex mno-force-l32\n+@item -mforce-l32\n+@itemx -mno-force-l32\n+When this option is enabled, GCC performs 1- or 2-byte loads in the generic\n+address space (ie., default memory references) by bit-extracting the desired\n+portion from the result of an aligned 4-byte load, instead of the instructions\n+originally provided for those purposes. This option does not affect memory\n+stores of such byte width, or the placement of those memory sections (see\n+also @code{__force_l32} address spaces described in\n+@ref{Xtensa Named Address Spaces}, and @code{force_l32} attribute described\n+in @ref{Xtensa Attributes}). The default is @option{-mno-force-l32}.\n+\n @end table\n \n @node zSeries Options\n","prefixes":["v2","4/4"]}