{"id":2232117,"url":"http://patchwork.ozlabs.org/api/patches/2232117/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/63a2d5f9-5dd1-49d3-8984-5db4a9a7a81a@yahoo.co.jp/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<63a2d5f9-5dd1-49d3-8984-5db4a9a7a81a@yahoo.co.jp>","list_archive_url":null,"date":"2026-05-02T18:14:43","name":"[v2,3/4] xtensa: Implement \"-mforce-l32\" target-specific option","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"91789bd7903fc061fbc385911a5ae182345423d7","submitter":{"id":83997,"url":"http://patchwork.ozlabs.org/api/people/83997/?format=json","name":"Takayuki 'January June' Suwa","email":"jjsuwa_sys3175@yahoo.co.jp"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/63a2d5f9-5dd1-49d3-8984-5db4a9a7a81a@yahoo.co.jp/mbox/","series":[{"id":502546,"url":"http://patchwork.ozlabs.org/api/series/502546/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=502546","date":"2026-05-02T18:14:43","name":"[v2,1/4] xtensa: Implement \"__force_l32\" named address space","version":2,"mbox":"http://patchwork.ozlabs.org/series/502546/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2232117/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2232117/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=yahoo.co.jp header.i=@yahoo.co.jp header.a=rsa-sha256\n header.s=yahoocojp-202506 header.b=jsV7bM/3;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1777745683;\n s=yahoocojp-202506; d=yahoo.co.jp;\n h=References:Content-Transfer-Encoding:Content-Type:Subject:From:Cc:To:MIME-Version:Date:Message-ID;\n bh=s7VGvRMgjnE9Tb7vI84T1uVtlj46o1HdsIJ1TQFjGes=;\n b=jsV7bM/3ijPr0KpbLSwCB03IF4378WWJhOe7t5wcXuYrhosCu1l1hIAdjtx9060k\n 2CBdcOud8vZi6RZuuKrOmTIPscA0DAnsX1lIfYTG+mVJNlspH66kMigtHbBYf+Izgyo\n jTpI/5/VH4MLDIimF38fgoKHsnn4DfgKsLxDsRMeE+EoyoyI9+pD9MHkDX/6f6OxejI\n RPRhNyKJ7ucGHLmjki19TaFM5jaddkG6eYjc5/GMJdsWUG/rPCnKFjSdK1JqyDJsk4Q\n WYqwrBDPttqjIcVJOrT3WZEFRW36Ztyu8vJhCYp1aMBo4p1LiM2qjA8sHrj2G4Wxw99\n YF9Bc6LXBw==","Message-ID":"<63a2d5f9-5dd1-49d3-8984-5db4a9a7a81a@yahoo.co.jp>","Date":"Sun, 3 May 2026 03:14:43 +0900","MIME-Version":"1.0","User-Agent":"Mozilla Thunderbird","Content-Language":"en-US","To":"gcc-patches@gcc.gnu.org","Cc":"Max Filippov ","From":"Takayuki 'January June' Suwa ","Subject":"[PATCH v2 3/4] xtensa: Implement \"-mforce-l32\" target-specific option","Content-Type":"text/plain; charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit","References":"<63a2d5f9-5dd1-49d3-8984-5db4a9a7a81a.ref@yahoo.co.jp>","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"In the previous patches, both the named address space \"__force_l32\" and\nthe target-specific attribute \"force_l32\" were introduced for reading\nsub-words from the instruction memory area.\n\nThis patch introduces a new target-specific option \"-mforce-l32\", which\nallows sub-word reading from the instruction memory area even in the\ngeneric address spaces (ie., the default memory references) or without\nthe \"force_l32\" attribute.\n\n /* example */\n int test(unsigned int i) {\n static const char string[] __attribute__((section(\".irom.text\")))\n = \"The quick brown fox jumps over the lazy dog.\";\n return i < __builtin_strlen(string) ? string[i] : -1;\n }\n\n ;; result (-O2 -mforce-l32)\n \t.literal_position\n \t.literal .LC0, string$0\n test:\n \tentry\tsp, 32\n \tmovi.n\ta8, 0x2b\n \tbltu\ta8, a2, .L3\n \tl32r\ta9, .LC0\t;; If -mno-force-l32,\n \tmovi.n\ta8, -4\t\t;;\n \tadd.n\ta9, a9, a2\t;;\tl32r\ta8, .LC0\n \tand\ta8, a9, a8\t;;\tadd.n\ta8, a8, a2\n \tl32i.n\ta8, a8, 0\t;;\tl8ui\ta2, a8, 0\n \tssa8l\ta9\t\t;;\n \tsrl\ta8, a8\t\t;;\n \textui\ta2, a8, 0, 8\t;;\n \tretw.n\n .L3:\n \tmovi.n\ta2, -1\n \tretw.n\n \t.section .irom.text,\"a\"\n string$0:\n \t.string\t\"The quick brown fox jumps over the lazy dog.\"\n\ngcc/ChangeLog:\n\n\t* config/xtensa/xtensa.cc (xtensa_expand_load_force_l32_2):\n\tNew sub-function for inspecting pseudos that clearly point to the\n\tfunction's stack frame.\n\t(xtensa_expand_load_force_l32):\n\tAdd handling for loading from the generic address space when the\n\t\"-mforce-l32\" option is enabled, however, obvious references to\n\tfunction stack frames are excluded.\n\t* config/xtensa/xtensa.opt (mforce-l32):\n\tNew target-specific option definition.\n---\n gcc/config/xtensa/xtensa.cc | 36 ++++++++++++++++++++++++++++++++----\n gcc/config/xtensa/xtensa.opt | 4 ++++\n 2 files changed, 36 insertions(+), 4 deletions(-)","diff":"diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc\nindex 1b4aa8934ff..5a9b18de1ce 100644\n--- a/gcc/config/xtensa/xtensa.cc\n+++ b/gcc/config/xtensa/xtensa.cc\n@@ -2628,7 +2628,7 @@ xtensa_emit_add_imm (rtx dst, rtx src, HOST_WIDE_INT imm, rtx scratch,\n load with bit-extraction of the required bytes. */\n \n static bool\n-xtensa_expand_load_force_l32_1 (rtx mem)\n+xtensa_expand_load_force_l32_1 (const_rtx mem)\n {\n tree expr = MEM_EXPR (mem), type;\n \n@@ -2639,6 +2639,29 @@ xtensa_expand_load_force_l32_1 (rtx mem)\n \t && lookup_attribute (\"force_l32\", TYPE_ATTRIBUTES (type));\n }\n \n+static bool\n+xtensa_expand_load_force_l32_2 (const_rtx reg)\n+{\n+ unsigned int regno;\n+\n+ /* These pseudos are unlikely to be passed during the RTL generation,\n+ but just in case. */\n+ switch (regno = REGNO (reg))\n+ {\n+ case STACK_POINTER_REGNUM:\n+ case FRAME_POINTER_REGNUM:\n+ case ARG_POINTER_REGNUM:\n+ return true;\n+ }\n+\n+ /* gccint explicitly states that these pseudos indicate the location of\n+ the stack frame. In addition, the static chain pointers also clearly\n+ refer to the stack frame. */\n+ return IN_RANGE (regno, FIRST_VIRTUAL_REGISTER, LAST_VIRTUAL_REGISTER)\n+\t || (cfun && cfun->static_chain_decl\n+\t && cfun->static_chain_decl == REG_EXPR (regno_reg_rtx[regno]));\n+}\n+\n bool\n xtensa_expand_load_force_l32 (rtx *operands, machine_mode dest_mode,\n \t\t\t machine_mode src_mode, int unsignedp)\n@@ -2670,13 +2693,17 @@ xtensa_expand_load_force_l32 (rtx *operands, machine_mode dest_mode,\n \n /* Exclude insns that do not perform memory loading with \"force_l32\". */\n if (MEM_ADDR_SPACE (src) != ADDR_SPACE_FORCE_L32\n- && ! xtensa_expand_load_force_l32_1 (src))\n+ && ! xtensa_expand_load_force_l32_1 (src)\n+ && (!TARGET_FORCE_L32 || MEM_ADDR_SPACE (src) != ADDR_SPACE_GENERIC))\n return false;\n \n /* As a preprocessing, handle cases where addr is (PLUS (REG, OFFSET))\n form. */\n if (REG_P (addr = XEXP (src, 0)))\n- ;\n+ {\n+ if (xtensa_expand_load_force_l32_2 (addr))\n+\treturn false;\n+ }\n else if (GET_CODE (addr) == PLUS)\n {\n rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);\n@@ -2684,7 +2711,8 @@ xtensa_expand_load_force_l32 (rtx *operands, machine_mode dest_mode,\n \n if (! CONST_INT_P (op1))\n \tstd::swap (op0, op1);\n- if (! REG_P (op0) || ! CONST_INT_P (op1))\n+ if (! REG_P (op0) || ! CONST_INT_P (op1)\n+\t || xtensa_expand_load_force_l32_2 (op0))\n \treturn false;\n if ((v = INTVAL (op1)) == 0)\n \taddr = op0;\ndiff --git a/gcc/config/xtensa/xtensa.opt b/gcc/config/xtensa/xtensa.opt\nindex aee776f124e..90665ba180c 100644\n--- a/gcc/config/xtensa/xtensa.opt\n+++ b/gcc/config/xtensa/xtensa.opt\n@@ -71,3 +71,7 @@ Use windowed registers ABI.\n mstrict-align\n Target Var(xtensa_strict_alignment) Init(XTENSA_STRICT_ALIGNMENT_UNDEFINED)\n Do not use unaligned memory references.\n+\n+mforce-l32\n+Target Mask(FORCE_L32)\n+Use L32I instruction to access 1- and 2-byte quantities in memory instead of L8UI/L16UI/L16SI.\n","prefixes":["v2","3/4"]}