{"id":2231466,"url":"http://patchwork.ozlabs.org/api/patches/2231466/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430172204.1006673-32-pbonzini@redhat.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260430172204.1006673-32-pbonzini@redhat.com>","list_archive_url":null,"date":"2026-04-30T17:21:37","name":"[PULL,31/58] whpx: i386: use WHvX64RegisterCr8 only when kernel-irqchip=off","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"fdf8a7880917f8e1e26cefbbd6846b1aeb98968d","submitter":{"id":2701,"url":"http://patchwork.ozlabs.org/api/people/2701/?format=json","name":"Paolo Bonzini","email":"pbonzini@redhat.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430172204.1006673-32-pbonzini@redhat.com/mbox/","series":[{"id":502347,"url":"http://patchwork.ozlabs.org/api/series/502347/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502347","date":"2026-04-30T17:21:16","name":"[PULL,01/58] pythondeps: bump to meson 1.11.1","version":1,"mbox":"http://patchwork.ozlabs.org/series/502347/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2231466/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2231466/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256\n header.s=mimecast20190719 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SMTP id\n d75a77b69052e-5102afa4e75mr53971391cf.57.1777569825130;\n Thu, 30 Apr 2026 10:23:45 -0700 (PDT)","by 2002:a05:622a:513:b0:50f:b81e:c655 with SMTP id\n d75a77b69052e-5102afa4e75mr53970681cf.57.1777569824459;\n Thu, 30 Apr 2026 10:23:44 -0700 (PDT)"],"From":"Paolo Bonzini ","To":"qemu-devel@nongnu.org","Cc":"Mohamed Mediouni ","Subject":"[PULL 31/58] whpx: i386: use WHvX64RegisterCr8 only when\n kernel-irqchip=off","Date":"Thu, 30 Apr 2026 19:21:37 +0200","Message-ID":"<20260430172204.1006673-32-pbonzini@redhat.com>","X-Mailer":"git-send-email 2.54.0","In-Reply-To":"<20260430172204.1006673-1-pbonzini@redhat.com>","References":"<20260430172204.1006673-1-pbonzini@redhat.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=170.10.133.124;\n envelope-from=pbonzini@redhat.com;\n helo=us-smtp-delivery-124.mimecast.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Mohamed Mediouni \n\nWhen kernel-irqchip=on, manage TPR as part of the APIC state instead entirely.\n\nThis fixes some failure to set state errors.\n\nSigned-off-by: Mohamed Mediouni \nLink: https://lore.kernel.org/r/20260422214225.2242-10-mohamed@unpredictable.fr\nSigned-off-by: Paolo Bonzini \n---\n target/i386/whpx/whpx-all.c | 37 ++++++++++++++++++++++---------------\n 1 file changed, 22 insertions(+), 15 deletions(-)","diff":"diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c\nindex d470c5b9d37..03c146dfb8c 100644\n--- a/target/i386/whpx/whpx-all.c\n+++ b/target/i386/whpx/whpx-all.c\n@@ -95,7 +95,6 @@ static const WHV_REGISTER_NAME whpx_register_names[] = {\n WHvX64RegisterCr2,\n WHvX64RegisterCr3,\n WHvX64RegisterCr4,\n- WHvX64RegisterCr8,\n \n /* X64 Debug Registers */\n /*\n@@ -478,8 +477,11 @@ void whpx_set_registers(CPUState *cpu, WHPXStateLevel level)\n vcxt.values[idx++].Reg64 = env->cr[3];\n assert(whpx_register_names[idx] == WHvX64RegisterCr4);\n vcxt.values[idx++].Reg64 = env->cr[4];\n- assert(whpx_register_names[idx] == WHvX64RegisterCr8);\n- vcxt.values[idx++].Reg64 = vcpu->tpr;\n+ /* For kernel-irqchip=on, TPR is managed as part of APIC state */\n+ if (!whpx_irqchip_in_kernel()) {\n+ WHV_REGISTER_VALUE cr8 = {.Reg64 = vcpu->tpr};\n+ whpx_set_reg(cpu, WHvX64RegisterCr8, cr8);\n+ }\n \n /* 8 Debug Registers - Skipped */\n \n@@ -735,11 +737,14 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel level)\n env->cr[3] = vcxt.values[idx++].Reg64;\n assert(whpx_register_names[idx] == WHvX64RegisterCr4);\n env->cr[4] = vcxt.values[idx++].Reg64;\n- assert(whpx_register_names[idx] == WHvX64RegisterCr8);\n- tpr = vcxt.values[idx++].Reg64;\n- if (tpr != vcpu->tpr) {\n- vcpu->tpr = tpr;\n- cpu_set_apic_tpr(x86_cpu->apic_state, tpr);\n+\n+ /* For kernel-irqchip=on, TPR is managed as part of APIC state */\n+ if (!whpx_irqchip_in_kernel()) {\n+ tpr = vcpu->exit_ctx.VpContext.Cr8;\n+ if (tpr != vcpu->tpr) {\n+ vcpu->tpr = tpr;\n+ cpu_set_apic_tpr(x86_cpu->apic_state, tpr);\n+ }\n }\n \n /* 8 Debug Registers - Skipped */\n@@ -1745,7 +1750,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n \n /* Sync the TPR to the CR8 if was modified during the intercept */\n tpr = cpu_get_apic_tpr(x86_cpu->apic_state);\n- if (tpr != vcpu->tpr) {\n+ if (!whpx_irqchip_in_kernel() && tpr != vcpu->tpr) {\n vcpu->tpr = tpr;\n reg_values[reg_count].Reg64 = tpr;\n qatomic_set(&cpu->exit_request, true);\n@@ -1787,12 +1792,14 @@ static void whpx_vcpu_post_run(CPUState *cpu)\n \n env->eflags = vcpu->exit_ctx.VpContext.Rflags;\n \n- uint64_t tpr = vcpu->exit_ctx.VpContext.Cr8;\n- if (vcpu->tpr != tpr) {\n- vcpu->tpr = tpr;\n- bql_lock();\n- cpu_set_apic_tpr(x86_cpu->apic_state, vcpu->tpr);\n- bql_unlock();\n+ if (!whpx_irqchip_in_kernel()) {\n+ uint64_t tpr = vcpu->exit_ctx.VpContext.Cr8;\n+ if (vcpu->tpr != tpr) {\n+ vcpu->tpr = tpr;\n+ bql_lock();\n+ cpu_set_apic_tpr(x86_cpu->apic_state, vcpu->tpr);\n+ bql_unlock();\n+ }\n }\n \n vcpu->interruption_pending =\n","prefixes":["PULL","31/58"]}