{"id":2231451,"url":"http://patchwork.ozlabs.org/api/patches/2231451/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430172204.1006673-36-pbonzini@redhat.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260430172204.1006673-36-pbonzini@redhat.com>","list_archive_url":null,"date":"2026-04-30T17:21:41","name":"[PULL,35/58] whpx: i386: interrupt priority support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"a8928d6db7320caa8f26526718c6a0a6a64b31e1","submitter":{"id":2701,"url":"http://patchwork.ozlabs.org/api/people/2701/?format=json","name":"Paolo Bonzini","email":"pbonzini@redhat.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430172204.1006673-36-pbonzini@redhat.com/mbox/","series":[{"id":502347,"url":"http://patchwork.ozlabs.org/api/series/502347/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502347","date":"2026-04-30T17:21:16","name":"[PULL,01/58] pythondeps: bump to meson 1.11.1","version":1,"mbox":"http://patchwork.ozlabs.org/series/502347/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2231451/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2231451/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256\n header.s=mimecast20190719 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SMTP id\n af79cd13be357-8fab2140c16mr480772585a.54.1777569837500;\n Thu, 30 Apr 2026 10:23:57 -0700 (PDT)","by 2002:a05:620a:4627:b0:8d0:191:69b5 with SMTP id\n af79cd13be357-8fab2140c16mr480763285a.54.1777569836657;\n Thu, 30 Apr 2026 10:23:56 -0700 (PDT)"],"From":"Paolo Bonzini ","To":"qemu-devel@nongnu.org","Cc":"Mohamed Mediouni ","Subject":"[PULL 35/58] whpx: i386: interrupt priority support","Date":"Thu, 30 Apr 2026 19:21:41 +0200","Message-ID":"<20260430172204.1006673-36-pbonzini@redhat.com>","X-Mailer":"git-send-email 2.54.0","In-Reply-To":"<20260430172204.1006673-1-pbonzini@redhat.com>","References":"<20260430172204.1006673-1-pbonzini@redhat.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=170.10.129.124;\n envelope-from=pbonzini@redhat.com;\n helo=us-smtp-delivery-124.mimecast.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Mohamed Mediouni \n\nImplement APIC IRR interrupt priorities.\n\nEven with kernel-irqchip=off, Hyper-V is aware of interrupt priorities\nand implements CR8/TPR, with the InterruptPriority field being followed.\n\nSigned-off-by: Mohamed Mediouni \nLink: https://lore.kernel.org/r/20260422214225.2242-14-mohamed@unpredictable.fr\nSigned-off-by: Paolo Bonzini \n---\n target/i386/whpx/whpx-all.c | 24 ++++++++++++++++++++----\n 1 file changed, 20 insertions(+), 4 deletions(-)","diff":"diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c\nindex cbcf1de7ae4..012fa6d0216 100644\n--- a/target/i386/whpx/whpx-all.c\n+++ b/target/i386/whpx/whpx-all.c\n@@ -1673,6 +1673,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n UINT32 reg_count = 0;\n WHV_REGISTER_VALUE reg_values[3];\n WHV_REGISTER_NAME reg_names[3];\n+ int irr = apic_get_highest_priority_irr(x86_cpu->apic_state);\n \n memset(&new_int, 0, sizeof(new_int));\n memset(reg_values, 0, sizeof(reg_values));\n@@ -1708,10 +1709,20 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n }\n }\n \n+ if (irr == -1) {\n+ if (isa_pic != NULL && pic_get_output(isa_pic)) {\n+ /* In case it's a PIC interrupt */\n+ irr = 0;\n+ } else if (cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) {\n+ abort();\n+ }\n+ }\n+\n /* Get pending hard interruption or replay one that was overwritten */\n if (!whpx_irqchip_in_kernel()) {\n if (!vcpu->interruption_pending &&\n- vcpu->interruptable && (env->eflags & IF_MASK)) {\n+ vcpu->interruptable && (env->eflags & IF_MASK)\n+ && (vcpu->tpr < irr || irr == 0)) {\n assert(!new_int.InterruptionPending);\n if (cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) {\n cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD);\n@@ -1768,13 +1779,17 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n }\n \n /* Update the state of the interrupt delivery notification */\n- if (!vcpu->window_registered &&\n+ if ((!vcpu->window_registered ||\n+ (vcpu->window_priority < irr && vcpu->window_priority != 0) ||\n+ (irr == 0 && vcpu->window_priority != 0)) &&\n cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) {\n reg_values[reg_count].DeliverabilityNotifications =\n (WHV_X64_DELIVERABILITY_NOTIFICATIONS_REGISTER) {\n- .InterruptNotification = 1\n+ .InterruptNotification = 1,\n+ .InterruptPriority = irr >> 4\n };\n vcpu->window_registered = 1;\n+ vcpu->window_priority = irr;\n reg_names[reg_count] = WHvX64RegisterDeliverabilityNotifications;\n reg_count += 1;\n }\n@@ -1788,7 +1803,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n reg_names, reg_count, reg_values);\n if (FAILED(hr)) {\n error_report(\"WHPX: Failed to set interrupt state registers,\"\n- \" hr=%08lx\", hr);\n+ \" hr=%08lx, InterruptPriority=%i\", hr, irr >> 4);\n }\n }\n }\n@@ -2004,6 +2019,7 @@ int whpx_vcpu_run(CPUState *cpu)\n case WHvRunVpExitReasonX64InterruptWindow:\n vcpu->ready_for_pic_interrupt = 1;\n vcpu->window_registered = 0;\n+ vcpu->window_priority = 0;\n ret = 0;\n break;\n \n","prefixes":["PULL","35/58"]}