{"id":2231444,"url":"http://patchwork.ozlabs.org/api/patches/2231444/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430172204.1006673-38-pbonzini@redhat.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260430172204.1006673-38-pbonzini@redhat.com>","list_archive_url":null,"date":"2026-04-30T17:21:43","name":"[PULL,37/58] whpx: i386: fix CPUID[1:EDX].APIC reporting","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"d74f1a39346ba8c0ce97fec82b0b73bd803b8120","submitter":{"id":2701,"url":"http://patchwork.ozlabs.org/api/people/2701/?format=json","name":"Paolo Bonzini","email":"pbonzini@redhat.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430172204.1006673-38-pbonzini@redhat.com/mbox/","series":[{"id":502347,"url":"http://patchwork.ozlabs.org/api/series/502347/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502347","date":"2026-04-30T17:21:16","name":"[PULL,01/58] pythondeps: bump to meson 1.11.1","version":1,"mbox":"http://patchwork.ozlabs.org/series/502347/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2231444/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2231444/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256\n header.s=mimecast20190719 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SMTP id\n d75a77b69052e-5102ab1c0abmr56558881cf.12.1777569843696;\n Thu, 30 Apr 2026 10:24:03 -0700 (PDT)","by 2002:a05:622a:199d:b0:50f:ae60:25ab with SMTP id\n d75a77b69052e-5102ab1c0abmr56558101cf.12.1777569843084;\n Thu, 30 Apr 2026 10:24:03 -0700 (PDT)"],"From":"Paolo Bonzini ","To":"qemu-devel@nongnu.org","Cc":"Mohamed Mediouni ","Subject":"[PULL 37/58] whpx: i386: fix CPUID[1:EDX].APIC reporting","Date":"Thu, 30 Apr 2026 19:21:43 +0200","Message-ID":"<20260430172204.1006673-38-pbonzini@redhat.com>","X-Mailer":"git-send-email 2.54.0","In-Reply-To":"<20260430172204.1006673-1-pbonzini@redhat.com>","References":"<20260430172204.1006673-1-pbonzini@redhat.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=170.10.129.124;\n envelope-from=pbonzini@redhat.com;\n helo=us-smtp-delivery-124.mimecast.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Mohamed Mediouni \n\nHyper-V always has CPUID[1:EDX].APIC set, even when the APIC isn't enabled yet.\n\nWork around this by also using the APICBASE trap for kernel-irqchip=on.\n\nSigned-off-by: Mohamed Mediouni \nLink: https://lore.kernel.org/r/20260422214225.2242-16-mohamed@unpredictable.fr\nSigned-off-by: Paolo Bonzini \n---\n include/system/whpx-common.h | 1 -\n target/i386/whpx/whpx-all.c | 34 ++++++++---------\n target/i386/whpx/whpx-apic.c | 71 ++++++++++++++++++++++++++++++++++--\n 3 files changed, 84 insertions(+), 22 deletions(-)","diff":"diff --git a/include/system/whpx-common.h b/include/system/whpx-common.h\nindex 3406c20fec0..79710e2fb3c 100644\n--- a/include/system/whpx-common.h\n+++ b/include/system/whpx-common.h\n@@ -8,7 +8,6 @@ struct AccelCPUState {\n bool interruptable;\n bool ready_for_pic_interrupt;\n uint64_t tpr;\n- uint64_t apic_base;\n bool interruption_pending;\n /* Must be the last field as it may have a tail */\n WHV_RUN_VP_EXIT_CONTEXT exit_ctx;\ndiff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c\nindex 012fa6d0216..b0556445801 100644\n--- a/target/i386/whpx/whpx-all.c\n+++ b/target/i386/whpx/whpx-all.c\n@@ -139,7 +139,6 @@ static const WHV_REGISTER_NAME whpx_register_names[] = {\n #ifdef TARGET_X86_64\n WHvX64RegisterKernelGsBase,\n #endif\n- WHvX64RegisterApicBase,\n /* WHvX64RegisterPat, */\n WHvX64RegisterSysenterCs,\n WHvX64RegisterSysenterEip,\n@@ -420,7 +419,6 @@ void whpx_set_registers(CPUState *cpu, WHPXStateLevel level)\n r86 = !(env->cr[0] & CR0_PE_MASK);\n \n vcpu->tpr = cpu_get_apic_tpr(x86_cpu->apic_state);\n- vcpu->apic_base = cpu_get_apic_base(x86_cpu->apic_state);\n \n idx = 0;\n \n@@ -538,9 +536,6 @@ void whpx_set_registers(CPUState *cpu, WHPXStateLevel level)\n vcxt.values[idx++].Reg64 = env->kernelgsbase;\n #endif\n \n- assert(whpx_register_names[idx] == WHvX64RegisterApicBase);\n- vcxt.values[idx++].Reg64 = vcpu->apic_base;\n-\n /* WHvX64RegisterPat - Skipped */\n \n assert(whpx_register_names[idx] == WHvX64RegisterSysenterCs);\n@@ -575,6 +570,12 @@ void whpx_set_registers(CPUState *cpu, WHPXStateLevel level)\n error_report(\"WHPX: Failed to set virtual processor context, hr=%08lx\",\n hr);\n }\n+\n+ if (level >= WHPX_LEVEL_FULL_STATE) {\n+ WHV_REGISTER_VALUE apic_base = {};\n+ apic_base.Reg64 = cpu_get_apic_base(X86_CPU(cpu)->apic_state);\n+ whpx_set_reg(cpu, WHvX64RegisterApicBase, apic_base);\n+ }\n }\n \n static int whpx_get_tsc(CPUState *cpu)\n@@ -666,7 +667,7 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel level)\n X86CPU *x86_cpu = X86_CPU(cpu);\n CPUX86State *env = &x86_cpu->env;\n struct whpx_register_set vcxt;\n- uint64_t tpr, apic_base;\n+ uint64_t tpr;\n HRESULT hr;\n int idx;\n int idx_next;\n@@ -798,13 +799,6 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel level)\n env->kernelgsbase = vcxt.values[idx++].Reg64;\n #endif\n \n- assert(whpx_register_names[idx] == WHvX64RegisterApicBase);\n- apic_base = vcxt.values[idx++].Reg64;\n- if (apic_base != vcpu->apic_base) {\n- vcpu->apic_base = apic_base;\n- cpu_set_apic_base(x86_cpu->apic_state, vcpu->apic_base);\n- }\n-\n /* WHvX64RegisterPat - Skipped */\n \n assert(whpx_register_names[idx] == WHvX64RegisterSysenterCs);\n@@ -2082,8 +2076,7 @@ int whpx_vcpu_run(CPUState *cpu)\n val = X86_CPU(cpu)->env.apic_bus_freq;\n }\n \n- if (!whpx_irqchip_in_kernel() &&\n- vcpu->exit_ctx.MsrAccess.MsrNumber == MSR_IA32_APICBASE) {\n+ if (vcpu->exit_ctx.MsrAccess.MsrNumber == MSR_IA32_APICBASE) {\n is_known_msr = 1;\n if (!vcpu->exit_ctx.MsrAccess.AccessInfo.IsWrite) {\n /* Read path unreachable on Hyper-V */\n@@ -2233,6 +2226,13 @@ int whpx_vcpu_run(CPUState *cpu)\n } else {\n reg_values[2].Reg32 &= ~CPUID_EXT_X2APIC;\n }\n+\n+ /* CPUID[1:EDX].APIC is dynamic */\n+ if (env->features[FEAT_1_EDX] & CPUID_APIC) {\n+ reg_values[3].Reg32 |= CPUID_APIC;\n+ } else {\n+ reg_values[3].Reg32 &= ~CPUID_APIC;\n+ }\n }\n \n /* Dynamic depending on XCR0 and XSS, so query DefaultResult */\n@@ -2804,9 +2804,7 @@ int whpx_accel_init(AccelState *as, MachineState *ms)\n \n memset(&prop, 0, sizeof(WHV_PARTITION_PROPERTY));\n prop.X64MsrExitBitmap.UnhandledMsrs = 1;\n- if (!whpx_irqchip_in_kernel()) {\n- prop.X64MsrExitBitmap.ApicBaseMsrWrite = 1;\n- }\n+ prop.X64MsrExitBitmap.ApicBaseMsrWrite = 1;\n \n hr = whp_dispatch.WHvSetPartitionProperty(\n whpx->partition,\ndiff --git a/target/i386/whpx/whpx-apic.c b/target/i386/whpx/whpx-apic.c\nindex f26ecaf6e83..65629ca45f9 100644\n--- a/target/i386/whpx/whpx-apic.c\n+++ b/target/i386/whpx/whpx-apic.c\n@@ -90,9 +90,70 @@ static void whpx_get_apic_state(APICCommonState *s,\n apic_next_timer(s, s->initial_count_load_time);\n }\n \n-static int whpx_apic_set_base(APICCommonState *s, uint64_t val)\n+static int apic_set_base_check(APICCommonState *s, uint64_t val)\n {\n- s->apicbase = val;\n+ /* Enable x2apic when x2apic is not supported by CPU */\n+ if (!cpu_has_x2apic_feature(&s->cpu->env) &&\n+ val & MSR_IA32_APICBASE_EXTD) {\n+ return -1;\n+ }\n+\n+ /*\n+ * Transition into invalid state\n+ * (s->apicbase & MSR_IA32_APICBASE_ENABLE == 0) &&\n+ * (s->apicbase & MSR_IA32_APICBASE_EXTD) == 1\n+ */\n+ if (!(val & MSR_IA32_APICBASE_ENABLE) &&\n+ (val & MSR_IA32_APICBASE_EXTD)) {\n+ return -1;\n+ }\n+\n+ /* Invalid transition from disabled mode to x2APIC */\n+ if (!(s->apicbase & MSR_IA32_APICBASE_ENABLE) &&\n+ !(s->apicbase & MSR_IA32_APICBASE_EXTD) &&\n+ (val & MSR_IA32_APICBASE_ENABLE) &&\n+ (val & MSR_IA32_APICBASE_EXTD)) {\n+ return -1;\n+ }\n+\n+ /* Invalid transition from x2APIC to xAPIC */\n+ if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) &&\n+ (s->apicbase & MSR_IA32_APICBASE_EXTD) &&\n+ (val & MSR_IA32_APICBASE_ENABLE) &&\n+ !(val & MSR_IA32_APICBASE_EXTD)) {\n+ return -1;\n+ }\n+\n+ return 0;\n+}\n+\n+static int apic_set_base(APICCommonState *s, uint64_t val)\n+{\n+ if (apic_set_base_check(s, val) < 0) {\n+ return -1;\n+ }\n+\n+ s->apicbase = (val & MSR_IA32_APICBASE_BASE) |\n+ (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));\n+ if (!(val & MSR_IA32_APICBASE_ENABLE)) {\n+ s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;\n+ cpu_clear_apic_feature(&s->cpu->env);\n+ }\n+\n+ /* Transition from disabled mode to xAPIC */\n+ if (!(s->apicbase & MSR_IA32_APICBASE_ENABLE) &&\n+ (val & MSR_IA32_APICBASE_ENABLE)) {\n+ s->apicbase |= MSR_IA32_APICBASE_ENABLE;\n+ cpu_set_apic_feature(&s->cpu->env);\n+ }\n+\n+ /* Transition from xAPIC to x2APIC */\n+ if (cpu_has_x2apic_feature(&s->cpu->env) &&\n+ !(s->apicbase & MSR_IA32_APICBASE_EXTD) &&\n+ (val & MSR_IA32_APICBASE_EXTD)) {\n+ s->apicbase |= MSR_IA32_APICBASE_EXTD;\n+ }\n+\n return 0;\n }\n \n@@ -235,6 +296,10 @@ static void whpx_apic_mem_write(void *opaque, hwaddr addr,\n static const MemoryRegionOps whpx_apic_io_ops = {\n .read = whpx_apic_mem_read,\n .write = whpx_apic_mem_write,\n+ .impl.min_access_size = 1,\n+ .impl.max_access_size = 4,\n+ .valid.min_access_size = 1,\n+ .valid.max_access_size = 4,\n .endianness = DEVICE_LITTLE_ENDIAN,\n };\n \n@@ -262,7 +327,7 @@ static void whpx_apic_class_init(ObjectClass *klass, const void *data)\n \n k->realize = whpx_apic_realize;\n k->reset = whpx_apic_reset;\n- k->set_base = whpx_apic_set_base;\n+ k->set_base = apic_set_base;\n k->set_tpr = whpx_apic_set_tpr;\n k->get_tpr = whpx_apic_get_tpr;\n k->post_load = whpx_apic_post_load;\n","prefixes":["PULL","37/58"]}