{"id":2231399,"url":"http://patchwork.ozlabs.org/api/patches/2231399/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260430162855.2029285-1-arnd@kernel.org/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260430162855.2029285-1-arnd@kernel.org>","list_archive_url":null,"date":"2026-04-30T16:28:05","name":"mfd: ezx-pcap: remove unused driver","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"843895231d0ccf6bc459f7f15bee82074d1a7cd0","submitter":{"id":80402,"url":"http://patchwork.ozlabs.org/api/people/80402/?format=json","name":"Arnd Bergmann","email":"arnd@kernel.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260430162855.2029285-1-arnd@kernel.org/mbox/","series":[{"id":502341,"url":"http://patchwork.ozlabs.org/api/series/502341/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=502341","date":"2026-04-30T16:28:05","name":"mfd: ezx-pcap: remove unused driver","version":1,"mbox":"http://patchwork.ozlabs.org/series/502341/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2231399/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2231399/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=FPc9pY3k;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; helo=sin.lore.kernel.org;\n envelope-from=linux-gpio+bounces-35943-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"FPc9pY3k\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sin.lore.kernel.org (sin.lore.kernel.org\n [IPv6:2600:3c15:e001:75::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g60Dk4RHhz1xqf\n\tfor ; Fri, 01 May 2026 02:36:38 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sin.lore.kernel.org (Postfix) with ESMTP id 337BE301AFF9\n\tfor ; Thu, 30 Apr 2026 16:29:04 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id AC1F74219EA;\n\tThu, 30 Apr 2026 16:29:02 +0000 (UTC)","from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D12F427A0B;\n\tThu, 30 Apr 2026 16:29:02 +0000 (UTC)","by smtp.kernel.org (Postfix) with ESMTPSA id 44570C2BCB3;\n\tThu, 30 Apr 2026 16:29:00 +0000 (UTC)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1777566542; cv=none;\n b=ObDtbFNWbn0e822Gav+5zrLYx6fafm3+LrJb/CNNk6gZNaUdjgBA2b+RPsbweMqCS78nq2Rg2KufhViUlOe8RnHogbbrczmE2RgzjYkOPyKAIMYhjYtAzMNGYn3z73bpfhSG4ew0wAtBn9XezK/5MZ6cqtCYDX6TP0n/ybqh7Sc=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1777566542; c=relaxed/simple;\n\tbh=jgRsewY+If+JOuVi7cNItrBcsWY9spq5fwhsPIc4p+Y=;\n\th=From:To:Cc:Subject:Date:Message-Id:MIME-Version;\n b=JGhEHygUKphI3fPZz41SmJaJKBWjOQpXfkRZtK6DmqPtaV09FEcycbampT66rsz4yOovAR1B7NRlZUggvMNioobkmO1dHbw7OQ1vx7zvK6aaMrSKWrL9O3xNvxg4v39PmfTgODhSFgFC4jdSLeaimWvdOQM/BFapIWDGnyhHlgM=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=FPc9pY3k; arc=none smtp.client-ip=10.30.226.201","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1777566542;\n\tbh=jgRsewY+If+JOuVi7cNItrBcsWY9spq5fwhsPIc4p+Y=;\n\th=From:To:Cc:Subject:Date:From;\n\tb=FPc9pY3kp2fDHFzOS0e48pvzF9Q9T/gp/JOe4WSq/4TWzy3EODQHif1cP4THuvKa3\n\t fXQ0YHRgQFUCgNgueHrsgNomVp2mpRZXa/awH4QgB1+FCsEVKclHa5fvnbDXm4BS1X\n\t cBNpLVTojfGK2cdsrInNhnByEsQfjnWpJCuLeNUIwlCl5EchVhauGrdwxY+e/zBzMc\n\t OdJQj/t6Bs5xcKX2HeTTd6iqKxUjqU4idqDiqAOrC6U8n1GE3z2dS96euFxiFLBHEU\n\t T0z/AWDEOoLdG7qbsPc5sEZiB0MKbz0k7FjvXKdTbwsMO8UK5QyD02u1kjVzD/SjUa\n\t Q9CET8ujGq1Mg==","From":"Arnd Bergmann ","To":"Lee Jones ,\n\tLinus Walleij ,\n\tBartosz Golaszewski ","Cc":"Arnd Bergmann ,\n\tkernel test robot ,\n\tHarald Welte ,\n\tlinux-kernel@vger.kernel.org,\n\tlinux-gpio@vger.kernel.org","Subject":"[PATCH] mfd: ezx-pcap: remove unused driver","Date":"Thu, 30 Apr 2026 18:28:05 +0200","Message-Id":"<20260430162855.2029285-1-arnd@kernel.org>","X-Mailer":"git-send-email 2.39.5","Precedence":"bulk","X-Mailing-List":"linux-gpio@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit"},"content":"From: Arnd Bergmann \n\nSupport for the Motorola EZX phones based on Intel PXA processors was\nremoved in 2022, but this driver remained present in the tree. As far\nas I can tell, the support was never quite functional upstream because\nthe board files did not actually instatiate the SPI device for the PCAP.\n\nThere are still also drivers for the various mfd cells: keys, touchscreen,\nregulor and rtc, all of which are obviously orphaned as well but can\nbe removed separately as the Kconfig dependency now prevents them from\nbeing enabled.\n\nReported-by: kernel test robot \nCloses: https://lore.kernel.org/oe-kbuild-all/202604301209.f1YXTsIr-lkp@intel.com/\nCc: Harald Welte \nSigned-off-by: Arnd Bergmann \n---\n drivers/mfd/Kconfig | 7 -\n drivers/mfd/Makefile | 1 -\n drivers/mfd/ezx-pcap.c | 491 -----------------------------------\n include/linux/mfd/ezx-pcap.h | 253 ------------------\n 4 files changed, 752 deletions(-)\n delete mode 100644 drivers/mfd/ezx-pcap.c\n delete mode 100644 include/linux/mfd/ezx-pcap.h","diff":"diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig\nindex 7192c9d1d268..d08d70d41bce 100644\n--- a/drivers/mfd/Kconfig\n+++ b/drivers/mfd/Kconfig\n@@ -1199,13 +1199,6 @@ config MFD_OCELOT\n \n \t If unsure, say N.\n \n-config EZX_PCAP\n-\tbool \"Motorola EZXPCAP Support\"\n-\tdepends on SPI_MASTER\n-\thelp\n-\t This enables the PCAP ASIC present on EZX Phones. This is\n-\t needed for MMC, TouchScreen, Sound, USB, etc..\n-\n config MFD_CPCAP\n \ttristate \"Support for Motorola CPCAP\"\n \tdepends on SPI\ndiff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile\nindex e75e8045c28a..dd4bb7e77c33 100644\n--- a/drivers/mfd/Makefile\n+++ b/drivers/mfd/Makefile\n@@ -131,7 +131,6 @@ obj-$(CONFIG_MFD_CORE)\t\t+= mfd-core.o\n ocelot-soc-objs\t\t\t:= ocelot-core.o ocelot-spi.o\n obj-$(CONFIG_MFD_OCELOT)\t+= ocelot-soc.o\n \n-obj-$(CONFIG_EZX_PCAP)\t\t+= ezx-pcap.o\n obj-$(CONFIG_MFD_CPCAP)\t\t+= motorola-cpcap.o\n \n obj-$(CONFIG_MCP)\t\t+= mcp-core.o\ndiff --git a/drivers/mfd/ezx-pcap.c b/drivers/mfd/ezx-pcap.c\ndeleted file mode 100644\nindex e8b51f630a60..000000000000\n--- a/drivers/mfd/ezx-pcap.c\n+++ /dev/null\n@@ -1,491 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-only\n-/*\n- * Driver for Motorola PCAP2 as present in EZX phones\n- *\n- * Copyright (C) 2006 Harald Welte \n- * Copyright (C) 2009 Daniel Ribeiro \n- */\n-\n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-#include \n-\n-#define PCAP_ADC_MAXQ\t\t8\n-struct pcap_adc_request {\n-\tu8 bank;\n-\tu8 ch[2];\n-\tu32 flags;\n-\tvoid (*callback)(void *, u16[]);\n-\tvoid *data;\n-};\n-\n-struct pcap_chip {\n-\tstruct spi_device *spi;\n-\n-\t/* IO */\n-\tu32 buf;\n-\tspinlock_t io_lock;\n-\n-\t/* IRQ */\n-\tunsigned int irq_base;\n-\tu32 msr;\n-\tstruct work_struct isr_work;\n-\tstruct work_struct msr_work;\n-\tstruct workqueue_struct *workqueue;\n-\n-\t/* ADC */\n-\tstruct pcap_adc_request *adc_queue[PCAP_ADC_MAXQ];\n-\tu8 adc_head;\n-\tu8 adc_tail;\n-\tspinlock_t adc_lock;\n-};\n-\n-/* IO */\n-static int ezx_pcap_putget(struct pcap_chip *pcap, u32 *data)\n-{\n-\tstruct spi_transfer t;\n-\tstruct spi_message m;\n-\tint status;\n-\n-\tmemset(&t, 0, sizeof(t));\n-\tspi_message_init(&m);\n-\tt.len = sizeof(u32);\n-\tspi_message_add_tail(&t, &m);\n-\n-\tpcap->buf = *data;\n-\tt.tx_buf = (u8 *) &pcap->buf;\n-\tt.rx_buf = (u8 *) &pcap->buf;\n-\tstatus = spi_sync(pcap->spi, &m);\n-\n-\tif (status == 0)\n-\t\t*data = pcap->buf;\n-\n-\treturn status;\n-}\n-\n-int ezx_pcap_write(struct pcap_chip *pcap, u8 reg_num, u32 value)\n-{\n-\tunsigned long flags;\n-\tint ret;\n-\n-\tspin_lock_irqsave(&pcap->io_lock, flags);\n-\tvalue &= PCAP_REGISTER_VALUE_MASK;\n-\tvalue |= PCAP_REGISTER_WRITE_OP_BIT\n-\t\t| (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);\n-\tret = ezx_pcap_putget(pcap, &value);\n-\tspin_unlock_irqrestore(&pcap->io_lock, flags);\n-\n-\treturn ret;\n-}\n-EXPORT_SYMBOL_GPL(ezx_pcap_write);\n-\n-int ezx_pcap_read(struct pcap_chip *pcap, u8 reg_num, u32 *value)\n-{\n-\tunsigned long flags;\n-\tint ret;\n-\n-\tspin_lock_irqsave(&pcap->io_lock, flags);\n-\t*value = PCAP_REGISTER_READ_OP_BIT\n-\t\t| (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);\n-\n-\tret = ezx_pcap_putget(pcap, value);\n-\tspin_unlock_irqrestore(&pcap->io_lock, flags);\n-\n-\treturn ret;\n-}\n-EXPORT_SYMBOL_GPL(ezx_pcap_read);\n-\n-int ezx_pcap_set_bits(struct pcap_chip *pcap, u8 reg_num, u32 mask, u32 val)\n-{\n-\tunsigned long flags;\n-\tint ret;\n-\tu32 tmp = PCAP_REGISTER_READ_OP_BIT |\n-\t\t(reg_num << PCAP_REGISTER_ADDRESS_SHIFT);\n-\n-\tspin_lock_irqsave(&pcap->io_lock, flags);\n-\tret = ezx_pcap_putget(pcap, &tmp);\n-\tif (ret)\n-\t\tgoto out_unlock;\n-\n-\ttmp &= (PCAP_REGISTER_VALUE_MASK & ~mask);\n-\ttmp |= (val & mask) | PCAP_REGISTER_WRITE_OP_BIT |\n-\t\t(reg_num << PCAP_REGISTER_ADDRESS_SHIFT);\n-\n-\tret = ezx_pcap_putget(pcap, &tmp);\n-out_unlock:\n-\tspin_unlock_irqrestore(&pcap->io_lock, flags);\n-\n-\treturn ret;\n-}\n-EXPORT_SYMBOL_GPL(ezx_pcap_set_bits);\n-\n-/* IRQ */\n-int irq_to_pcap(struct pcap_chip *pcap, int irq)\n-{\n-\treturn irq - pcap->irq_base;\n-}\n-EXPORT_SYMBOL_GPL(irq_to_pcap);\n-\n-int pcap_to_irq(struct pcap_chip *pcap, int irq)\n-{\n-\treturn pcap->irq_base + irq;\n-}\n-EXPORT_SYMBOL_GPL(pcap_to_irq);\n-\n-static void pcap_mask_irq(struct irq_data *d)\n-{\n-\tstruct pcap_chip *pcap = irq_data_get_irq_chip_data(d);\n-\n-\tpcap->msr |= 1 << irq_to_pcap(pcap, d->irq);\n-\tqueue_work(pcap->workqueue, &pcap->msr_work);\n-}\n-\n-static void pcap_unmask_irq(struct irq_data *d)\n-{\n-\tstruct pcap_chip *pcap = irq_data_get_irq_chip_data(d);\n-\n-\tpcap->msr &= ~(1 << irq_to_pcap(pcap, d->irq));\n-\tqueue_work(pcap->workqueue, &pcap->msr_work);\n-}\n-\n-static struct irq_chip pcap_irq_chip = {\n-\t.name\t\t= \"pcap\",\n-\t.irq_disable\t= pcap_mask_irq,\n-\t.irq_mask\t= pcap_mask_irq,\n-\t.irq_unmask\t= pcap_unmask_irq,\n-};\n-\n-static void pcap_msr_work(struct work_struct *work)\n-{\n-\tstruct pcap_chip *pcap = container_of(work, struct pcap_chip, msr_work);\n-\n-\tezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);\n-}\n-\n-static void pcap_isr_work(struct work_struct *work)\n-{\n-\tstruct pcap_chip *pcap = container_of(work, struct pcap_chip, isr_work);\n-\tstruct pcap_platform_data *pdata = dev_get_platdata(&pcap->spi->dev);\n-\tu32 msr, isr, int_sel, service;\n-\tint irq;\n-\n-\tdo {\n-\t\tezx_pcap_read(pcap, PCAP_REG_MSR, &msr);\n-\t\tezx_pcap_read(pcap, PCAP_REG_ISR, &isr);\n-\n-\t\t/* We can't service/ack irqs that are assigned to port 2 */\n-\t\tif (!(pdata->config & PCAP_SECOND_PORT)) {\n-\t\t\tezx_pcap_read(pcap, PCAP_REG_INT_SEL, &int_sel);\n-\t\t\tisr &= ~int_sel;\n-\t\t}\n-\n-\t\tezx_pcap_write(pcap, PCAP_REG_MSR, isr | msr);\n-\t\tezx_pcap_write(pcap, PCAP_REG_ISR, isr);\n-\n-\t\tservice = isr & ~msr;\n-\t\tfor (irq = pcap->irq_base; service; service >>= 1, irq++) {\n-\t\t\tif (service & 1)\n-\t\t\t\tgeneric_handle_irq_safe(irq);\n-\t\t}\n-\t\tezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);\n-\t} while (gpio_get_value(pdata->gpio));\n-}\n-\n-static void pcap_irq_handler(struct irq_desc *desc)\n-{\n-\tstruct pcap_chip *pcap = irq_desc_get_handler_data(desc);\n-\n-\tdesc->irq_data.chip->irq_ack(&desc->irq_data);\n-\tqueue_work(pcap->workqueue, &pcap->isr_work);\n-}\n-\n-/* ADC */\n-void pcap_set_ts_bits(struct pcap_chip *pcap, u32 bits)\n-{\n-\tunsigned long flags;\n-\tu32 tmp;\n-\n-\tspin_lock_irqsave(&pcap->adc_lock, flags);\n-\tezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);\n-\ttmp &= ~(PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);\n-\ttmp |= bits & (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);\n-\tezx_pcap_write(pcap, PCAP_REG_ADC, tmp);\n-\tspin_unlock_irqrestore(&pcap->adc_lock, flags);\n-}\n-EXPORT_SYMBOL_GPL(pcap_set_ts_bits);\n-\n-static void pcap_disable_adc(struct pcap_chip *pcap)\n-{\n-\tu32 tmp;\n-\n-\tezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);\n-\ttmp &= ~(PCAP_ADC_ADEN|PCAP_ADC_BATT_I_ADC|PCAP_ADC_BATT_I_POLARITY);\n-\tezx_pcap_write(pcap, PCAP_REG_ADC, tmp);\n-}\n-\n-static void pcap_adc_trigger(struct pcap_chip *pcap)\n-{\n-\tunsigned long flags;\n-\tu32 tmp;\n-\tu8 head;\n-\n-\tspin_lock_irqsave(&pcap->adc_lock, flags);\n-\thead = pcap->adc_head;\n-\tif (!pcap->adc_queue[head]) {\n-\t\t/* queue is empty, save power */\n-\t\tpcap_disable_adc(pcap);\n-\t\tspin_unlock_irqrestore(&pcap->adc_lock, flags);\n-\t\treturn;\n-\t}\n-\t/* start conversion on requested bank, save TS_M bits */\n-\tezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);\n-\ttmp &= (PCAP_ADC_TS_M_MASK | PCAP_ADC_TS_REF_LOWPWR);\n-\ttmp |= pcap->adc_queue[head]->flags | PCAP_ADC_ADEN;\n-\n-\tif (pcap->adc_queue[head]->bank == PCAP_ADC_BANK_1)\n-\t\ttmp |= PCAP_ADC_AD_SEL1;\n-\n-\tezx_pcap_write(pcap, PCAP_REG_ADC, tmp);\n-\tspin_unlock_irqrestore(&pcap->adc_lock, flags);\n-\tezx_pcap_write(pcap, PCAP_REG_ADR, PCAP_ADR_ASC);\n-}\n-\n-static irqreturn_t pcap_adc_irq(int irq, void *_pcap)\n-{\n-\tstruct pcap_chip *pcap = _pcap;\n-\tstruct pcap_adc_request *req;\n-\tu16 res[2];\n-\tu32 tmp;\n-\n-\tspin_lock(&pcap->adc_lock);\n-\treq = pcap->adc_queue[pcap->adc_head];\n-\n-\tif (WARN(!req, \"adc irq without pending request\\n\")) {\n-\t\tspin_unlock(&pcap->adc_lock);\n-\t\treturn IRQ_HANDLED;\n-\t}\n-\n-\t/* read requested channels results */\n-\tezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);\n-\ttmp &= ~(PCAP_ADC_ADA1_MASK | PCAP_ADC_ADA2_MASK);\n-\ttmp |= (req->ch[0] << PCAP_ADC_ADA1_SHIFT);\n-\ttmp |= (req->ch[1] << PCAP_ADC_ADA2_SHIFT);\n-\tezx_pcap_write(pcap, PCAP_REG_ADC, tmp);\n-\tezx_pcap_read(pcap, PCAP_REG_ADR, &tmp);\n-\tres[0] = (tmp & PCAP_ADR_ADD1_MASK) >> PCAP_ADR_ADD1_SHIFT;\n-\tres[1] = (tmp & PCAP_ADR_ADD2_MASK) >> PCAP_ADR_ADD2_SHIFT;\n-\n-\tpcap->adc_queue[pcap->adc_head] = NULL;\n-\tpcap->adc_head = (pcap->adc_head + 1) & (PCAP_ADC_MAXQ - 1);\n-\tspin_unlock(&pcap->adc_lock);\n-\n-\t/* pass the results and release memory */\n-\treq->callback(req->data, res);\n-\tkfree(req);\n-\n-\t/* trigger next conversion (if any) on queue */\n-\tpcap_adc_trigger(pcap);\n-\n-\treturn IRQ_HANDLED;\n-}\n-\n-int pcap_adc_async(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[],\n-\t\t\t\t\t\tvoid *callback, void *data)\n-{\n-\tstruct pcap_adc_request *req;\n-\tunsigned long irq_flags;\n-\n-\t/* This will be freed after we have a result */\n-\treq = kmalloc_obj(struct pcap_adc_request);\n-\tif (!req)\n-\t\treturn -ENOMEM;\n-\n-\treq->bank = bank;\n-\treq->flags = flags;\n-\treq->ch[0] = ch[0];\n-\treq->ch[1] = ch[1];\n-\treq->callback = callback;\n-\treq->data = data;\n-\n-\tspin_lock_irqsave(&pcap->adc_lock, irq_flags);\n-\tif (pcap->adc_queue[pcap->adc_tail]) {\n-\t\tspin_unlock_irqrestore(&pcap->adc_lock, irq_flags);\n-\t\tkfree(req);\n-\t\treturn -EBUSY;\n-\t}\n-\tpcap->adc_queue[pcap->adc_tail] = req;\n-\tpcap->adc_tail = (pcap->adc_tail + 1) & (PCAP_ADC_MAXQ - 1);\n-\tspin_unlock_irqrestore(&pcap->adc_lock, irq_flags);\n-\n-\t/* start conversion */\n-\tpcap_adc_trigger(pcap);\n-\n-\treturn 0;\n-}\n-EXPORT_SYMBOL_GPL(pcap_adc_async);\n-\n-/* subdevs */\n-static int pcap_remove_subdev(struct device *dev, void *unused)\n-{\n-\tplatform_device_unregister(to_platform_device(dev));\n-\treturn 0;\n-}\n-\n-static int pcap_add_subdev(struct pcap_chip *pcap,\n-\t\t\t\t\t\tstruct pcap_subdev *subdev)\n-{\n-\tstruct platform_device *pdev;\n-\tint ret;\n-\n-\tpdev = platform_device_alloc(subdev->name, subdev->id);\n-\tif (!pdev)\n-\t\treturn -ENOMEM;\n-\n-\tpdev->dev.parent = &pcap->spi->dev;\n-\tpdev->dev.platform_data = subdev->platform_data;\n-\n-\tret = platform_device_add(pdev);\n-\tif (ret)\n-\t\tplatform_device_put(pdev);\n-\n-\treturn ret;\n-}\n-\n-static void ezx_pcap_remove(struct spi_device *spi)\n-{\n-\tstruct pcap_chip *pcap = spi_get_drvdata(spi);\n-\tunsigned long flags;\n-\tint i;\n-\n-\t/* remove all registered subdevs */\n-\tdevice_for_each_child(&spi->dev, NULL, pcap_remove_subdev);\n-\n-\t/* cleanup ADC */\n-\tspin_lock_irqsave(&pcap->adc_lock, flags);\n-\tfor (i = 0; i < PCAP_ADC_MAXQ; i++)\n-\t\tkfree(pcap->adc_queue[i]);\n-\tspin_unlock_irqrestore(&pcap->adc_lock, flags);\n-\n-\t/* cleanup irqchip */\n-\tfor (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)\n-\t\tirq_set_chip_and_handler(i, NULL, NULL);\n-}\n-\n-static int ezx_pcap_probe(struct spi_device *spi)\n-{\n-\tstruct pcap_platform_data *pdata = dev_get_platdata(&spi->dev);\n-\tstruct pcap_chip *pcap;\n-\tint i, adc_irq;\n-\tint ret;\n-\n-\t/* platform data is required */\n-\tif (!pdata)\n-\t\treturn -ENODEV;\n-\n-\tpcap = devm_kzalloc(&spi->dev, sizeof(*pcap), GFP_KERNEL);\n-\tif (!pcap)\n-\t\treturn -ENOMEM;\n-\n-\tspin_lock_init(&pcap->io_lock);\n-\tspin_lock_init(&pcap->adc_lock);\n-\tINIT_WORK(&pcap->isr_work, pcap_isr_work);\n-\tINIT_WORK(&pcap->msr_work, pcap_msr_work);\n-\tspi_set_drvdata(spi, pcap);\n-\n-\t/* setup spi */\n-\tspi->bits_per_word = 32;\n-\tspi->mode = SPI_MODE_0 | (pdata->config & PCAP_CS_AH ? SPI_CS_HIGH : 0);\n-\tret = spi_setup(spi);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\tpcap->spi = spi;\n-\n-\t/* setup irq */\n-\tpcap->irq_base = pdata->irq_base;\n-\tpcap->workqueue = devm_alloc_ordered_workqueue(&spi->dev, \"pcapd\", 0);\n-\tif (!pcap->workqueue)\n-\t\treturn -ENOMEM;\n-\n-\t/* redirect interrupts to AP, except adcdone2 */\n-\tif (!(pdata->config & PCAP_SECOND_PORT))\n-\t\tezx_pcap_write(pcap, PCAP_REG_INT_SEL,\n-\t\t\t\t\t(1 << PCAP_IRQ_ADCDONE2));\n-\n-\t/* setup irq chip */\n-\tfor (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++) {\n-\t\tirq_set_chip_and_handler(i, &pcap_irq_chip, handle_simple_irq);\n-\t\tirq_set_chip_data(i, pcap);\n-\t\tirq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);\n-\t}\n-\n-\t/* mask/ack all PCAP interrupts */\n-\tezx_pcap_write(pcap, PCAP_REG_MSR, PCAP_MASK_ALL_INTERRUPT);\n-\tezx_pcap_write(pcap, PCAP_REG_ISR, PCAP_CLEAR_INTERRUPT_REGISTER);\n-\tpcap->msr = PCAP_MASK_ALL_INTERRUPT;\n-\n-\tirq_set_irq_type(spi->irq, IRQ_TYPE_EDGE_RISING);\n-\tirq_set_chained_handler_and_data(spi->irq, pcap_irq_handler, pcap);\n-\tirq_set_irq_wake(spi->irq, 1);\n-\n-\t/* ADC */\n-\tadc_irq = pcap_to_irq(pcap, (pdata->config & PCAP_SECOND_PORT) ?\n-\t\t\t\t\tPCAP_IRQ_ADCDONE2 : PCAP_IRQ_ADCDONE);\n-\n-\tret = devm_request_irq(&spi->dev, adc_irq, pcap_adc_irq, 0, \"ADC\",\n-\t\t\t\tpcap);\n-\tif (ret)\n-\t\tgoto free_irqchip;\n-\n-\t/* setup subdevs */\n-\tfor (i = 0; i < pdata->num_subdevs; i++) {\n-\t\tret = pcap_add_subdev(pcap, &pdata->subdevs[i]);\n-\t\tif (ret)\n-\t\t\tgoto remove_subdevs;\n-\t}\n-\n-\t/* board specific quirks */\n-\tif (pdata->init)\n-\t\tpdata->init(pcap);\n-\n-\treturn 0;\n-\n-remove_subdevs:\n-\tdevice_for_each_child(&spi->dev, NULL, pcap_remove_subdev);\n-free_irqchip:\n-\tfor (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)\n-\t\tirq_set_chip_and_handler(i, NULL, NULL);\n-\n-\treturn ret;\n-}\n-\n-static struct spi_driver ezxpcap_driver = {\n-\t.probe\t= ezx_pcap_probe,\n-\t.remove = ezx_pcap_remove,\n-\t.driver = {\n-\t\t.name\t= \"ezx-pcap\",\n-\t},\n-};\n-\n-static int __init ezx_pcap_init(void)\n-{\n-\treturn spi_register_driver(&ezxpcap_driver);\n-}\n-\n-static void __exit ezx_pcap_exit(void)\n-{\n-\tspi_unregister_driver(&ezxpcap_driver);\n-}\n-\n-subsys_initcall(ezx_pcap_init);\n-module_exit(ezx_pcap_exit);\n-\n-MODULE_AUTHOR(\"Daniel Ribeiro / Harald Welte\");\n-MODULE_DESCRIPTION(\"Motorola PCAP2 ASIC Driver\");\n-MODULE_ALIAS(\"spi:ezx-pcap\");\ndiff --git a/include/linux/mfd/ezx-pcap.h b/include/linux/mfd/ezx-pcap.h\ndeleted file mode 100644\nindex ea51b1cdca5a..000000000000\n--- a/include/linux/mfd/ezx-pcap.h\n+++ /dev/null\n@@ -1,253 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0 */\n-/*\n- * Copyright 2009 Daniel Ribeiro \n- *\n- * For further information, please see http://wiki.openezx.org/PCAP2\n- */\n-\n-#ifndef EZX_PCAP_H\n-#define EZX_PCAP_H\n-\n-struct pcap_subdev {\n-\tint id;\n-\tconst char *name;\n-\tvoid *platform_data;\n-};\n-\n-struct pcap_platform_data {\n-\tunsigned int irq_base;\n-\tunsigned int config;\n-\tint gpio;\n-\tvoid (*init) (void *);\t/* board specific init */\n-\tint num_subdevs;\n-\tstruct pcap_subdev *subdevs;\n-};\n-\n-struct pcap_chip;\n-\n-int ezx_pcap_write(struct pcap_chip *, u8, u32);\n-int ezx_pcap_read(struct pcap_chip *, u8, u32 *);\n-int ezx_pcap_set_bits(struct pcap_chip *, u8, u32, u32);\n-int pcap_to_irq(struct pcap_chip *, int);\n-int irq_to_pcap(struct pcap_chip *, int);\n-int pcap_adc_async(struct pcap_chip *, u8, u32, u8[], void *, void *);\n-void pcap_set_ts_bits(struct pcap_chip *, u32);\n-\n-#define PCAP_SECOND_PORT\t1\n-#define PCAP_CS_AH\t\t2\n-\n-#define PCAP_REGISTER_WRITE_OP_BIT\t0x80000000\n-#define PCAP_REGISTER_READ_OP_BIT\t0x00000000\n-\n-#define PCAP_REGISTER_VALUE_MASK\t0x01ffffff\n-#define PCAP_REGISTER_ADDRESS_MASK\t0x7c000000\n-#define PCAP_REGISTER_ADDRESS_SHIFT\t26\n-#define PCAP_REGISTER_NUMBER\t\t32\n-#define PCAP_CLEAR_INTERRUPT_REGISTER\t0x01ffffff\n-#define PCAP_MASK_ALL_INTERRUPT\t\t0x01ffffff\n-\n-/* registers accessible by both pcap ports */\n-#define PCAP_REG_ISR\t\t0x0\t/* Interrupt Status */\n-#define PCAP_REG_MSR\t\t0x1\t/* Interrupt Mask */\n-#define PCAP_REG_PSTAT\t\t0x2\t/* Processor Status */\n-#define PCAP_REG_VREG2\t\t0x6\t/* Regulator Bank 2 Control */\n-#define PCAP_REG_AUXVREG\t0x7\t/* Auxiliary Regulator Control */\n-#define PCAP_REG_BATT\t\t0x8\t/* Battery Control */\n-#define PCAP_REG_ADC\t\t0x9\t/* AD Control */\n-#define PCAP_REG_ADR\t\t0xa\t/* AD Result */\n-#define PCAP_REG_CODEC\t\t0xb\t/* Audio Codec Control */\n-#define PCAP_REG_RX_AMPS\t0xc\t/* RX Audio Amplifiers Control */\n-#define PCAP_REG_ST_DAC\t\t0xd\t/* Stereo DAC Control */\n-#define PCAP_REG_BUSCTRL\t0x14\t/* Connectivity Control */\n-#define PCAP_REG_PERIPH\t\t0x15\t/* Peripheral Control */\n-#define PCAP_REG_LOWPWR\t\t0x18\t/* Regulator Low Power Control */\n-#define PCAP_REG_TX_AMPS\t0x1a\t/* TX Audio Amplifiers Control */\n-#define PCAP_REG_GP\t\t0x1b\t/* General Purpose */\n-#define PCAP_REG_TEST1\t\t0x1c\n-#define PCAP_REG_TEST2\t\t0x1d\n-#define PCAP_REG_VENDOR_TEST1\t0x1e\n-#define PCAP_REG_VENDOR_TEST2\t0x1f\n-\n-/* registers accessible by pcap port 1 only (a1200, e2 & e6) */\n-#define PCAP_REG_INT_SEL\t0x3\t/* Interrupt Select */\n-#define PCAP_REG_SWCTRL\t\t0x4\t/* Switching Regulator Control */\n-#define PCAP_REG_VREG1\t\t0x5\t/* Regulator Bank 1 Control */\n-#define PCAP_REG_RTC_TOD\t0xe\t/* RTC Time of Day */\n-#define PCAP_REG_RTC_TODA\t0xf\t/* RTC Time of Day Alarm */\n-#define PCAP_REG_RTC_DAY\t0x10\t/* RTC Day */\n-#define PCAP_REG_RTC_DAYA\t0x11\t/* RTC Day Alarm */\n-#define PCAP_REG_MTRTMR\t\t0x12\t/* AD Monitor Timer */\n-#define PCAP_REG_PWR\t\t0x13\t/* Power Control */\n-#define PCAP_REG_AUXVREG_MASK\t0x16\t/* Auxiliary Regulator Mask */\n-#define PCAP_REG_VENDOR_REV\t0x17\n-#define PCAP_REG_PERIPH_MASK\t0x19\t/* Peripheral Mask */\n-\n-/* PCAP2 Interrupts */\n-#define PCAP_NIRQS\t\t23\n-#define PCAP_IRQ_ADCDONE\t0\t/* ADC done port 1 */\n-#define PCAP_IRQ_TS\t\t1\t/* Touch Screen */\n-#define PCAP_IRQ_1HZ\t\t2\t/* 1HZ timer */\n-#define PCAP_IRQ_WH\t\t3\t/* ADC above high limit */\n-#define PCAP_IRQ_WL\t\t4\t/* ADC below low limit */\n-#define PCAP_IRQ_TODA\t\t5\t/* Time of day alarm */\n-#define PCAP_IRQ_USB4V\t\t6\t/* USB above 4V */\n-#define PCAP_IRQ_ONOFF\t\t7\t/* On/Off button */\n-#define PCAP_IRQ_ONOFF2\t\t8\t/* On/Off button 2 */\n-#define PCAP_IRQ_USB1V\t\t9\t/* USB above 1V */\n-#define PCAP_IRQ_MOBPORT\t10\n-#define PCAP_IRQ_MIC\t\t11\t/* Mic attach/HS button */\n-#define PCAP_IRQ_HS\t\t12\t/* Headset attach */\n-#define PCAP_IRQ_ST\t\t13\n-#define PCAP_IRQ_PC\t\t14\t/* Power Cut */\n-#define PCAP_IRQ_WARM\t\t15\n-#define PCAP_IRQ_EOL\t\t16\t/* Battery End Of Life */\n-#define PCAP_IRQ_CLK\t\t17\n-#define PCAP_IRQ_SYSRST\t\t18\t/* System Reset */\n-#define PCAP_IRQ_DUMMY\t\t19\n-#define PCAP_IRQ_ADCDONE2\t20\t/* ADC done port 2 */\n-#define PCAP_IRQ_SOFTRESET\t21\n-#define PCAP_IRQ_MNEXB\t\t22\n-\n-/* voltage regulators */\n-#define V1\t\t0\n-#define V2\t\t1\n-#define V3\t\t2\n-#define V4\t\t3\n-#define V5\t\t4\n-#define V6\t\t5\n-#define V7\t\t6\n-#define V8\t\t7\n-#define V9\t\t8\n-#define V10\t\t9\n-#define VAUX1\t\t10\n-#define VAUX2\t\t11\n-#define VAUX3\t\t12\n-#define VAUX4\t\t13\n-#define VSIM\t\t14\n-#define VSIM2\t\t15\n-#define VVIB\t\t16\n-#define SW1\t\t17\n-#define SW2\t\t18\n-#define SW3\t\t19\n-#define SW1S\t\t20\n-#define SW2S\t\t21\n-\n-#define PCAP_BATT_DAC_MASK\t\t0x000000ff\n-#define PCAP_BATT_DAC_SHIFT\t\t0\n-#define PCAP_BATT_B_FDBK\t\t(1 << 8)\n-#define PCAP_BATT_EXT_ISENSE\t\t(1 << 9)\n-#define PCAP_BATT_V_COIN_MASK\t\t0x00003c00\n-#define PCAP_BATT_V_COIN_SHIFT\t\t10\n-#define PCAP_BATT_I_COIN\t\t(1 << 14)\n-#define PCAP_BATT_COIN_CH_EN\t\t(1 << 15)\n-#define PCAP_BATT_EOL_SEL_MASK\t\t0x000e0000\n-#define PCAP_BATT_EOL_SEL_SHIFT\t\t17\n-#define PCAP_BATT_EOL_CMP_EN\t\t(1 << 20)\n-#define PCAP_BATT_BATT_DET_EN\t\t(1 << 21)\n-#define PCAP_BATT_THERMBIAS_CTRL\t(1 << 22)\n-\n-#define PCAP_ADC_ADEN\t\t\t(1 << 0)\n-#define PCAP_ADC_RAND\t\t\t(1 << 1)\n-#define PCAP_ADC_AD_SEL1\t\t(1 << 2)\n-#define PCAP_ADC_AD_SEL2\t\t(1 << 3)\n-#define PCAP_ADC_ADA1_MASK\t\t0x00000070\n-#define PCAP_ADC_ADA1_SHIFT\t\t4\n-#define PCAP_ADC_ADA2_MASK\t\t0x00000380\n-#define PCAP_ADC_ADA2_SHIFT\t\t7\n-#define PCAP_ADC_ATO_MASK\t\t0x00003c00\n-#define PCAP_ADC_ATO_SHIFT\t\t10\n-#define PCAP_ADC_ATOX\t\t\t(1 << 14)\n-#define PCAP_ADC_MTR1\t\t\t(1 << 15)\n-#define PCAP_ADC_MTR2\t\t\t(1 << 16)\n-#define PCAP_ADC_TS_M_MASK\t\t0x000e0000\n-#define PCAP_ADC_TS_M_SHIFT\t\t17\n-#define PCAP_ADC_TS_REF_LOWPWR\t\t(1 << 20)\n-#define PCAP_ADC_TS_REFENB\t\t(1 << 21)\n-#define PCAP_ADC_BATT_I_POLARITY\t(1 << 22)\n-#define PCAP_ADC_BATT_I_ADC\t\t(1 << 23)\n-\n-#define PCAP_ADC_BANK_0\t\t\t0\n-#define PCAP_ADC_BANK_1\t\t\t1\n-/* ADC bank 0 */\n-#define PCAP_ADC_CH_COIN\t\t0\n-#define PCAP_ADC_CH_BATT\t\t1\n-#define PCAP_ADC_CH_BPLUS\t\t2\n-#define PCAP_ADC_CH_MOBPORTB\t\t3\n-#define PCAP_ADC_CH_TEMPERATURE\t\t4\n-#define PCAP_ADC_CH_CHARGER_ID\t\t5\n-#define PCAP_ADC_CH_AD6\t\t\t6\n-/* ADC bank 1 */\n-#define PCAP_ADC_CH_AD7\t\t\t0\n-#define PCAP_ADC_CH_AD8\t\t\t1\n-#define PCAP_ADC_CH_AD9\t\t\t2\n-#define PCAP_ADC_CH_TS_X1\t\t3\n-#define PCAP_ADC_CH_TS_X2\t\t4\n-#define PCAP_ADC_CH_TS_Y1\t\t5\n-#define PCAP_ADC_CH_TS_Y2\t\t6\n-\n-#define PCAP_ADC_T_NOW\t\t\t0\n-#define PCAP_ADC_T_IN_BURST\t\t1\n-#define PCAP_ADC_T_OUT_BURST\t\t2\n-\n-#define PCAP_ADC_ATO_IN_BURST\t\t6\n-#define PCAP_ADC_ATO_OUT_BURST\t\t0\n-\n-#define PCAP_ADC_TS_M_XY\t\t1\n-#define PCAP_ADC_TS_M_PRESSURE\t\t2\n-#define PCAP_ADC_TS_M_PLATE_X\t\t3\n-#define PCAP_ADC_TS_M_PLATE_Y\t\t4\n-#define PCAP_ADC_TS_M_STANDBY\t\t5\n-#define PCAP_ADC_TS_M_NONTS\t\t6\n-\n-#define PCAP_ADR_ADD1_MASK\t\t0x000003ff\n-#define PCAP_ADR_ADD1_SHIFT\t\t0\n-#define PCAP_ADR_ADD2_MASK\t\t0x000ffc00\n-#define PCAP_ADR_ADD2_SHIFT\t\t10\n-#define PCAP_ADR_ADINC1\t\t\t(1 << 20)\n-#define PCAP_ADR_ADINC2\t\t\t(1 << 21)\n-#define PCAP_ADR_ASC\t\t\t(1 << 22)\n-#define PCAP_ADR_ONESHOT\t\t(1 << 23)\n-\n-#define PCAP_BUSCTRL_FSENB\t\t(1 << 0)\n-#define PCAP_BUSCTRL_USB_SUSPEND\t(1 << 1)\n-#define PCAP_BUSCTRL_USB_PU\t\t(1 << 2)\n-#define PCAP_BUSCTRL_USB_PD\t\t(1 << 3)\n-#define PCAP_BUSCTRL_VUSB_EN\t\t(1 << 4)\n-#define PCAP_BUSCTRL_USB_PS\t\t(1 << 5)\n-#define PCAP_BUSCTRL_VUSB_MSTR_EN\t(1 << 6)\n-#define PCAP_BUSCTRL_VBUS_PD_ENB\t(1 << 7)\n-#define PCAP_BUSCTRL_CURRLIM\t\t(1 << 8)\n-#define PCAP_BUSCTRL_RS232ENB\t\t(1 << 9)\n-#define PCAP_BUSCTRL_RS232_DIR\t\t(1 << 10)\n-#define PCAP_BUSCTRL_SE0_CONN\t\t(1 << 11)\n-#define PCAP_BUSCTRL_USB_PDM\t\t(1 << 12)\n-#define PCAP_BUSCTRL_BUS_PRI_ADJ\t(1 << 24)\n-\n-/* leds */\n-#define PCAP_LED0\t\t0\n-#define PCAP_LED1\t\t1\n-#define PCAP_BL0\t\t2\n-#define PCAP_BL1\t\t3\n-#define PCAP_LED_3MA\t\t0\n-#define PCAP_LED_4MA\t\t1\n-#define PCAP_LED_5MA\t\t2\n-#define PCAP_LED_9MA\t\t3\n-#define PCAP_LED_T_MASK\t\t0xf\n-#define PCAP_LED_C_MASK\t\t0x3\n-#define PCAP_BL_MASK\t\t0x1f\n-#define PCAP_BL0_SHIFT\t\t0\n-#define PCAP_LED0_EN\t\t(1 << 5)\n-#define PCAP_LED1_EN\t\t(1 << 6)\n-#define PCAP_LED0_T_SHIFT\t7\n-#define PCAP_LED1_T_SHIFT\t11\n-#define PCAP_LED0_C_SHIFT\t15\n-#define PCAP_LED1_C_SHIFT\t17\n-#define PCAP_BL1_SHIFT\t\t20\n-\n-/* RTC */\n-#define PCAP_RTC_DAY_MASK\t0x3fff\n-#define PCAP_RTC_TOD_MASK\t0xffff\n-#define PCAP_RTC_PC_MASK\t0x7\n-#define SEC_PER_DAY\t\t86400\n-\n-#endif\n","prefixes":[]}