{"id":2231397,"url":"http://patchwork.ozlabs.org/api/patches/2231397/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260430162420.42839-14-18255117159@163.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260430162420.42839-14-18255117159@163.com>","list_archive_url":null,"date":"2026-04-30T16:24:17","name":"[RESEND,13/16] PCI: qcom: Use FIELD_MODIFY()","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"a67ce039e6dab3d85a4b0fe32a37718757f12628","submitter":{"id":89937,"url":"http://patchwork.ozlabs.org/api/people/89937/?format=json","name":"Hans Zhang","email":"18255117159@163.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260430162420.42839-14-18255117159@163.com/mbox/","series":[{"id":502340,"url":"http://patchwork.ozlabs.org/api/series/502340/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=502340","date":"2026-04-30T16:24:06","name":"PCI: Use FIELD_MODIFY() to simplify bitfield operations","version":1,"mbox":"http://patchwork.ozlabs.org/series/502340/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2231397/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2231397/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=163.com header.i=@163.com header.a=rsa-sha256\n header.s=s110527 header.b=IFG78m6c;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; helo=sin.lore.kernel.org;\n envelope-from=linux-pci+bounces-53524-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (1024-bit key) header.d=163.com header.i=@163.com\n header.b=\"IFG78m6c\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=220.197.31.4","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=163.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=163.com"],"Received":["from sin.lore.kernel.org (sin.lore.kernel.org\n [IPv6:2600:3c15:e001:75::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g60BY3kNMz1yGq\n\tfor ; Fri, 01 May 2026 02:34:45 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sin.lore.kernel.org (Postfix) with ESMTP id 79E6B302E209\n\tfor ; Thu, 30 Apr 2026 16:26:20 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 94DCA47DD5B;\n\tThu, 30 Apr 2026 16:25:09 +0000 (UTC)","from m16.mail.163.com (m16.mail.163.com [220.197.31.4])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C5A947D92B;\n\tThu, 30 Apr 2026 16:25:06 +0000 (UTC)","from zhb.. (unknown [])\n\tby gzga-smtp-mtada-g1-2 (Coremail) with SMTP id\n _____wA3Df0_gvNpcypXCg--.51103S7;\n\tFri, 01 May 2026 00:24:34 +0800 (CST)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1777566309; cv=none;\n b=HqtfJ+vQB17nD9EfhUI6b/MCiK0vWjKASo3Ty0iqXv4J31FyWehAvBkATQ1v8JRUF5sd/w6Zklkkv9D5gVWZw/H3UUwBL3vVnKXu7YccHYPV/c4+1/0SW223uWCHAGmNmn7KnUJCEiGnvR4IO0Th89yUtNhh07h6pbt5vsceIy4=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1777566309; c=relaxed/simple;\n\tbh=vZ4uOzaFRCb9PY8JtFYGG0Um0DEUay7WKzS4t7ZqMa0=;\n\th=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:\n\t MIME-Version;\n b=jrq4iw3ATbZoMXr1ecTz+vovkH9mt++2a5tWIgGMzwbZD//eft2SyLfQIMwQXI9F+iOCyXuJZZjvTtwxuRoDnaGyYDWx51B7SV/OTgB6LZO0Q4cU9dVzX82ZkdxWn4opti7gOr/OmCxbr/qe+HisVZQfe8IHv5T85pc0i2xexfE=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=163.com;\n spf=pass smtp.mailfrom=163.com;\n dkim=pass (1024-bit key) header.d=163.com header.i=@163.com\n header.b=IFG78m6c; arc=none smtp.client-ip=220.197.31.4","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com;\n\ts=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=cD\n\tl2ZCPmDUg/728GazbNRHsswC8Xpvy+YlB6anU9tzI=; b=IFG78m6c6ZXsOK5K31\n\tZWx43DnN8XMZnab8e32qJ1aoEEloln6QLsZka3BvPQb/7dVJg5s4EwiR9k1MBtpU\n\tMXmEN03jG7+e3r50jXpztcbkvotEfpfWn028NDoxrKBbCHFSjPUGo31UufNl/E2I\n\t+G0xDWMasjtnzJuZyPa5FoIvg=","From":"Hans Zhang <18255117159@163.com>","To":"bhelgaas@google.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\tjingoohan1@gmail.com","Cc":"robh@kernel.org,\n\ts32@nxp.com,\n\tlinux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tHans Zhang <18255117159@163.com>","Subject":"[RESEND PATCH 13/16] PCI: qcom: Use FIELD_MODIFY()","Date":"Fri, 1 May 2026 00:24:17 +0800","Message-Id":"<20260430162420.42839-14-18255117159@163.com>","X-Mailer":"git-send-email 2.34.1","In-Reply-To":"<20260430162420.42839-1-18255117159@163.com>","References":"<20260430162420.42839-1-18255117159@163.com>","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-CM-TRANSID":"_____wA3Df0_gvNpcypXCg--.51103S7","X-Coremail-Antispam":"1Uf129KBjvJXoWxZr45CFWrXFWDuFy3ury5CFg_yoW7Jw4Upa\n\t48t3Z7JF18tF4UurZIkanrur1F9FsxAw12kanxKanruasFyFZrWa90y3sxtrn7JF4UKFya\n\tk348AFW3GFySyrUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2\n\t9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pRP8nOUUUUU=","X-CM-SenderInfo":"rpryjkyvrrlimvzbiqqrwthudrp/xtbCxAMIq2nzgkNcVAAA33"},"content":"Use FIELD_MODIFY() to remove open-coded bit manipulation.\nNo functional change intended.\n\nSigned-off-by: Hans Zhang <18255117159@163.com>\n---\n drivers/pci/controller/dwc/pcie-qcom-common.c | 40 +++++++------------\n drivers/pci/controller/dwc/pcie-qcom-ep.c | 6 +--\n 2 files changed, 16 insertions(+), 30 deletions(-)","diff":"diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.c b/drivers/pci/controller/dwc/pcie-qcom-common.c\nindex 5aa73c628737..0da73caf2011 100644\n--- a/drivers/pci/controller/dwc/pcie-qcom-common.c\n+++ b/drivers/pci/controller/dwc/pcie-qcom-common.c\n@@ -30,20 +30,15 @@ void qcom_pcie_common_set_equalization(struct dw_pcie *pci)\n \n \t\treg = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);\n \t\treg &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;\n-\t\treg &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;\n-\t\treg |= FIELD_PREP(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK,\n-\t\t\t speed - PCIE_SPEED_8_0GT);\n+\t\tFIELD_MODIFY(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, ®,\n+\t\t\t speed - PCIE_SPEED_8_0GT);\n \t\tdw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg);\n \n \t\treg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF);\n-\t\treg &= ~(GEN3_EQ_FMDC_T_MIN_PHASE23 |\n-\t\t\tGEN3_EQ_FMDC_N_EVALS |\n-\t\t\tGEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA |\n-\t\t\tGEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA);\n-\t\treg |= FIELD_PREP(GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1) |\n-\t\t\tFIELD_PREP(GEN3_EQ_FMDC_N_EVALS, 0xd) |\n-\t\t\tFIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA, 0x5) |\n-\t\t\tFIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA, 0x5);\n+\t\tFIELD_MODIFY(GEN3_EQ_FMDC_T_MIN_PHASE23, ®, 0x1);\n+\t\tFIELD_MODIFY(GEN3_EQ_FMDC_N_EVALS, ®, 0xd);\n+\t\tFIELD_MODIFY(GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA, ®, 0x5);\n+\t\tFIELD_MODIFY(GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA, ®, 0x5);\n \t\tdw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg);\n \n \t\treg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);\n@@ -61,14 +56,10 @@ void qcom_pcie_common_set_16gt_lane_margining(struct dw_pcie *pci)\n \tu32 reg;\n \n \treg = dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_1_OFF);\n-\treg &= ~(MARGINING_MAX_VOLTAGE_OFFSET |\n-\t\tMARGINING_NUM_VOLTAGE_STEPS |\n-\t\tMARGINING_MAX_TIMING_OFFSET |\n-\t\tMARGINING_NUM_TIMING_STEPS);\n-\treg |= FIELD_PREP(MARGINING_MAX_VOLTAGE_OFFSET, 0x24) |\n-\t\tFIELD_PREP(MARGINING_NUM_VOLTAGE_STEPS, 0x78) |\n-\t\tFIELD_PREP(MARGINING_MAX_TIMING_OFFSET, 0x32) |\n-\t\tFIELD_PREP(MARGINING_NUM_TIMING_STEPS, 0x10);\n+\tFIELD_MODIFY(MARGINING_MAX_VOLTAGE_OFFSET, ®, 0x24);\n+\tFIELD_MODIFY(MARGINING_NUM_VOLTAGE_STEPS, ®, 0x78);\n+\tFIELD_MODIFY(MARGINING_MAX_TIMING_OFFSET, ®, 0x32);\n+\tFIELD_MODIFY(MARGINING_NUM_TIMING_STEPS, ®, 0x10);\n \tdw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_1_OFF, reg);\n \n \treg = dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_2_OFF);\n@@ -76,13 +67,10 @@ void qcom_pcie_common_set_16gt_lane_margining(struct dw_pcie *pci)\n \t\tMARGINING_SAMPLE_REPORTING_METHOD |\n \t\tMARGINING_IND_LEFT_RIGHT_TIMING |\n \t\tMARGINING_VOLTAGE_SUPPORTED;\n-\treg &= ~(MARGINING_IND_UP_DOWN_VOLTAGE |\n-\t\tMARGINING_MAXLANES |\n-\t\tMARGINING_SAMPLE_RATE_TIMING |\n-\t\tMARGINING_SAMPLE_RATE_VOLTAGE);\n-\treg |= FIELD_PREP(MARGINING_MAXLANES, pci->num_lanes) |\n-\t\tFIELD_PREP(MARGINING_SAMPLE_RATE_TIMING, 0x3f) |\n-\t\tFIELD_PREP(MARGINING_SAMPLE_RATE_VOLTAGE, 0x3f);\n+\treg &= ~MARGINING_IND_UP_DOWN_VOLTAGE;\n+\tFIELD_MODIFY(MARGINING_MAXLANES, ®, pci->num_lanes);\n+\tFIELD_MODIFY(MARGINING_SAMPLE_RATE_TIMING, ®, 0x3f);\n+\tFIELD_MODIFY(MARGINING_SAMPLE_RATE_VOLTAGE, ®, 0x3f);\n \tdw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_2_OFF, reg);\n }\n EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_lane_margining);\ndiff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c\nindex 257c2bcb5f76..56184e6ca6e6 100644\n--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c\n+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c\n@@ -494,15 +494,13 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)\n \t/* Set the L0s Exit Latency to 2us-4us = 0x6 */\n \toffset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);\n \tval = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);\n-\tval &= ~PCI_EXP_LNKCAP_L0SEL;\n-\tval |= FIELD_PREP(PCI_EXP_LNKCAP_L0SEL, 0x6);\n+\tFIELD_MODIFY(PCI_EXP_LNKCAP_L0SEL, &val, 0x6);\n \tdw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val);\n \n \t/* Set the L1 Exit Latency to be 32us-64 us = 0x6 */\n \toffset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);\n \tval = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);\n-\tval &= ~PCI_EXP_LNKCAP_L1EL;\n-\tval |= FIELD_PREP(PCI_EXP_LNKCAP_L1EL, 0x6);\n+\tFIELD_MODIFY(PCI_EXP_LNKCAP_L1EL, &val, 0x6);\n \tdw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val);\n \n \tdw_pcie_dbi_ro_wr_dis(pci);\n","prefixes":["RESEND","13/16"]}