{"id":2231395,"url":"http://patchwork.ozlabs.org/api/patches/2231395/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260430162420.42839-15-18255117159@163.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260430162420.42839-15-18255117159@163.com>","list_archive_url":null,"date":"2026-04-30T16:24:18","name":"[RESEND,14/16] PCI: dwc: Use FIELD_MODIFY()","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"582d3c52716a4be4b575a9a144fb0641cee44461","submitter":{"id":89937,"url":"http://patchwork.ozlabs.org/api/people/89937/?format=json","name":"Hans Zhang","email":"18255117159@163.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260430162420.42839-15-18255117159@163.com/mbox/","series":[{"id":502340,"url":"http://patchwork.ozlabs.org/api/series/502340/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=502340","date":"2026-04-30T16:24:06","name":"PCI: Use FIELD_MODIFY() to simplify bitfield operations","version":1,"mbox":"http://patchwork.ozlabs.org/series/502340/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2231395/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2231395/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=163.com header.i=@163.com header.a=rsa-sha256\n header.s=s110527 header.b=keShUSEk;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-53526-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (1024-bit key) header.d=163.com header.i=@163.com\n header.b=\"keShUSEk\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=220.197.31.5","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=163.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=163.com"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g60756rw8z1yGq\n\tfor ; Fri, 01 May 2026 02:31:45 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 76988305933E\n\tfor ; Thu, 30 Apr 2026 16:26:32 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id F1CF1477982;\n\tThu, 30 Apr 2026 16:25:15 +0000 (UTC)","from m16.mail.163.com (m16.mail.163.com [220.197.31.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id A7BCB47DD60;\n\tThu, 30 Apr 2026 16:25:03 +0000 (UTC)","from zhb.. (unknown [])\n\tby gzga-smtp-mtada-g1-2 (Coremail) with SMTP id\n _____wA3Df0_gvNpcypXCg--.51103S8;\n\tFri, 01 May 2026 00:24:35 +0800 (CST)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1777566315; cv=none;\n b=Lfk0BFKvEfD+cKYbL9X4m9s/hqUBKuM38GUWM3S2vnbmAw3EOhKk2B9//EFVU5Bi63aqIdDsdOd2EcWFUXXOKbejEs9ZUDDxnWmBcJPC8U2fSw0Ts0LBsz7U9gvuqBV1au+UHsKytDGpA9g5ZRP20dNXnuHY7KDGFIq4qvXnz7Q=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1777566315; c=relaxed/simple;\n\tbh=yQO3BGRmV2kjV7ZOVBoEhN3HcNfDmDzJd7JphAWGMg4=;\n\th=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:\n\t MIME-Version;\n b=LnNKk7c0YSynuoWuZT6+QrZPMt0rxi1ojOmIwUVz755wHo3AniKe6QNoedLEj7Q3MQeKxuVW4Hs2ZTfxbWpBa/vFLyQEXJcORq6briFGXzBUt4Go8YJugcCKIWSPpZqHYD4JuID50b5595XmCDm47suAIhewLp2q+zB8qCAz2r8=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=163.com;\n spf=pass smtp.mailfrom=163.com;\n dkim=pass (1024-bit key) header.d=163.com header.i=@163.com\n header.b=keShUSEk; arc=none smtp.client-ip=220.197.31.5","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com;\n\ts=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=ab\n\tjbWUMg51txoJ4eO3Die4tJLGoUyy9UCj0uefKd21o=; b=keShUSEkoxZscZNARV\n\tqXMhl02SxnOu1o+9iHV3NcO4I5q1dapq1OmuY42zPE/uIklMidooLNwh5kKZT6yT\n\tqW+wNEdVv3m6dH4gCUK7WQpV3gg5VSW7c81PXiilYLSglDTEETq77k4lZkjAhqd0\n\tGGtc5gBVhquW8cVRf1Dkf6V6A=","From":"Hans Zhang <18255117159@163.com>","To":"bhelgaas@google.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\tjingoohan1@gmail.com","Cc":"robh@kernel.org,\n\ts32@nxp.com,\n\tlinux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tHans Zhang <18255117159@163.com>","Subject":"[RESEND PATCH 14/16] PCI: dwc: Use FIELD_MODIFY()","Date":"Fri, 1 May 2026 00:24:18 +0800","Message-Id":"<20260430162420.42839-15-18255117159@163.com>","X-Mailer":"git-send-email 2.34.1","In-Reply-To":"<20260430162420.42839-1-18255117159@163.com>","References":"<20260430162420.42839-1-18255117159@163.com>","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-CM-TRANSID":"_____wA3Df0_gvNpcypXCg--.51103S8","X-Coremail-Antispam":"1Uf129KBjvJXoWxZr4UKFy7Ar13ZrWrAFy7Wrg_yoWrKF4Upa\n\ty5ArySyF1rtr45Z3Z8Za4DuF15X3Z3AFZ7G39ruw1xWFy2vr42qay8Ka4Yyr1fJFW0qry5\n\tKw4jy347GFs8JaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2\n\t9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0pRP8nOUUUUU=","X-CM-SenderInfo":"rpryjkyvrrlimvzbiqqrwthudrp/xtbCxAMIq2nzgkNcawAA3I"},"content":"Use FIELD_MODIFY() to remove open-coded bit manipulation.\nNo functional change intended.\n\nSigned-off-by: Hans Zhang <18255117159@163.com>\n---\n .../controller/dwc/pcie-designware-debugfs.c | 23 +++++++------------\n .../pci/controller/dwc/pcie-designware-ep.c | 3 +--\n drivers/pci/controller/dwc/pcie-designware.c | 3 +--\n 3 files changed, 10 insertions(+), 19 deletions(-)","diff":"diff --git a/drivers/pci/controller/dwc/pcie-designware-debugfs.c b/drivers/pci/controller/dwc/pcie-designware-debugfs.c\nindex d0884253be97..945f8f9b6d0e 100644\n--- a/drivers/pci/controller/dwc/pcie-designware-debugfs.c\n+++ b/drivers/pci/controller/dwc/pcie-designware-debugfs.c\n@@ -265,8 +265,7 @@ static ssize_t lane_detect_write(struct file *file, const char __user *buf,\n \t\treturn ret;\n \n \tval = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_REG);\n-\tval &= ~(LANE_SELECT);\n-\tval |= FIELD_PREP(LANE_SELECT, lane);\n+\tFIELD_MODIFY(LANE_SELECT, &val, lane);\n \tdw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_REG, val);\n \n \treturn count;\n@@ -339,14 +338,10 @@ static ssize_t err_inj_write(struct file *file, const char __user *buf,\n \tval |= ((err_inj_list[pdata->idx].err_inj_type << EINJ_TYPE_SHIFT) & type_mask);\n \tval |= FIELD_PREP(EINJ_COUNT, counter);\n \n-\tif (err_group == 1 || err_group == 4) {\n-\t\tval &= ~(EINJ_VAL_DIFF);\n-\t\tval |= FIELD_PREP(EINJ_VAL_DIFF, val_diff);\n-\t}\n-\tif (err_group == 4) {\n-\t\tval &= ~(EINJ_VC_NUM);\n-\t\tval |= FIELD_PREP(EINJ_VC_NUM, vc_num);\n-\t}\n+\tif (err_group == 1 || err_group == 4)\n+\t\tFIELD_MODIFY(EINJ_VAL_DIFF, &val, val_diff);\n+\tif (err_group == 4)\n+\t\tFIELD_MODIFY(EINJ_VC_NUM, &val, vc_num);\n \n \tdw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + ERR_INJ0_OFF + (0x4 * err_group), val);\n \tdw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + ERR_INJ_ENABLE_REG, (0x1 << err_group));\n@@ -362,9 +357,8 @@ static void set_event_number(struct dwc_pcie_rasdes_priv *pdata,\n \n \tval = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG);\n \tval &= ~EVENT_COUNTER_ENABLE;\n-\tval &= ~(EVENT_COUNTER_GROUP_SELECT | EVENT_COUNTER_EVENT_SELECT);\n-\tval |= FIELD_PREP(EVENT_COUNTER_GROUP_SELECT, event_list[pdata->idx].group_no);\n-\tval |= FIELD_PREP(EVENT_COUNTER_EVENT_SELECT, event_list[pdata->idx].event_no);\n+\tFIELD_MODIFY(EVENT_COUNTER_GROUP_SELECT, &val, event_list[pdata->idx].group_no);\n+\tFIELD_MODIFY(EVENT_COUNTER_EVENT_SELECT, &val, event_list[pdata->idx].event_no);\n \tdw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG, val);\n }\n \n@@ -469,8 +463,7 @@ static ssize_t counter_lane_write(struct file *file, const char __user *buf,\n \tmutex_lock(&rinfo->reg_event_lock);\n \tset_event_number(pdata, pci, rinfo);\n \tval = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG);\n-\tval &= ~(EVENT_COUNTER_LANE_SELECT);\n-\tval |= FIELD_PREP(EVENT_COUNTER_LANE_SELECT, lane);\n+\tFIELD_MODIFY(EVENT_COUNTER_LANE_SELECT, &val, lane);\n \tdw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG, val);\n \tmutex_unlock(&rinfo->reg_event_lock);\n \ndiff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c\nindex d4dc3b24da60..88e7fc3d5e9d 100644\n--- a/drivers/pci/controller/dwc/pcie-designware-ep.c\n+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c\n@@ -707,8 +707,7 @@ static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no,\n \n \treg = ep_func->msi_cap + PCI_MSI_FLAGS;\n \tval = dw_pcie_ep_readw_dbi(ep, func_no, reg);\n-\tval &= ~PCI_MSI_FLAGS_QMASK;\n-\tval |= FIELD_PREP(PCI_MSI_FLAGS_QMASK, mmc);\n+\tFIELD_MODIFY(PCI_MSI_FLAGS_QMASK, &val, mmc);\n \tdw_pcie_dbi_ro_wr_en(pci);\n \tdw_pcie_ep_writew_dbi(ep, func_no, reg, val);\n \tdw_pcie_dbi_ro_wr_dis(pci);\ndiff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c\nindex c11cf61b8319..bcfc7bfcf232 100644\n--- a/drivers/pci/controller/dwc/pcie-designware.c\n+++ b/drivers/pci/controller/dwc/pcie-designware.c\n@@ -938,8 +938,7 @@ static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)\n \n \tcap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);\n \tlnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP);\n-\tlnkcap &= ~PCI_EXP_LNKCAP_MLW;\n-\tlnkcap |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes);\n+\tFIELD_MODIFY(PCI_EXP_LNKCAP_MLW, &lnkcap, num_lanes);\n \tdw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap);\n }\n \n","prefixes":["RESEND","14/16"]}