{"id":2231332,"url":"http://patchwork.ozlabs.org/api/patches/2231332/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/177756498815.8917.12449488721849651971-5@git.sr.ht/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<177756498815.8917.12449488721849651971-5@git.sr.ht>","list_archive_url":null,"date":"2026-04-13T16:27:19","name":"[qemu,v4,5/9] ot_uart: gather similar behaviours togeter in register read and write","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"768f941b79fe45cb5932b1c6e01d0add18a6f156","submitter":{"id":92675,"url":"http://patchwork.ozlabs.org/api/people/92675/?format=json","name":"~lexbaileylowrisc","email":"lexbaileylowrisc@git.sr.ht"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/177756498815.8917.12449488721849651971-5@git.sr.ht/mbox/","series":[{"id":502334,"url":"http://patchwork.ozlabs.org/api/series/502334/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502334","date":"2026-04-14T12:45:41","name":"Update opentitan uart (part of supporting opentitan version 1)","version":4,"mbox":"http://patchwork.ozlabs.org/series/502334/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2231332/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2231332/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=fail reason=\"key not found in DNS\" header.d=git.sr.ht\n header.i=@git.sr.ht header.a=rsa-sha256 header.s=20240113 header.b=p6UWgn57;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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bh=ywww7Nv5Qiuj7CAJWTkw1HmYKvkxUnqP3gKISLYCA3I=;\n c=simple/simple; d=git.sr.ht;\n h=From:Date:Subject:Reply-to:In-Reply-To:To:Cc; q=dns/txt; s=20240113;\n t=1777564993; v=1;\n b=p6UWgn57Zlq//5wvy1aNHLraPrvq7c76HFHRyTje2Og8CPbiBDZWczt81riwt23EhWPN5C7S\n 4ELKdoKhWeB0E4EYYtNV6F8iurBT6n8EkpyF5ptKnl68h3CTrhh6yLhQ91iAYamcEAO2Ggfkfsu\n ArSQOXOXUt5K3uLARMHeG9MQrh18pTsQjJuHuR4jKY6OjppOlK77P0ZN1BL7hNbx/uV7DbnCdZD\n pJC1cDIu+JebKjrHngo5yolLnc+TdVJj9PTVlEOAFANVG93/RCIDaDkNBY6zFEJ0fKIlzLBpVL0\n 1xl9hl0jexdzpHT+XFAKval5OVdbSqxo4tLZ+xhT/kM5g==","From":"~lexbaileylowrisc ","Date":"Mon, 13 Apr 2026 17:27:19 +0100","Subject":"[PATCH qemu v4 5/9] ot_uart: gather similar behaviours togeter in\n register read and write","Message-ID":"<177756498815.8917.12449488721849651971-5@git.sr.ht>","X-Mailer":"git.sr.ht","In-Reply-To":"<177756498815.8917.12449488721849651971-0@git.sr.ht>","To":"qemu-riscv@nongnu.org, Alistair Francis ","Cc":"Paolo Bonzini ,\n =?utf-8?q?Marc-Andr=C3=A9?= Lureau ,\n Palmer Dabbelt , Weiwei Li ,\n Daniel Henrique Barboza ,\n Liu Zhiwei ,\n Chao Liu , qemu-devel@nongnu.org,\n Amit Kumar-Hermosillo ,\n nabihestefan ","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"quoted-printable","MIME-Version":"1.0","Received-SPF":"pass client-ip=46.23.81.152; envelope-from=outgoing@sr.ht;\n helo=mail-a.sr.ht","X-Spam_score_int":"17","X-Spam_score":"1.7","X-Spam_bar":"+","X-Spam_report":"(1.7 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405,\n DKIM_INVALID=0.1, DKIM_SIGNED=0.1, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Reply-To":"~lexbaileylowrisc ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Lex Bailey \n\nthe register read and write functions are each a large switch statement with\nmany similar behaviours in, this is mostly for enabling the use of specific\nregister names inside of log messages. this commit adds a lookup table for\nregister names and uses that instead, allowing much of the code in the register\nread and write functions to be deduplicated.\n\nthe write function was also missing a switch case for R_ALERT_TEST, so I added\nthat in this commit since it has a very simple implementation for now\n\nSigned-off-by: Lex Bailey \n---\n hw/char/ot_uart.c | 103 ++++++++++++++++++++++++----------------------\n 1 file changed, 53 insertions(+), 50 deletions(-)","diff":"diff --git a/hw/char/ot_uart.c b/hw/char/ot_uart.c\nindex 62c182cbed..2247db7110 100644\n--- a/hw/char/ot_uart.c\n+++ b/hw/char/ot_uart.c\n@@ -109,6 +109,26 @@ REG32(TIMEOUT_CTRL, 0x30)\n #define R_LAST_REG (R_TIMEOUT_CTRL)\n #define REGS_COUNT (R_LAST_REG + 1u)\n #define REGS_SIZE (REGS_COUNT * sizeof(uint32_t))\n+#define REG_NAME(_reg_) \\\n+ ((((_reg_) < REGS_COUNT) && REG_NAMES[_reg_]) ? REG_NAMES[_reg_] : \"?\")\n+\n+#define REG_NAME_ENTRY(_reg_) [R_##_reg_] = stringify(_reg_)\n+static const char *REG_NAMES[REGS_COUNT] = {\n+ REG_NAME_ENTRY(INTR_STATE),\n+ REG_NAME_ENTRY(INTR_ENABLE),\n+ REG_NAME_ENTRY(INTR_TEST),\n+ REG_NAME_ENTRY(ALERT_TEST),\n+ REG_NAME_ENTRY(CTRL),\n+ REG_NAME_ENTRY(STATUS),\n+ REG_NAME_ENTRY(RDATA),\n+ REG_NAME_ENTRY(WDATA),\n+ REG_NAME_ENTRY(FIFO_CTRL),\n+ REG_NAME_ENTRY(FIFO_STATUS),\n+ REG_NAME_ENTRY(OVRD),\n+ REG_NAME_ENTRY(VAL),\n+ REG_NAME_ENTRY(TIMEOUT_CTRL),\n+};\n+#undef REG_NAME_ENTRY\n \n static void ot_uart_update_irqs(OtUARTState *s)\n {\n@@ -301,23 +321,14 @@ static uint64_t ot_uart_read(void *opaque, hwaddr addr, unsigned int size)\n OtUARTState *s = opaque;\n uint64_t retvalue = 0;\n \n- switch (addr >> 2) {\n+ hwaddr reg = R32_OFF(addr);\n+ switch (reg) {\n case R_INTR_STATE:\n- retvalue = s->regs[R_INTR_STATE];\n- break;\n case R_INTR_ENABLE:\n- retvalue = s->regs[R_INTR_ENABLE];\n- break;\n- case R_INTR_TEST:\n- qemu_log_mask(LOG_GUEST_ERROR,\n- \"%s: wdata is write only\\n\", __func__);\n- break;\n-\n case R_CTRL:\n- retvalue = s->regs[R_CTRL];\n- break;\n+ case R_FIFO_CTRL:\n case R_STATUS:\n- retvalue = s->regs[R_STATUS];\n+ retvalue = s->regs[reg];\n break;\n \n case R_RDATA:\n@@ -333,14 +344,7 @@ static uint64_t ot_uart_read(void *opaque, hwaddr addr, unsigned int size)\n }\n }\n break;\n- case R_WDATA:\n- qemu_log_mask(LOG_GUEST_ERROR,\n- \"%s: wdata is write only\\n\", __func__);\n- break;\n \n- case R_FIFO_CTRL:\n- retvalue = s->regs[R_FIFO_CTRL];\n- break;\n case R_FIFO_STATUS:\n retvalue = s->regs[R_FIFO_STATUS];\n \n@@ -351,21 +355,21 @@ static uint64_t ot_uart_read(void *opaque, hwaddr addr, unsigned int size)\n \"%s: RX fifos are not supported\\n\", __func__);\n break;\n \n- case R_OVRD:\n- retvalue = s->regs[R_OVRD];\n- qemu_log_mask(LOG_UNIMP,\n- \"%s: ovrd is not supported\\n\", __func__);\n- break;\n case R_VAL:\n- retvalue = s->regs[R_VAL];\n- qemu_log_mask(LOG_UNIMP,\n- \"%s: val is not supported\\n\", __func__);\n- break;\n+ case R_OVRD:\n case R_TIMEOUT_CTRL:\n- retvalue = s->regs[R_TIMEOUT_CTRL];\n+ retvalue = s->regs[reg];\n qemu_log_mask(LOG_UNIMP,\n- \"%s: timeout_ctrl is not supported\\n\", __func__);\n+ \"%s: %s is not supported\\n\", __func__, REG_NAME(reg));\n+ break;\n+\n+ case R_ALERT_TEST:\n+ case R_INTR_TEST:\n+ case R_WDATA:\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"%s: %s is write only\\n\", __func__, REG_NAME(reg));\n break;\n+\n default:\n qemu_log_mask(LOG_GUEST_ERROR,\n \"%s: Bad offset 0x%\"HWADDR_PRIx\"\\n\", __func__, addr);\n@@ -381,7 +385,9 @@ static void ot_uart_write(void *opaque, hwaddr addr, uint64_t val64,\n OtUARTState *s = opaque;\n uint32_t value = val64;\n \n- switch (addr >> 2) {\n+ hwaddr reg = R32_OFF(addr);\n+\n+ switch (reg) {\n case R_INTR_STATE:\n /* Write 1 clear */\n value &= INTR_MASK;\n@@ -398,7 +404,11 @@ static void ot_uart_write(void *opaque, hwaddr addr, uint64_t val64,\n s->regs[R_INTR_STATE] |= value;\n ot_uart_update_irqs(s);\n break;\n-\n+ case R_ALERT_TEST:\n+ value &= R_ALERT_TEST_FATAL_FAULT_MASK;\n+ s->regs[reg] = value;\n+ /* This will also set an IRQ once the alert handler is added */\n+ break;\n case R_CTRL:\n s->regs[R_CTRL] = value;\n \n@@ -434,15 +444,6 @@ static void ot_uart_write(void *opaque, hwaddr addr, uint64_t val64,\n s->char_tx_time = (NANOSECONDS_PER_SECOND / baud) * 10;\n }\n break;\n- case R_STATUS:\n- qemu_log_mask(LOG_GUEST_ERROR,\n- \"%s: status is read only\\n\", __func__);\n- break;\n-\n- case R_RDATA:\n- qemu_log_mask(LOG_GUEST_ERROR,\n- \"%s: rdata is read only\\n\", __func__);\n- break;\n case R_WDATA:\n uart_write_tx_fifo(s, value);\n break;\n@@ -459,10 +460,6 @@ static void ot_uart_write(void *opaque, hwaddr addr, uint64_t val64,\n s->tx_level = 0;\n }\n break;\n- case R_FIFO_STATUS:\n- qemu_log_mask(LOG_GUEST_ERROR,\n- \"%s: fifo_status is read only\\n\", __func__);\n- break;\n case R_OVRD:\n if (value & R_OVRD_TXEN_MASK) {\n qemu_log_mask(LOG_UNIMP, \"%s: OVRD.TXEN is not supported\\n\",\n@@ -470,16 +467,22 @@ static void ot_uart_write(void *opaque, hwaddr addr, uint64_t val64,\n }\n s->regs[R_OVRD] = value & R_OVRD_TXVAL_MASK;\n break;\n- case R_VAL:\n- qemu_log_mask(LOG_GUEST_ERROR,\n- \"%s: val is read only\\n\", __func__);\n- break;\n+\n case R_TIMEOUT_CTRL:\n s->regs[R_TIMEOUT_CTRL] =\n value & (R_TIMEOUT_CTRL_EN_MASK | R_TIMEOUT_CTRL_VAL_MASK);\n qemu_log_mask(LOG_UNIMP,\n \"%s: timeout_ctrl is not supported\\n\", __func__);\n break;\n+\n+ case R_STATUS:\n+ case R_RDATA:\n+ case R_FIFO_STATUS:\n+ case R_VAL:\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"%s: %s is read only\\n\", __func__, REG_NAME(reg));\n+ break;\n+\n default:\n qemu_log_mask(LOG_GUEST_ERROR,\n \"%s: Bad offset 0x%\"HWADDR_PRIx\"\\n\", __func__, addr);\n","prefixes":["qemu","v4","5/9"]}