{"id":2231309,"url":"http://patchwork.ozlabs.org/api/patches/2231309/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/20260430152418.1455141-1-michiel@synopsys.com/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260430152418.1455141-1-michiel@synopsys.com>","list_archive_url":null,"date":"2026-04-30T15:24:18","name":"[v2] RISC-V: Add Synopsys RHX-100 series pipeline description","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"b14fd4ddce5f662eeb62c3f4864571b971b62a25","submitter":{"id":93030,"url":"http://patchwork.ozlabs.org/api/people/93030/?format=json","name":"Michiel Derhaeg","email":"Michiel.Derhaeg@synopsys.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/20260430152418.1455141-1-michiel@synopsys.com/mbox/","series":[{"id":502325,"url":"http://patchwork.ozlabs.org/api/series/502325/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=502325","date":"2026-04-30T15:24:18","name":"[v2] RISC-V: Add Synopsys RHX-100 series pipeline description","version":2,"mbox":"http://patchwork.ozlabs.org/series/502325/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2231309/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2231309/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=synopsys.com header.i=@synopsys.com header.a=rsa-sha256\n header.s=pfptdkimsnps header.b=uA9MTrWE;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=synopsys.com header.i=@synopsys.com header.a=rsa-sha256\n header.s=mail header.b=LPYJUFJ/;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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The RHX-100 features a 10-stage,\ndual-issue, in-order execution pipeline architecture.\n\nIt has support for instruction fusion, which will be addressed by subsequent\npatches. Due to fusion, up to four instructions can be issued in a single\ncycle. It is modeled as four separate pipelines and the issue_rate is set to\nfour.\n\ngcc/ChangeLog:\n\n * config/riscv/riscv-cores.def (RISCV_TUNE): Add arc-v-rhx-100-series.\n * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): Add\n arcv_rhx100.\n * config/riscv/riscv.cc (arcv_rhx100_tune_info): New riscv_tune_param.\n * config/riscv/riscv.md: Add arcv_rhx100 to tune attribute.\n * doc/riscv-mtune.texi: Add RHX-100 documentation.\n * config/riscv/arcv-rhx100.md: New file.\n\nCo-authored-by: Artemiy Volkov \nCo-authored-by: Luis Silva \nSigned-off-by: Michiel Derhaeg \n---\nv2:\n - Added reservation for missing insn types\n - use_divmod_expansion is set to true in tune_info\n - Reservation for arcv_rhx100_fdivsqrt functional unit is clamped to 7 cycles\n - Don't use nothing*N at the end of reservations\n - Some units/reservations were renamed\n\n gcc/config/riscv/arcv-rhx100.md | 120 +++++++++++++++++++++++++++++++\n gcc/config/riscv/riscv-cores.def | 1 +\n gcc/config/riscv/riscv-opts.h | 1 +\n gcc/config/riscv/riscv.cc | 26 +++++++\n gcc/config/riscv/riscv.md | 4 +-\n gcc/doc/riscv-mtune.texi | 2 +\n 6 files changed, 153 insertions(+), 1 deletion(-)\n create mode 100644 gcc/config/riscv/arcv-rhx100.md","diff":"diff --git a/gcc/config/riscv/arcv-rhx100.md b/gcc/config/riscv/arcv-rhx100.md\nnew file mode 100644\nindex 00000000000..da46f714db4\n--- /dev/null\n+++ b/gcc/config/riscv/arcv-rhx100.md\n@@ -0,0 +1,120 @@\n+;; DFA scheduling description of the Synopsys RHX-100 cpu\n+;; for GNU C compiler\n+;; Copyright (C) 2026 Free Software Foundation, Inc.\n+\n+;; This file is part of GCC.\n+\n+;; GCC is free software; you can redistribute it and/or modify\n+;; it under the terms of the GNU General Public License as published by\n+;; the Free Software Foundation; either version 3, or (at your option)\n+;; any later version.\n+\n+;; GCC is distributed in the hope that it will be useful,\n+;; but WITHOUT ANY WARRANTY; without even the implied warranty of\n+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+;; GNU General Public License for more details.\n+\n+;; You should have received a copy of the GNU General Public License\n+;; along with GCC; see the file COPYING3. If not see\n+;; .\n+\n+(define_automaton \"arcv_rhx100\")\n+\n+(define_cpu_unit \"arcv_rhx100_ALU_A_fuse0_early\"\t\"arcv_rhx100\")\n+(define_cpu_unit \"arcv_rhx100_ALU_A_fuse1_early\"\t\"arcv_rhx100\")\n+(define_cpu_unit \"arcv_rhx100_ALU_B_fuse0_early\"\t\"arcv_rhx100\")\n+(define_cpu_unit \"arcv_rhx100_ALU_B_fuse1_early\"\t\"arcv_rhx100\")\n+(define_cpu_unit \"arcv_rhx100_MPY\"\t\"arcv_rhx100\")\n+(define_cpu_unit \"arcv_rhx100_DIV\"\t\"arcv_rhx100\")\n+(define_cpu_unit \"arcv_rhx100_DMP_fuse0\"\t\"arcv_rhx100\")\n+(define_cpu_unit \"arcv_rhx100_DMP_fuse1\"\t\"arcv_rhx100\")\n+(define_cpu_unit \"arcv_rhx100_fdivsqrt\"\t\"arcv_rhx100\")\n+(define_cpu_unit \"arcv_rhx100_issueA_fuse0\" \"arcv_rhx100\")\n+(define_cpu_unit \"arcv_rhx100_issueA_fuse1\" \"arcv_rhx100\")\n+(define_cpu_unit \"arcv_rhx100_issueB_fuse0\" \"arcv_rhx100\")\n+(define_cpu_unit \"arcv_rhx100_issueB_fuse1\" \"arcv_rhx100\")\n+\n+;; Instruction reservation for arithmetic instructions (pipe A, pipe B).\n+(define_insn_reservation \"arcv_rhx100_alu_early_arith\" 1\n+ (and (eq_attr \"tune\" \"arcv_rhx100\")\n+ (eq_attr \"type\" \"unknown,move,const,arith,shift,slt,multi,auipc,nop,logical,\\\n+\t\tbitmanip,min,max,minu,maxu,clz,ctz,atomic,\\\n+\t\tcondmove,mvpair,zicond,cpop,clmul,rotate\"))\n+ \"((arcv_rhx100_issueA_fuse0 + arcv_rhx100_ALU_A_fuse0_early) | (arcv_rhx100_issueA_fuse1 + arcv_rhx100_ALU_A_fuse1_early)) | ((arcv_rhx100_issueB_fuse0 + arcv_rhx100_ALU_B_fuse0_early) | (arcv_rhx100_issueB_fuse1 + arcv_rhx100_ALU_B_fuse1_early))\")\n+\n+(define_insn_reservation \"arcv_rhx100_jmp_insn\" 1\n+ (and (eq_attr \"tune\" \"arcv_rhx100\")\n+ (eq_attr \"type\" \"branch,jump,call,jalr,ret,trap\"))\n+ \"arcv_rhx100_issueA_fuse0 | arcv_rhx100_issueA_fuse1\")\n+\n+(define_insn_reservation \"arcv_rhx100_div_insn\" 12\n+ (and (eq_attr \"tune\" \"arcv_rhx100\")\n+ (eq_attr \"type\" \"idiv\"))\n+ \"arcv_rhx100_issueA_fuse0 + arcv_rhx100_DIV\")\n+\n+(define_insn_reservation \"arcv_rhx100_mpy_insn\" 4\n+ (and (eq_attr \"tune\" \"arcv_rhx100\")\n+ (eq_attr \"type\" \"imul\"))\n+ \"arcv_rhx100_issueA_fuse0 + arcv_rhx100_MPY\")\n+\n+(define_insn_reservation \"arcv_rhx100_load_insn\" 3\n+ (and (eq_attr \"tune\" \"arcv_rhx100\")\n+ (eq_attr \"type\" \"load,fpload\"))\n+ \"(arcv_rhx100_issueB_fuse0 + arcv_rhx100_DMP_fuse0) | (arcv_rhx100_issueB_fuse1 + arcv_rhx100_DMP_fuse1)\")\n+\n+(define_insn_reservation \"arcv_rhx100_store_insn\" 1\n+ (and (eq_attr \"tune\" \"arcv_rhx100\")\n+ (eq_attr \"type\" \"store,fpstore\"))\n+ \"(arcv_rhx100_issueB_fuse0 + arcv_rhx100_DMP_fuse0) | (arcv_rhx100_issueB_fuse1 + arcv_rhx100_DMP_fuse1)\")\n+\n+;; (soft) floating points\n+(define_insn_reservation \"arcv_rhx100_xfer\" 3\n+ (and (eq_attr \"tune\" \"arcv_rhx100\")\n+ (eq_attr \"type\" \"mfc,mtc,fcvt,fcvt_i2f,fcvt_f2i,fmove,fcmp\"))\n+ \"(arcv_rhx100_ALU_A_fuse0_early | arcv_rhx100_ALU_B_fuse0_early)\")\n+\n+(define_insn_reservation \"arcv_rhx100_fmul\" 5\n+ (and (eq_attr \"tune\" \"arcv_rhx100\")\n+ (eq_attr \"type\" \"fadd,fmul,fmadd\"))\n+ \"(arcv_rhx100_ALU_A_fuse0_early | arcv_rhx100_ALU_B_fuse0_early)\")\n+\n+(define_insn_reservation \"arcv_rhx100_fdiv\" 20\n+ (and (eq_attr \"tune\" \"arcv_rhx100\")\n+ (eq_attr \"type\" \"fdiv,fsqrt\"))\n+ \"arcv_rhx100_fdivsqrt*7\")\n+\n+(define_insn_reservation \"arcv_rhx100_unknown\" 5\n+ (and (eq_attr \"tune\" \"arcv_rhx100\")\n+ (eq_attr \"type\" \"vfwalu,vfwcvtftoi,vrol,vmidx,vext,vaeskf1,vfredo,\n+ vector,sfb_alu,vlds,viminmax,vfcmp,vimov,vsmul,vnclip,\n+ vldm,vsetvl_pre,vwsll,vfmerge,vmffs,vclmul,vmpop,wrfrm,\n+ vsha2ms,vidiv,vfncvtitof,vaesef,vldr,vlsegdox,vfwmul,\n+ vfmul,vfredu,crypto,vmalu,vimul,vghsh,vialu,viwmul,\n+ vfcvtftoi,vaalu,vislide1up,vfcvtitof,vfwcvtftof,vgather,\n+ vaesz,vbrev,vshift,vsha2ch,vssegtux,vssegtox,vcompress,\n+ vcpop,vstux,vfncvtftof,vfrecp,vssegts,sf_vfnrclip,\n+ vstox,vstr,vlsegdff,vired,vimovvx,vislide1down,vclz,\n+ vfwredu,rdvl,vlde,vaesem,vsm3me,vmiota,vldux,vlsegde,\n+ vssegte,vfwmaccbf16,vfwredo,vctz,vsm4k,vsshift,vsts,\n+ vmsfs,vfmovvf,vfslide1down,viwred,vslidedown,vfncvtftoi,\n+ vsm3c,vnshift,vfalu,vfsqrt,wrvxrm,vfmuladd,vmov,vsetvl,\n+ vfclass,vsha2cl,vicmp,vldff,vfdiv,vste,vaeskf2,\n+ vfncvtbf16,vandn,vbrev8,vgmul,vaesdm,vlsegdux,vfsgnj,\n+ vfmov,rdfrm,vlsegds,vclmulh,vimuladd,viwalu,vfwmuladd,\n+ vimerge,vror,rdvlenb,vfwcvtitof,vaesdf,viwmuladd,vrev8,\n+ vsm4r,vsalu,vfminmax,vicalu,vslideup,vldox,vstm,\n+ vfwcvtbf16,vfmovfv,vfslide1up,vimovxv,sf_vc,sf_vqmacc,\n+ sf_vc_se\"))\n+ \"(arcv_rhx100_issueA_fuse0 + arcv_rhx100_issueA_fuse1) | (arcv_rhx100_issueB_fuse0 + arcv_rhx100_issueB_fuse1)\")\n+\n+;; Bypasses\n+(define_bypass 1 \"arcv_rhx100_alu_early_arith\" \"arcv_rhx100_store_insn\" \"riscv_store_data_bypass_p\")\n+\n+(define_bypass 1 \"arcv_rhx100_load_insn\" \"arcv_rhx100_store_insn\" \"riscv_store_data_bypass_p\")\n+(define_bypass 1 \"arcv_rhx100_load_insn\" \"arcv_rhx100_alu_early_arith\")\n+(define_bypass 1 \"arcv_rhx100_load_insn\" \"arcv_rhx100_mpy_insn\")\n+(define_bypass 2 \"arcv_rhx100_load_insn\" \"arcv_rhx100_load_insn\")\n+(define_bypass 1 \"arcv_rhx100_load_insn\" \"arcv_rhx100_div_insn\")\n+\n+(define_bypass 3 \"arcv_rhx100_mpy_insn\" \"arcv_rhx100_mpy_insn\")\n+(define_bypass 3 \"arcv_rhx100_mpy_insn\" \"arcv_rhx100_div_insn\")\ndiff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def\nindex 79a460f8176..66f1dc70315 100644\n--- a/gcc/config/riscv/riscv-cores.def\n+++ b/gcc/config/riscv/riscv-cores.def\n@@ -51,6 +51,7 @@ RISCV_TUNE(\"xt-c920v2\", generic, generic_ooo_tune_info)\n RISCV_TUNE(\"xiangshan-nanhu\", xiangshan, xiangshan_nanhu_tune_info)\n RISCV_TUNE(\"xiangshan-kunminghu\", xiangshan, generic_ooo_tune_info)\n RISCV_TUNE(\"spacemit-x60\", spacemit_x60, spacemit_x60_tune_info)\n+RISCV_TUNE(\"arc-v-rhx-100-series\", arcv_rhx100, arcv_rhx100_tune_info)\n RISCV_TUNE(\"generic-ooo\", generic_ooo, generic_ooo_tune_info)\n RISCV_TUNE(\"size\", generic, optimize_size_tune_info)\n RISCV_TUNE(\"mips-p8700\", mips_p8700, mips_p8700_tune_info)\ndiff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h\nindex 1c44bc4e6ec..d4bd4310076 100644\n--- a/gcc/config/riscv/riscv-opts.h\n+++ b/gcc/config/riscv/riscv-opts.h\n@@ -65,6 +65,7 @@ enum riscv_microarchitecture_type {\n andes_23_series,\n andes_45_series,\n spacemit_x60,\n+ arcv_rhx100\n };\n extern enum riscv_microarchitecture_type riscv_microarchitecture;\n \ndiff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc\nindex 97272b4349a..28ec620bf68 100644\n--- a/gcc/config/riscv/riscv.cc\n+++ b/gcc/config/riscv/riscv.cc\n@@ -837,6 +837,32 @@ static const struct riscv_tune_param andes_45_tune_info = {\n true,\t\t\t\t\t\t/* prefer-agnostic. */\n };\n \n+/* Costs to use when optimizing for Synopsys RHX-100. */\n+static const struct riscv_tune_param arcv_rhx100_tune_info = {\n+ {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */\n+ {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */\n+ {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */\n+ {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */\n+ {COSTS_N_INSNS (27), COSTS_N_INSNS (43)}, /* int_div */\n+ 4,\t\t\t\t\t /* issue_rate */\n+ 9,\t\t\t\t\t /* branch_cost */\n+ 2,\t\t\t\t\t /* memory_cost */\n+ 8,\t\t\t\t\t /* fmv_cost */\n+ false,\t\t\t\t /* slow_unaligned_access */\n+ false,\t\t\t\t /* vector_unaligned_access */\n+ true,\t\t\t\t\t /* use_divmod_expansion */\n+ false,\t\t\t\t /* overlap_op_by_pieces */\n+ true,\t\t\t\t\t /* use_zero_stride_load */\n+ false,\t\t\t\t /* speculative_sched_vsetvl */\n+ RISCV_FUSE_NOTHING,\t\t\t /* fusible_ops */\n+ NULL,\t\t\t\t\t /* vector cost */\n+ NULL,\t\t\t\t\t /* function_align */\n+ NULL,\t\t\t\t\t /* jump_align */\n+ NULL,\t\t\t\t\t /* loop_align */\n+ true,\t\t\t\t\t /* prefer-agnostic. */\n+};\n+\n+\n static bool riscv_avoid_shrink_wrapping_separate ();\n static tree riscv_handle_fndecl_attribute (tree *, tree, tree, int, bool *);\n static tree riscv_handle_type_attribute (tree *, tree, tree, int, bool *);\ndiff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md\nindex 6b5f824109e..6576f1fed0b 100644\n--- a/gcc/config/riscv/riscv.md\n+++ b/gcc/config/riscv/riscv.md\n@@ -679,7 +679,8 @@\n ;; Keep this in sync with enum riscv_microarchitecture.\n (define_attr \"tune\"\n \"generic,sifive_7,sifive_p400,sifive_p600,xiangshan,generic_ooo,mips_p8700,\n- tt_ascalon_d8,andes_25_series,andes_23_series,andes_45_series,spacemit_x60\"\n+ tt_ascalon_d8,andes_25_series,andes_23_series,andes_45_series,spacemit_x60,\n+ arcv_rhx100\"\n (const (symbol_ref \"((enum attr_tune) riscv_microarchitecture)\")))\n \n ;; Describe a user's asm statement.\n@@ -5205,3 +5206,4 @@\n (include \"andes-25-series.md\")\n (include \"andes-45-series.md\")\n (include \"spacemit-x60.md\")\n+(include \"arcv-rhx100.md\")\ndiff --git a/gcc/doc/riscv-mtune.texi b/gcc/doc/riscv-mtune.texi\nindex 6865bd6fbf7..6ceb9a93fac 100644\n--- a/gcc/doc/riscv-mtune.texi\n+++ b/gcc/doc/riscv-mtune.texi\n@@ -52,6 +52,8 @@ particular CPU name. Permissible values for this option are:\n \n @samp{spacemit-x60},\n \n+@samp{arc-v-rhx-100-series},\n+\n @samp{generic-ooo},\n \n @samp{size},\n","prefixes":["v2"]}