{"id":2231288,"url":"http://patchwork.ozlabs.org/api/patches/2231288/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260430135838.3438728-3-andre.przywara@arm.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260430135838.3438728-3-andre.przywara@arm.com>","list_archive_url":null,"date":"2026-04-30T13:58:38","name":"[v2,2/2] sunxi: A133: dram: Add NSI arbiter configuration support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"336296445cf96fbfaf91948be22dcc35a831e039","submitter":{"id":61837,"url":"http://patchwork.ozlabs.org/api/people/61837/?format=json","name":"Andre Przywara","email":"andre.przywara@arm.com"},"delegate":{"id":114289,"url":"http://patchwork.ozlabs.org/api/users/114289/?format=json","username":"apritzel","first_name":"Andre","last_name":"Przywara","email":"andre.przywara@arm.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260430135838.3438728-3-andre.przywara@arm.com/mbox/","series":[{"id":502307,"url":"http://patchwork.ozlabs.org/api/series/502307/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=502307","date":"2026-04-30T13:58:36","name":"sunxi: DRAM: rework NSI priority settings","version":2,"mbox":"http://patchwork.ozlabs.org/series/502307/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2231288/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2231288/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256\n header.s=foss header.b=iKBHjy6J;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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Thu, 30 Apr 2026 15:58:49 +0200 (CEST)","from foss.arm.com (foss.arm.com [217.140.110.172])\n by phobos.denx.de (Postfix) with ESMTP id 78D32803C6\n for ; Thu, 30 Apr 2026 15:58:47 +0200 (CEST)","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 50BD632C5;\n Thu, 30 Apr 2026 06:58:41 -0700 (PDT)","from e142021.fritz.box (usa-sjc-mx-foss1.foss.arm.com\n [172.31.20.19])\n by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A820E3F7B4;\n Thu, 30 Apr 2026 06:58:45 -0700 (PDT)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED,\n SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2","DKIM-Signature":"v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss;\n t=1777557526; bh=drWJpcSE0TJcdgZ7vlQSxAWArtbiJCMXBwRn1bvPmw8=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=iKBHjy6JZRmicJsCA62Twj3XuO1tTyKwIqbE4Z6vTZ/n2JfeI6P/Doa5znWhhXeGQ\n MxvcF2wX7aYyAaZiQxBX93gDpLpXjjEvRAAREle85SnVrqdYyqKHEGXsWDze8+/Xfi\n unBKwiimiweyqsyVlwqEl2Wc66EWofDHtiOwFPZ8=","From":"Andre Przywara ","To":"Paul Kocialkowski ,\n\tu-boot@lists.denx.de","Cc":"Jernej Skrabec , Chen-Yu Tsai ,\n linux-sunxi@lists.linux.dev","Subject":"[PATCH v2 2/2] sunxi: A133: dram: Add NSI arbiter configuration\n support","Date":"Thu, 30 Apr 2026 15:58:38 +0200","Message-ID":"<20260430135838.3438728-3-andre.przywara@arm.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260430135838.3438728-1-andre.przywara@arm.com>","References":"<20260430135838.3438728-1-andre.przywara@arm.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"From: Paul Kocialkowski \n\nThe Allwinner DRAM controllers contains logic to assign priorities to\nvarious DRAM DMA masters. Configuring this DRAM port arbitration priority\ncorrectly is important to make sure that critical masters are not starved\nby other less important ones. This is especially the case with the display\nengine that needs to be able to fetch pixels in time for scanout and can\neasily be starved by CPU or GPU access.\n\nAdd support for configuring the NSI arbiter in the A133 DRAM init code,\nusing the recently refactored NSI code already used on the A523.\nThe list and order of available ports are highly SoC-specific and the\ndefault config values are set to match the BSP's defaults.\n\nSigned-off-by: Paul Kocialkowski \n[Andre: using new generic NSI function]\nSigned-off-by: Andre Przywara \nSponsored-by: MEC Electronics GmbH \n---\n .../include/asm/arch-sunxi/cpu_sun50i_h6.h | 4 ++\n .../include/asm/arch-sunxi/dram_sun50i_a133.h | 23 ++++++++++\n arch/arm/mach-sunxi/Makefile | 2 +-\n arch/arm/mach-sunxi/dram_sun50i_a133.c | 43 ++++++++++++++++++-\n 4 files changed, 70 insertions(+), 2 deletions(-)","diff":"diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h\nindex b0f2d3f4656..c31437f9acc 100644\n--- a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h\n+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h\n@@ -17,6 +17,10 @@\n \n #define SUNXI_GIC400_BASE\t\t0x03020000\n \n+#ifdef CONFIG_MACH_SUN50I_A133\n+#define SUNXI_NSI_BASE\t\t\t0x03100000\n+#endif\n+\n #ifdef CONFIG_MACH_SUN50I_H6\n #define SUNXI_DRAM_COM_BASE\t\t0x04002000\n #define SUNXI_DRAM_CTL0_BASE\t\t0x04003000\ndiff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h\nindex 01f2214cd15..1e8e0f7ab96 100644\n--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h\n+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_a133.h\n@@ -24,6 +24,29 @@ static inline int ns_to_t(int nanoseconds)\n \treturn DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);\n }\n \n+enum sunxi_nsi_port {\n+\tSUNXI_NSI_PORT_CPU\t= 0,\n+\tSUNXI_NSI_PORT_GPU,\n+\tSUNXI_NSI_PORT_SD1,\n+\tSUNXI_NSI_PORT_MSTG,\n+\tSUNXI_NSI_PORT_GMAC0,\n+\tSUNXI_NSI_PORT_GMAC1,\n+\tSUNXI_NSI_PORT_USB0,\n+\tSUNXI_NSI_PORT_USB1,\n+\tSUNXI_NSI_PORT_NDFC,\n+\tSUNXI_NSI_PORT_DMAC,\n+\tSUNXI_NSI_PORT_CE,\n+\tSUNXI_NSI_PORT_DE0,\n+\tSUNXI_NSI_PORT_DE1,\n+\tSUNXI_NSI_PORT_VE,\n+\tSUNXI_NSI_PORT_CSI,\n+\tSUNXI_NSI_PORT_ISP,\n+\tSUNXI_NSI_PORT_G2D,\n+\tSUNXI_NSI_PORT_EINK,\n+\tSUNXI_NSI_PORT_IOMMU,\n+\tSUNXI_NSI_PORT_CPUS,\n+};\n+\n /* MBUS part is largely the same as in H6, except for one special register */\n #define MCTL_COM_UNK_008\t0x008\n /* NOTE: This register has the same importance as mctl_ctl->clken in H616 */\ndiff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile\nindex 3ef0113ea43..30cce7d1784 100644\n--- a/arch/arm/mach-sunxi/Makefile\n+++ b/arch/arm/mach-sunxi/Makefile\n@@ -48,7 +48,7 @@ obj-$(CONFIG_DRAM_SUN50I_H6)\t+= dram_sun50i_h6.o dram_dw_helpers.o\n obj-$(CONFIG_DRAM_SUN50I_H6)\t+= dram_timings/\n obj-$(CONFIG_DRAM_SUN50I_H616)\t+= dram_sun50i_h616.o dram_dw_helpers.o\n obj-$(CONFIG_DRAM_SUN50I_H616)\t+= dram_timings/\n-obj-$(CONFIG_DRAM_SUN50I_A133)\t+= dram_sun50i_a133.o\n+obj-$(CONFIG_DRAM_SUN50I_A133)\t+= dram_sun50i_a133.o sunxi_nsi.o\n obj-$(CONFIG_DRAM_SUN50I_A133)\t+= dram_timings/\n obj-$(CONFIG_MACH_SUN55I_A523)\t+= dram_sun55i_a523.o dram_dw_helpers.o sunxi_nsi.o\n obj-$(CONFIG_DRAM_SUN55I_A523)\t+= dram_timings/\ndiff --git a/arch/arm/mach-sunxi/dram_sun50i_a133.c b/arch/arm/mach-sunxi/dram_sun50i_a133.c\nindex ca3e2513c69..433044e1e2b 100644\n--- a/arch/arm/mach-sunxi/dram_sun50i_a133.c\n+++ b/arch/arm/mach-sunxi/dram_sun50i_a133.c\n@@ -21,6 +21,7 @@\n #include \n #include \n #include \n+#include \n #include \n #include \n #include \n@@ -69,6 +70,41 @@ static const u8 phy_init[] = {\n };\n #endif\n \n+static void nsi_set_master_priority(void)\n+{\n+\tstruct {\n+\t\tunsigned int port;\n+\t\tu8 pri;\n+\t\tu8 qos_sel;\n+\t} ports[] = {\n+\t\tNSI_CONF(CPU,\tLOWEST,\t\tINPUT),\n+\t\tNSI_CONF(GPU,\tLOWEST,\t\tINPUT),\n+\t\tNSI_CONF(SD1,\tLOWEST,\t\tOUTPUT),\n+\t\tNSI_CONF(MSTG,\tLOWEST,\t\tOUTPUT),\n+\t\tNSI_CONF(GMAC0,\tLOWEST,\t\tOUTPUT),\n+\t\tNSI_CONF(GMAC1,\tLOWEST,\t\tOUTPUT),\n+\t\tNSI_CONF(USB0,\tLOWEST,\t\tOUTPUT),\n+\t\tNSI_CONF(USB1,\tLOWEST,\t\tOUTPUT),\n+\t\tNSI_CONF(NDFC,\tLOWEST,\t\tOUTPUT),\n+\t\tNSI_CONF(DMAC,\tLOWEST,\t\tOUTPUT),\n+\t\tNSI_CONF(CE,\tLOWEST,\t\tOUTPUT),\n+\t\tNSI_CONF(DE0,\tHIGH,\t\tINPUT),\n+\t\tNSI_CONF(DE1,\tHIGH,\t\tINPUT),\n+\t\tNSI_CONF(VE,\tLOWEST,\t\tINPUT),\n+\t\tNSI_CONF(CSI,\tHIGH,\t\tINPUT),\n+\t\tNSI_CONF(ISP,\tHIGH,\t\tINPUT),\n+\t\tNSI_CONF(G2D,\tLOWEST,\t\tINPUT),\n+\t\tNSI_CONF(EINK,\tLOWEST,\t\tOUTPUT),\n+\t\tNSI_CONF(IOMMU,\tHIGHEST,\tINPUT),\n+\t\tNSI_CONF(CPUS,\tLOWEST,\t\tOUTPUT),\n+\t};\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(ports); i++)\n+\t\tnsi_configure_port(ports[i].port, ports[i].pri,\n+\t\t\t\t ports[i].qos_sel);\n+}\n+\n static void mctl_clk_init(u32 clk)\n {\n \tvoid * const ccm = (void *)SUNXI_CCM_BASE;\n@@ -1205,6 +1241,7 @@ static const struct dram_para para = {\n unsigned long sunxi_dram_init(void)\n {\n \tstruct dram_config config;\n+\tunsigned long size;\n \n \t/* Writing to undocumented SYS_CFG area, according to user manual. */\n \tsetbits_le32(0x03000160, BIT(8));\n@@ -1221,5 +1258,9 @@ unsigned long sunxi_dram_init(void)\n \t 1U << config.bankgrps, 1U << config.ranks,\n \t 16U << config.bus_full_width);\n \n-\treturn calculate_dram_size(&config);\n+\tsize = calculate_dram_size(&config);\n+\n+\tnsi_set_master_priority();\n+\n+\treturn size;\n }\n","prefixes":["v2","2/2"]}