{"id":2231282,"url":"http://patchwork.ozlabs.org/api/patches/2231282/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/20260430132307.231541-1-wangzicong@masscore.cn/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260430132307.231541-1-wangzicong@masscore.cn>","list_archive_url":null,"date":"2026-04-30T13:23:07","name":"[v3] RISC-V: Make tuple vector not tieable to some modes.","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"2d784b3be8514e4ecaa3f52cf64e84922588af22","submitter":{"id":93140,"url":"http://patchwork.ozlabs.org/api/people/93140/?format=json","name":"wangzicong","email":"wangzicong@masscore.cn"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/20260430132307.231541-1-wangzicong@masscore.cn/mbox/","series":[{"id":502305,"url":"http://patchwork.ozlabs.org/api/series/502305/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=502305","date":"2026-04-30T13:23:07","name":"[v3] RISC-V: Make tuple vector not tieable to some modes.","version":3,"mbox":"http://patchwork.ozlabs.org/series/502305/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2231282/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2231282/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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Without \nthis patch some unnecessary type conversions may occur, especially when zvl \nis specified. \nE.g. RVVMF2x4HI and RVVM2DI are tieable in gcc trunk, and when extracting \nan inner vector mode RVVMF2HI from RVVMF2x4HI and zvl is specified, it will \nbe converted to DI, which is not expected. But with same inner modes, e.g. \nRVVM1x4QI and RVVM1QI, they should be tieable.\n\n PR target/124448\n\ngcc/ChangeLog:\n\n * config/riscv/riscv.cc (riscv_modes_tieable_p): Make tuple modes \n not tieable to some modes.\n\ngcc/testsuite/ChangeLog:\n\n * gcc.target/riscv/rvv/autovec/pr124448.c: New test.\n\nSigned-off-by: wangzicong \n---\n gcc/config/riscv/riscv.cc | 27 ++++++++++++++\n .../gcc.target/riscv/rvv/autovec/pr124448.c | 36 +++++++++++++++++++\n 2 files changed, 63 insertions(+)\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr124448.c","diff":"diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc\nindex 615750f07449..65bbaf1a42cb 100644\n--- a/gcc/config/riscv/riscv.cc\n+++ b/gcc/config/riscv/riscv.cc\n@@ -10899,6 +10899,33 @@ riscv_modes_tieable_p (machine_mode mode1, machine_mode mode2)\n E.g. V2SI and DI are not tieable. */\n if (riscv_vector_mode_p (mode1) != riscv_vector_mode_p (mode2))\n return false;\n+\n+ /* We don't allow tuple vector modes to be tied to any vector mode\n+ that has different inner mode. It may cause unnecessary type\n+ conversions.\n+ E.g. RVVMF2x4HI and RVVM2DI are not tieable, but\n+ RVVM1x4QI and RVVM1QI are tieable. */\n+ if (riscv_tuple_mode_p (mode1) || riscv_tuple_mode_p (mode2))\n+ {\n+ machine_mode subpart_mode1, subpart_mode2;\n+ if (riscv_tuple_mode_p (mode1))\n+ {\n+ subpart_mode1 = riscv_vector::get_subpart_mode (mode1);\n+ subpart_mode1 = GET_MODE_INNER (subpart_mode1);\n+ }\n+ else\n+ subpart_mode1 = GET_MODE_INNER (mode1);\n+ if (riscv_tuple_mode_p (mode2))\n+ {\n+ subpart_mode2 = riscv_vector::get_subpart_mode (mode2);\n+ subpart_mode2 = GET_MODE_INNER (subpart_mode2);\n+ }\n+ else\n+ subpart_mode2 = GET_MODE_INNER (mode2);\n+ if (subpart_mode1 != subpart_mode2)\n+ return false;\n+ }\n+\n return (mode1 == mode2\n \t || !(GET_MODE_CLASS (mode1) == MODE_FLOAT\n \t && GET_MODE_CLASS (mode2) == MODE_FLOAT));\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr124448.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr124448.c\nnew file mode 100644\nindex 000000000000..32aa85761885\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr124448.c\n@@ -0,0 +1,36 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-march=rv64gcv_zvl128b -mabi=lp64d -O3 -mrvv-vector-bits=zvl -fdump-rtl-vregs\" } */\n+\n+typedef short int16_t;\n+\n+void dct( int16_t d[16], int16_t dct[16] )\n+{\n+ int16_t tmp[16];\n+ for( int i = 0; i < 4; i++ )\n+ {\n+ int s03 = d[i*4+0] + d[i*4+3];\n+ int s12 = d[i*4+1] + d[i*4+2];\n+ int d03 = d[i*4+0] - d[i*4+3];\n+ int d12 = d[i*4+1] - d[i*4+2];\n+ tmp[0*4+i] = s03 + s12;\n+ tmp[1*4+i] = 2*d03 + d12;\n+ tmp[2*4+i] = s03 - s12;\n+ tmp[3*4+i] = d03 - 2*d12;\n+ }\n+ for( int i = 0; i < 4; i++ )\n+ {\n+ int s03 = tmp[i*4+0] + tmp[i*4+3];\n+ int s12 = tmp[i*4+1] + tmp[i*4+2];\n+ int d03 = tmp[i*4+0] - tmp[i*4+3];\n+ int d12 = tmp[i*4+1] - tmp[i*4+2];\n+\n+ dct[i*4+0] = s03 + s12;\n+ dct[i*4+1] = 2*d03 + d12;\n+ dct[i*4+2] = s03 - s12;\n+ dct[i*4+3] = d03 - 2*d12;\n+ }\n+}\n+\n+/* { dg-final { scan-assembler-times {vsetivli} 1 } } */\n+/* { dg-final { scan-assembler-not {vslidedown\\.vi} } } */\n+/* { dg-final { scan-rtl-dump-not \"\\(subreg:RVVM2DI \\(reg:RVVMF2x4HI\" \"vregs\" } } */\n","prefixes":["v3"]}