{"id":2231239,"url":"http://patchwork.ozlabs.org/api/patches/2231239/?format=json","web_url":"http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260430122602.126722-5-aleksandr.loktionov@intel.com/","project":{"id":46,"url":"http://patchwork.ozlabs.org/api/projects/46/?format=json","name":"Intel Wired Ethernet development","link_name":"intel-wired-lan","list_id":"intel-wired-lan.osuosl.org","list_email":"intel-wired-lan@osuosl.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260430122602.126722-5-aleksandr.loktionov@intel.com>","list_archive_url":null,"date":"2026-04-30T12:26:01","name":"[4/5] ice: fix DPLL pin frequency range in CGU pin descriptors","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"5a49dd7cfa079b3ec34c3b52f922fa833a6be4aa","submitter":{"id":75597,"url":"http://patchwork.ozlabs.org/api/people/75597/?format=json","name":"Aleksandr Loktionov","email":"aleksandr.loktionov@intel.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260430122602.126722-5-aleksandr.loktionov@intel.com/mbox/","series":[{"id":502294,"url":"http://patchwork.ozlabs.org/api/series/502294/?format=json","web_url":"http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=502294","date":"2026-04-30T12:25:58","name":"ice: five small fixes and cleanups","version":1,"mbox":"http://patchwork.ozlabs.org/series/502294/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2231239/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2231239/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=zhpRHLwQ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=140.211.166.136; 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a=\"78689193\"","E=Sophos;i=\"6.23,208,1770624000\"; d=\"scan'208\";a=\"78689193\"","E=Sophos;i=\"6.23,208,1770624000\"; d=\"scan'208\";a=\"233538436\""],"X-ExtLoop1":"1","From":"Aleksandr Loktionov ","To":"intel-wired-lan@lists.osuosl.org, anthony.l.nguyen@intel.com,\n aleksandr.loktionov@intel.com","Cc":"netdev@vger.kernel.org,\n Arkadiusz Kubalewski ","Date":"Thu, 30 Apr 2026 14:26:01 +0200","Message-ID":"<20260430122602.126722-5-aleksandr.loktionov@intel.com>","X-Mailer":"git-send-email 2.52.0","In-Reply-To":"<20260430122602.126722-1-aleksandr.loktionov@intel.com>","References":"<20260430122602.126722-1-aleksandr.loktionov@intel.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Mailman-Original-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1777551971; x=1809087971;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=HeCSJC8AQFIhb51F7c7FJSajP0xoCAzaU8poc4y0+BU=;\n b=VlWdx3PG2xDJQXEmo+ukiQ5ZBsv0bhbaevQKzIF/ImvMhxYvJi9mbjXB\n uDEH1fB9tvnCVvzAu65p0J+Ihjs0ORwbMSWZd0zwzg5dmlm7H4OGmth2a\n vSrSZMzB4LybfDrZtCz9YEq3InFBa4qRL3y54lXZL5fzqa38htfkMFanp\n Cbm2WJy0aY7BNvYCoDLlceZ6GTrxJdf/Ltgz/W70mz0WkdlHT/XtuxouR\n zTAahyANqRvI6YIEPnzmApl3WQIFj6+kstdJ33V4mbVFeTNZrzSwl3bTS\n NNldqyHV9SuYPJhU845KicF7pF3Dc8QJQwrjKRUDbDVrIRWf3Swwq6TRl\n A==;","X-Mailman-Original-Authentication-Results":["smtp2.osuosl.org;\n dmarc=pass (p=none dis=none)\n header.from=intel.com","smtp2.osuosl.org;\n dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com\n header.a=rsa-sha256 header.s=Intel header.b=VlWdx3PG"],"Subject":"[Intel-wired-lan] [PATCH 4/5] ice: fix DPLL pin frequency range in\n CGU pin descriptors","X-BeenThere":"intel-wired-lan@osuosl.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Intel Wired Ethernet Linux Kernel Driver Development\n ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"intel-wired-lan-bounces@osuosl.org","Sender":"\"Intel-wired-lan\" "},"content":"From: Arkadiusz Kubalewski \n\nReplace the per-type frequency tables (ice_cgu_pin_freq_1_hz and\nice_cgu_pin_freq_10_mhz) and the two-entry ice_cgu_pin_freq_common array\nwith a named range constant ICE_CGU_MAX_FREQ_HZ (25 MHz), a new\nice_cgu_pin_freq_range array containing DPLL_PIN_FREQUENCY_RANGE(1,\nICE_CGU_MAX_FREQ_HZ), and a separate ice_cgu_pin_freq_gnss array that\nretains DPLL_PIN_FREQUENCY_1PPS for GNSS input pins.\n\nThe hardware firmware spec defines an any_freq capability for CGU inputs\n(ICE_AQC_GET_CGU_IN_CFG_FLG1_ANYFREQ), but the static pin descriptor\ntables constrained configurable pins to 1PPS or 10MHz, preventing users\nfrom setting valid intermediate frequencies. Use a range entry so the\nDPLL netlink interface correctly reflects what the firmware will accept.\nThe firmware validates the actual value and rejects out-of-range requests.\n\nMUX, SyncE ETH port, and configurable EXT pins now advertise the full\nfrequency range, matching the hardware capability. GNSS input pins retain\nthe 1PPS-only advertisement since a GNSS receiver is physically\nconstrained to 1 Hz.\n\nFixes: 6db5f2cd9ebb (\"ice: dpll: fix output pin capabilities\")\nSigned-off-by: Arkadiusz Kubalewski \nSigned-off-by: Aleksandr Loktionov \n---\n drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 128 +++++++++++---------\n 1 file changed, 72 insertions(+), 56 deletions(-)","diff":"diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c\nindex 7b1b402..3949138 100644\n--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c\n+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c\n@@ -7,127 +7,143 @@\n #include \"ice_ptp_hw.h\"\n #include \"ice_ptp_consts.h\"\n \n-static struct dpll_pin_frequency ice_cgu_pin_freq_common[] = {\n-\tDPLL_PIN_FREQUENCY_1PPS,\n-\tDPLL_PIN_FREQUENCY_10MHZ,\n-};\n+/* Maximum frequency supported by CGU pins, in Hz */\n+#define ICE_CGU_MAX_FREQ_HZ\t25000000\n \n-static struct dpll_pin_frequency ice_cgu_pin_freq_1_hz[] = {\n-\tDPLL_PIN_FREQUENCY_1PPS,\n+static struct dpll_pin_frequency ice_cgu_pin_freq_range[] = {\n+\tDPLL_PIN_FREQUENCY_RANGE(1, ICE_CGU_MAX_FREQ_HZ),\n };\n \n-static struct dpll_pin_frequency ice_cgu_pin_freq_10_mhz[] = {\n-\tDPLL_PIN_FREQUENCY_10MHZ,\n+static struct dpll_pin_frequency ice_cgu_pin_freq_gnss[] = {\n+\tDPLL_PIN_FREQUENCY_1PPS,\n };\n \n static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_inputs[] = {\n \t{ \"CVL-SDP22\",\t ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,\n-\t\tARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n \t{ \"CVL-SDP20\",\t ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,\n-\t\tARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },\n-\t{ \"C827_0-RCLKA\", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, },\n-\t{ \"C827_0-RCLKB\", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, },\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n+\t{ \"C827_0-RCLKA\", ZL_REF1P, DPLL_PIN_TYPE_MUX,\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n+\t{ \"C827_0-RCLKB\", ZL_REF1N, DPLL_PIN_TYPE_MUX,\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n \t{ \"SMA1\",\t ZL_REF3P, DPLL_PIN_TYPE_EXT,\n-\t\tARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n \t{ \"SMA2/U.FL2\",\t ZL_REF3N, DPLL_PIN_TYPE_EXT,\n-\t\tARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n \t{ \"GNSS-1PPS\",\t ZL_REF4P, DPLL_PIN_TYPE_GNSS,\n-\t\tARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_gnss), ice_cgu_pin_freq_gnss },\n };\n \n static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_inputs[] = {\n \t{ \"CVL-SDP22\",\t ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,\n-\t\tARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n \t{ \"CVL-SDP20\",\t ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,\n-\t\tARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },\n-\t{ \"C827_0-RCLKA\", ZL_REF1P, DPLL_PIN_TYPE_MUX, },\n-\t{ \"C827_0-RCLKB\", ZL_REF1N, DPLL_PIN_TYPE_MUX, },\n-\t{ \"C827_1-RCLKA\", ZL_REF2P, DPLL_PIN_TYPE_MUX, },\n-\t{ \"C827_1-RCLKB\", ZL_REF2N, DPLL_PIN_TYPE_MUX, },\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n+\t{ \"C827_0-RCLKA\", ZL_REF1P, DPLL_PIN_TYPE_MUX,\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n+\t{ \"C827_0-RCLKB\", ZL_REF1N, DPLL_PIN_TYPE_MUX,\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n+\t{ \"C827_1-RCLKA\", ZL_REF2P, DPLL_PIN_TYPE_MUX,\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n+\t{ \"C827_1-RCLKB\", ZL_REF2N, DPLL_PIN_TYPE_MUX,\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n \t{ \"SMA1\",\t ZL_REF3P, DPLL_PIN_TYPE_EXT,\n-\t\tARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n \t{ \"SMA2/U.FL2\",\t ZL_REF3N, DPLL_PIN_TYPE_EXT,\n-\t\tARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n \t{ \"GNSS-1PPS\",\t ZL_REF4P, DPLL_PIN_TYPE_GNSS,\n-\t\tARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_gnss), ice_cgu_pin_freq_gnss },\n };\n \n static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_outputs[] = {\n \t{ \"REF-SMA1\",\t ZL_OUT0, DPLL_PIN_TYPE_EXT,\n-\t\tARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n \t{ \"REF-SMA2/U.FL2\", ZL_OUT1, DPLL_PIN_TYPE_EXT,\n-\t\tARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },\n-\t{ \"PHY-CLK\",\t ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, },\n-\t{ \"MAC-CLK\",\t ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, },\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n+\t{ \"PHY-CLK\",\t ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT,\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n+\t{ \"MAC-CLK\",\t ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT,\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n \t{ \"CVL-SDP21\",\t ZL_OUT4, DPLL_PIN_TYPE_EXT,\n-\t\tARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n \t{ \"CVL-SDP23\",\t ZL_OUT5, DPLL_PIN_TYPE_EXT,\n-\t\tARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n };\n \n static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_outputs[] = {\n \t{ \"REF-SMA1\",\t ZL_OUT0, DPLL_PIN_TYPE_EXT,\n-\t\tARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n \t{ \"REF-SMA2/U.FL2\", ZL_OUT1, DPLL_PIN_TYPE_EXT,\n-\t\tARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },\n-\t{ \"PHY-CLK\",\t ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },\n-\t{ \"PHY2-CLK\",\t ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },\n-\t{ \"MAC-CLK\",\t ZL_OUT4, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n+\t{ \"PHY-CLK\",\t ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT,\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n+\t{ \"PHY2-CLK\",\t ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT,\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n+\t{ \"MAC-CLK\",\t ZL_OUT4, DPLL_PIN_TYPE_SYNCE_ETH_PORT,\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n \t{ \"CVL-SDP21\",\t ZL_OUT5, DPLL_PIN_TYPE_EXT,\n-\t\tARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n \t{ \"CVL-SDP23\",\t ZL_OUT6, DPLL_PIN_TYPE_EXT,\n-\t\tARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n };\n \n static const struct ice_cgu_pin_desc ice_e823_si_cgu_inputs[] = {\n \t{ \"NONE\",\t SI_REF0P, 0, 0 },\n \t{ \"NONE\",\t SI_REF0N, 0, 0 },\n-\t{ \"SYNCE0_DP\",\t SI_REF1P, DPLL_PIN_TYPE_MUX, 0 },\n-\t{ \"SYNCE0_DN\",\t SI_REF1N, DPLL_PIN_TYPE_MUX, 0 },\n+\t{ \"SYNCE0_DP\",\t SI_REF1P, DPLL_PIN_TYPE_MUX,\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n+\t{ \"SYNCE0_DN\",\t SI_REF1N, DPLL_PIN_TYPE_MUX,\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n \t{ \"EXT_CLK_SYNC\", SI_REF2P, DPLL_PIN_TYPE_EXT,\n-\t\tARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n \t{ \"NONE\",\t SI_REF2N, 0, 0 },\n \t{ \"EXT_PPS_OUT\", SI_REF3, DPLL_PIN_TYPE_EXT,\n-\t\tARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n \t{ \"INT_PPS_OUT\", SI_REF4, DPLL_PIN_TYPE_EXT,\n-\t\tARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n };\n \n static const struct ice_cgu_pin_desc ice_e823_si_cgu_outputs[] = {\n \t{ \"1588-TIME_SYNC\", SI_OUT0, DPLL_PIN_TYPE_EXT,\n-\t\tARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },\n-\t{ \"PHY-CLK\",\t SI_OUT1, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n+\t{ \"PHY-CLK\",\t SI_OUT1, DPLL_PIN_TYPE_SYNCE_ETH_PORT,\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n \t{ \"10MHZ-SMA2\",\t SI_OUT2, DPLL_PIN_TYPE_EXT,\n-\t\tARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz },\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n \t{ \"PPS-SMA1\",\t SI_OUT3, DPLL_PIN_TYPE_EXT,\n-\t\tARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n };\n \n static const struct ice_cgu_pin_desc ice_e823_zl_cgu_inputs[] = {\n \t{ \"NONE\",\t ZL_REF0P, 0, 0 },\n \t{ \"INT_PPS_OUT\", ZL_REF0N, DPLL_PIN_TYPE_EXT,\n-\t\tARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },\n-\t{ \"SYNCE0_DP\",\t ZL_REF1P, DPLL_PIN_TYPE_MUX, 0 },\n-\t{ \"SYNCE0_DN\",\t ZL_REF1N, DPLL_PIN_TYPE_MUX, 0 },\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n+\t{ \"SYNCE0_DP\",\t ZL_REF1P, DPLL_PIN_TYPE_MUX,\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n+\t{ \"SYNCE0_DN\",\t ZL_REF1N, DPLL_PIN_TYPE_MUX,\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n \t{ \"NONE\",\t ZL_REF2P, 0, 0 },\n \t{ \"NONE\",\t ZL_REF2N, 0, 0 },\n \t{ \"EXT_CLK_SYNC\", ZL_REF3P, DPLL_PIN_TYPE_EXT,\n-\t\tARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n \t{ \"NONE\",\t ZL_REF3N, 0, 0 },\n \t{ \"EXT_PPS_OUT\", ZL_REF4P, DPLL_PIN_TYPE_EXT,\n-\t\tARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n \t{ \"OCXO\",\t ZL_REF4N, DPLL_PIN_TYPE_INT_OSCILLATOR, 0 },\n };\n \n static const struct ice_cgu_pin_desc ice_e823_zl_cgu_outputs[] = {\n \t{ \"PPS-SMA1\",\t ZL_OUT0, DPLL_PIN_TYPE_EXT,\n-\t\tARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n \t{ \"10MHZ-SMA2\",\t ZL_OUT1, DPLL_PIN_TYPE_EXT,\n-\t\tARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz },\n-\t{ \"PHY-CLK\",\t ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },\n-\t{ \"1588-TIME_REF\", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n+\t{ \"PHY-CLK\",\t ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT,\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n+\t{ \"1588-TIME_REF\", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT,\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n \t{ \"CPK-TIME_SYNC\", ZL_OUT4, DPLL_PIN_TYPE_EXT,\n-\t\tARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },\n+\t\tARRAY_SIZE(ice_cgu_pin_freq_range), ice_cgu_pin_freq_range },\n \t{ \"NONE\",\t ZL_OUT5, 0, 0 },\n };\n \n","prefixes":["4/5"]}